WO1997006564A1 - Dispositif a semiconducteur et procede de fabrication - Google Patents

Dispositif a semiconducteur et procede de fabrication Download PDF

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Publication number
WO1997006564A1
WO1997006564A1 PCT/JP1996/002184 JP9602184W WO9706564A1 WO 1997006564 A1 WO1997006564 A1 WO 1997006564A1 JP 9602184 W JP9602184 W JP 9602184W WO 9706564 A1 WO9706564 A1 WO 9706564A1
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WIPO (PCT)
Prior art keywords
semiconductor device
concentration
region
diffusion layer
conductivity type
Prior art date
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PCT/JP1996/002184
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English (en)
Japanese (ja)
Inventor
Masatada Horiuchi
Takahide Ikeda
Ken Yamaguchi
Tohru Nakamura
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Hitachi, Ltd.
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Publication of WO1997006564A1 publication Critical patent/WO1997006564A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a high-performance MOS field-effect transistor formed on an insulating film and capable of operating at high speed with low parasitic capacitance, and a method of manufacturing the same.
  • MOS MOS field effect transistor
  • Si single crystal silicon
  • FIG. 1 4 is an isolation insulating film
  • 5 is a gate insulating film
  • 61 is a gate electrode
  • 7 is a gate protective insulating film
  • 8 is a gate sidewall insulating film
  • 9 and 10 are n-type high concentration diffusion layers.
  • the SO I'MOS as shown in Fig. 1 has a feature that the drain junction capacitance and wiring parasitic capacitance can be reduced to about 1Z10 compared to the conventional MOS because it has a thick insulating film 2 directly underneath. . Furthermore, since the MOS is insulated and separated from the substrate, it has features such as malfunction due to ⁇ -ray irradiation and radical phenomena can be fundamentally eliminated.
  • the disadvantage of the conventional SOI'MOS is that the single-crystal Si film 3 is insulated from the supporting substrate 1, and thus is transiently accumulated in the minority carrier force single-crystal Si film 3 generated by a strong electric field at the drain.
  • the threshold voltage fluctuates, which is the so-called substrate floating effect.
  • This effect is also a parasitic bipolar effect in which minority carriers are accumulated in the single-crystal Si film 3 and the potential rises due to an increase in the source force.
  • nMOS n-conductivity SOI • MOS
  • holes are accumulated, the threshold voltage fluctuates in the negative direction, a specific bump is observed in the current-voltage characteristics, and the leakage current increases in the off state. Further, the breakdown voltage between the source and the drain is reduced.
  • the substrate floating effect may be a fatal drawback for differential amplifiers and analog circuits that require detection of small current differences. There is.
  • S 0 I ⁇ MOS in Fig. 1 is a structure proposed to eliminate the substrate floating effect, and the germanium (Ge) ion implantation in the source diffusion layer 9 is performed with the Ge component ratio. About 10% of SiGe mixed crystal 16 is formed.
  • FIG. 2 is an energy band diagram along the channel in a state where the drain voltage Vds is applied in the SOI ′ MOS of FIG.
  • E f n is the pseudo-Furmi level
  • E i is the intrinsic Fermi level.
  • the introduction of Si Ge mixed crystal 16 narrows the band gap by about 0.1 leV, and the valence band Ev at the source is configured as shown by the broken line.
  • the diffusion potential difference for holes near the source is reduced.
  • the conduction band Ec is not affected by the Si Ge mixed crystal, and it is said that the behavior of electrons as majority carriers has no adverse effect.
  • An object of the present invention is to consider the fact that the structure shown in FIG. 1 is effective only for nMOS in eliminating the substrate floating effect of S 0 I ⁇ MOS, and therefore, p-type MOS (hereinafter abbreviated as pMOS), and An object of the present invention is to provide a substrate floating effect eliminating structure applicable to complementary MOS (hereinafter abbreviated as CMOS).
  • CMOS complementary MOS
  • Another object of the present invention is to solve the problem of the Ge ion implantation step which is essential for the formation of Si Ge mixed crystals.
  • GeH 4 germane
  • GeH 4 is usually used as an ion source for Ge ion implantation, but GeH 4 is a very easily decomposable substance, and it is difficult to supply implanted ions stably.
  • An object of the present invention is to provide a substrate floating effect eliminating structure which can be manufactured only by an existing sharable semiconductor manufacturing apparatus, and is therefore manufactured at a low cost.
  • the substrate floating effect is based on the parasitic bipolar effect using the drain and the substrate as the emitter and the base, the substrate has the current amplification factor larger than the bipolar current amplification factor, and the substrate is connected to the emitter.
  • the formation of a second parasitic bipolar in the source diffusion layer eliminates the accumulation of minority carriers on the substrate.
  • FIG. 3 is an impurity distribution diagram in the depth direction of the source diffusion layer in one embodiment of the present semiconductor device. It is assumed that the bottom of the source diffusion layer is separated from the outside by a buried oxide film.
  • a high concentration p-type diffusion layer is formed in an n-type source.
  • a relatively low-concentration first n-type impurity layer is formed by ion implantation of phosphorus (P) and subsequent heat treatment to reach the bottom of the source diffusion layer. From this state, ions of high concentration boron (B) and further high concentration of arsenic (As) are implanted to form an npn impurity distribution from the surface. The same impurity distribution is formed in the drain region as in the source.
  • P phosphorus
  • As arsenic
  • FIG. 4A is an energy band diagram for the nMOS having the above impurity distribution, in which the drain voltage Vds is applied.
  • the solid lines indicate the valence band Ev and the conduction band Ec in the channel formation region on the SOI surface, and the broken lines indicate the energy bands near the p-type diffusion layer separated from the outside.
  • Holes generated near the drain due to the strong electric field at the drain and accumulated in the p-type single-crystal Si film under the channel pass through the low-concentration P substrate under the channel through the p-type diffusion formed in the emitter P-E and source.
  • the conduction is controlled by a pnp transistor whose region is the collector P + c and whose n-type diffusion region is the base nB between the two regions.
  • FIG. 4B is an equivalent circuit diagram showing the vicinity of the source for explaining the operation principle of the pnp transistor.
  • the collector current density J is expressed by the following equation.
  • Equation 1 N B - W B is 1 0 1 2 value of about the normal transistor is referred base region number of carriers and Gummel number.
  • q is the electron charge amount
  • D n are diffusion coefficients
  • n is the intrinsic density
  • N B is Akuseputa impurity density in the base
  • W B Habe Ichisu width
  • V BE Habe Ichisu-Emitta voltage
  • k T Is thermal energy.
  • Low concentration p is the potential of the substrate accumulation hole density is Emitta buried oxide film capacitance C B. It is determined by x, and V ds.
  • V BE should be large enough for the diffusion potential difference between n + s -p + c when n + s ⁇ P + c can be represented by a diode, that is, when a normal pn junction is formed. Can not.
  • n + s ⁇ c When n + s ⁇ c is short-circuited, the collector is at ground potential and V BE can take a sufficiently large value, and holes flow out to the source electrode.
  • the short circuit between n + s and pc can be realized by the formation of crystal defects on the pn junction surface by high-concentration As ion implantation or by the direct formation of n-type doped polycrystalline Si on the p-type high concentration layer.
  • the p-type high-concentration layer in the source is a low-concentration n-type diffusion layer, which covers the side and bottom surfaces facing the drain, and the surface is covered with the high-concentration n-type diffusion layer.
  • the number of gummels on the side surface is set small, and the number of gummels on the front surface is increased. This has the effect of suppressing electron emission from the source to the substrate due to the rise in the substrate potential.
  • the width of the low-concentration n-type diffusion layer on the side of the p-type high-concentration layer in the source be narrow for the same reason.
  • an n-type diffusion layer is also formed at the bottom of the p-type diffusion layer to isolate the p-type diffusion layer from the substrate, so that the presence of the P-type diffusion layer is not affected by the drain-substrate capacitance. That is, the effect of reducing the parasitic capacitance by the thick buried oxide film, which is the largest feature of the conventional SOI * MOS, is maintained.
  • the substrate floating effect can be similarly eliminated by replacing the impurity conductivity type described above. That is, the present invention is effective in eliminating the substrate floating effect of SOI ⁇ CMOS.
  • FIG. 5A is an enlarged cross-sectional view of the vicinity of the source diffusion layer in another embodiment of the present semiconductor device
  • FIG. 5B is an equivalent circuit diagram of the present semiconductor device
  • FIG. 6B is a diagram showing the energy bands of the high-concentration P region and the high-concentration n region in the source region in an overlapping manner. It is assumed that the bottom of the source region is separated from the outside by a buried oxide film.
  • the second parasitic pnp bipolar formed in the source region is based on the emitter p- in the p-type substrate region, the base is based on the n-type low-concentration source diffusion layer, and the collector p + is in the p-type high-concentration region in the source. Act as The base is connected to the high-concentration source region at the ground potential through a resistance component of the low-concentration source diffusion layer. In the second parasitic bipolar of the present semiconductor device, the base potential is fixed.
  • the hole injection efficiency can be improved by reducing the diffusion potential difference between holes by bringing the emitter and collector closer together under the condition of sufficiently low impurity base concentration.
  • a mechanism is needed to quickly eliminate holes injected into the collector.
  • the present semiconductor device utilizes a recombination center based on a crystal defect or the like. It is well known that the hole annihilation mechanism due to the recombination center also depends on the impurity concentration, and it is desirable that the P-type impurity concentration be as high as possible.
  • the holes generated by the strong electric field at the drain and accumulated in the P-type substrate region are drawn out to the source region by the bipolar formed in the source region, and are converted into the source current. Is eliminated.
  • the above source current density J is expressed by the following equation.
  • the method of forming the present semiconductor device is to use a gate electrode as a mask and implant a relatively low-concentration first n-type impurity layer to reach a thick silicon oxide film immediately below the SOI layer by ion implantation of phosphorus (P).
  • a low-concentration n-type diffusion layer is first formed by a subsequent heat treatment. From this state, a gate sidewall insulating film is formed, and high-concentration boron (B) ions are implanted using the gate electrode and the gate sidewall insulating film as a mask to make the bottom portion of the SOI layer amorphous.
  • the bottom of the amorphous layer is an oxide film even in a short-time high-temperature heat treatment, single-crystallization by recrystallization heat treatment is not performed except for the side surface of the single-crystal SOI layer immediately below the gate. Only crystallization proceeds.
  • the above polycrystalline or amorphous properties can be controlled by heat treatment conditions, and control the recombination center characteristics.
  • the width of the source low-concentration n-type diffusion layer left on the side surface and serving as a base region is controlled by the thickness of the gate sidewall insulating film.
  • the n-type high-concentration region formed on the surface of the SOI layer is formed by ion implantation or by selectively removing a certain thickness of the surface of the p-type high-concentration region, and then forming the semiconductor film by deposition to leave. May be. In the latter case, a steeper high impurity distribution can be realized, and an impurity distribution having more excellent recombination characteristics and thus more effective in eliminating the substrate floating effect can be realized. Since the method of the present invention is performed using the gate electrode and the gate sidewall insulating film as a mask, a similar structure is formed in the drain region.
  • the drain voltage is applied to the n-type high-concentration region, but since the relationship between the n-type high-concentration region and the bottom P-type high-concentration region in the drain has a reverse characteristic with respect to hole injection, the junction leakage The increase in the blocking current is negligible and does not hinder the operation as a NOS transistor.
  • FIGS. 5A and 5B ie, a p-type low-concentration SOI substrate emitter, an n-type low-concentration diffusion layer as a base, a p-type high-concentration region as a collector, and an n-type high-concentration
  • the n-type high-concentration region was set to the ground potential, and the hole current flowing through the emitter when a positive voltage was applied to the p-type low-concentration SOI substrate emitter was determined by numerical analysis using the base width parameter.
  • Fig. 7 shows the results.
  • the p-type S 0 I layer having a uniform concentration distribution of 50 mn and 4 ⁇ 10 17 / cm 3 was used as the emitter, and the thickness was 10 nm, which was configured to be in contact with the buried insulating film at the bottom of the SO I layer.
  • the high-concentration region, n-type base has a Gaussian distribution with a maximum concentration of 5 XI 0 'Vcm 3 , and is configured so as to separate the collector and the n-type high-concentration region from the emitter.
  • the recombination time 1/10 '° sec collector region, in other regions assumes 1Z10 4 seconds.
  • Recombination time 1 1 0 1 The value of 1 second is a value normally observed in a high impurity concentration polycrystalline Si film.
  • the electron current and the hole current having no p-type collector region and the normal source structure are also shown by thin lines.
  • the electron current flowing into the emitter that of the present semiconductor device also matches that of the conventional structure, there is no difference, and it shows an increasing trend in proportion to the applied voltage with the exponential function.
  • the hole current the emitter current flows out from the emitter up to the threshold voltage (negative hole current). From the threshold voltage onwards, the hole current becomes a positive hole current, which increases in proportion to the applied voltage in an exponential function. Even in the normal structure, the hole current shows a value about two orders of magnitude larger than the electron current.
  • the base width is 4
  • the hole current near the threshold voltage is about three orders of magnitude higher than that of the conventional structure, and the threshold voltage is also 0.
  • a 2 V drop is seen.
  • the above-mentioned meaning indicates that the source diffusion potential with respect to the hole current is reduced by 0.2 eV in the present semiconductor device structure as compared with the conventional structure.
  • the above value is twice the reduced value of the source diffusion potential of 0.1 eV due to the known SiGe mixed crystal formation in the source, indicating that the elimination of the substrate floating effect is further improved.
  • the decrease in the threshold voltage tends to be eliminated with an increase in the base width, a decrease of 0.04 V is observed even with a base width of 0.1 ⁇ m as compared with the conventional structure. That is, in the present semiconductor device structure, the base width is desirably 0.1 m or less.
  • the semiconductor device has a symmetric structure with respect to the source and the drain, and is also effective for a so-called transfer MOS or the like in which the drain and the source are switched according to the circuit operating conditions to operate in both directions. Furthermore, an n-type diffusion layer is also formed at the bottom of the p-type high-concentration region in the source and drain to isolate the p-type diffusion layer from the substrate, or a configuration that limits the P-type high-concentration region to only the desired locations. By doing so, the presence of a p-type high concentration region in the drain-substrate capacitance can be reduced to a negligible level.
  • n MOS holes generated near the drain and accumulated in the substrate are quickly injected into the source diffusion layer and annihilated.
  • a region having a small diffusion potential difference formed between the P-type substrate region immediately below the channel and the source diffusion region, that is, a sufficiently low concentration n-type diffusion layer region is provided adjacent to the source high concentration diffusion layer.
  • a region acting as a recombination center for holes is provided in the n-type low-concentration diffusion layer region to eliminate holes injected into the n-type low-concentration diffusion layer region.
  • the electrons required for hole annihilation are supplied from the n-type high concentration diffusion layer region on the source surface.
  • the recombination based on crystal defects and the like is used as a hole annihilation mechanism by the recombination center. Take advantage of the center.
  • FIG. 8 is an enlarged cross-sectional view near the source diffusion layer in the present semiconductor device
  • FIG. 9 is an energy band diagram near the source when the drain voltage is the ground voltage. It is assumed that the bottom of the source region is separated from the outside by a buried oxide film.
  • the energy band in the case of the conventional source structure using the high-concentration source diffusion layer is also shown by broken lines, but in the structure of the present invention, the decrease in the diffusion potential difference with respect to holes is apparent.
  • the impurity concentration of the low concentration diffusion layer is preferably as low as possible without changing the conductivity type, and is preferably 10 15 / cm 3 or more and 10 ′ 8 Zcm 3 or less.
  • the formation of crystal defects acting as recombination centers is performed by ion implantation with an element that does not increase the diffusion potential difference with respect to holes in the n-type low-concentration diffusion layer, thereby making the bottom surface of the SOI layer amorphous.
  • single-crystallization by recrystallization heat treatment is not performed except for the side surface of the single-crystal SOI layer immediately below the gate because the bottom is an oxide film. Only progresses.
  • the above polycrystalline or amorphous properties can be controlled by heat treatment conditions, and the recombination center characteristics can be controlled.
  • CMOS semiconductor devices which are the mainstream of MOS type semiconductor devices
  • individually applying nMOS and pMOS will increase the number of manufacturing steps and decrease the yield of non-defective products. This leads to higher costs. Therefore, as the ion implantation source that forms the recombination center, an element that does not increase the diffusion potential difference with respect to a small number of carriers in the n-type and p-type low-concentration diffusion layers is used in the same process for each of the pMOS and nMOS source low-concentration diffusion regions. It is desirable to perform ion implantation to form recombination.
  • an element other than an element that easily activates and forms n or p conductivity type such as P, B, As, Sb, and Ga, may be used as an ion implantation source.
  • the element be an element that makes the semiconductor substrate amorphous by ion implantation, and an element having an atomic mass of 10 or less is not preferable.
  • Alkali metals such as Na and K and alkaline earth metals including Mg, which have an unusually large diffusion coefficient in Si semiconductors and impair reliability, are also not preferred.
  • a group 14 element such as Si, Ge and C, a halogen element such as F and C1, and a rare gas element such as Ne and Ar which constitute the semiconductor are preferable.
  • elements such as Si, C, Ne, Ar, and C1, which are inexpensive, stable in supply, easy to ionize, and stable, are most preferable.
  • a low-concentration and high-concentration source / drain diffusion layer is formed using a gate electrode as a mask.
  • the low-concentration diffusion layer is formed by ion implantation and heat treatment after reaching the silicon oxide film having a thickness L just below the SOI layer.
  • a gate sidewall insulating film is formed, and ion implantation of, for example, Si using the gate electrode and the gate sidewall insulating film as a mask is performed so as to reach a thick silicon oxide film immediately below the SOI layer, thereby forming the SOI layer in the oxide film interface region.
  • the interface of the amorphous region is not single-crystallized by the subsequent heat treatment, but is polycrystallized by fine grain boundaries, and functions as a recombination center.
  • the center between the recombination center region and the channel region The distance between the SOI substrates, that is, the width of the source low concentration n-type diffusion layer is controlled by the thickness of the gate sidewall insulating film.
  • the source low-concentration n-type diffusion layer width is preferably lower than 100 ⁇ 0 ° so that minority carriers can easily reach the recombination center region and disappear.
  • the n-type high-concentration source region formed on the surface of the SOI layer may be formed by forming the above-described recombination center region, selectively removing a certain thickness of the surface portion, and leaving the semiconductor film by the deposition method. ,.
  • Another method of forming the semiconductor device is to form a source / drain region having a desired diffusion layer structure based on a conventional manufacturing method, and then form a contact hole for connection with a source electrode. Selectively perform ion implantation to form a low concentration diffusion layer that reaches the thick silicon oxide film just below the SOI layer.
  • a side wall film is provided so as to reduce the contact hole dimension by a certain width, and ion implantation for forming a recombination center region using the side wall film as an implantation mask is performed so as to reach a thick silicon oxide film immediately below the SOI layer. May be.
  • the method of the present invention is performed using the gate electrode and the gate side wall insulating film or the contact hole as an ion implantation mask, a similar structure is formed in the drain region.
  • the drain voltage is applied to the n-type high-concentration region.However, the relationship between the n-type high-concentration region and the bottom recombination center region in the drain has a reverse characteristic with respect to hole injection. The increase in junction leakage current is negligible and does not hinder the operation as a MOS transistor.
  • the n-type high-concentration region is set to the ground potential, and the hole current flowing when a positive voltage is applied to the p-type low-concentration SOI substrate is reduced by the distance between the recombination center region and the channel region S 0 I substrate.
  • Figure 6 shows the results obtained by numerical analysis as parameters.
  • the diffusion layer width was used as a parameter.
  • the source low-concentration n-type diffusion layer has a Gaussian distribution with a maximum concentration of 1 ⁇ 10 16 / cm 3 and is configured to be in contact with the buried insulating film at the bottom of the SOI layer.
  • S assumes a 1 Z 1 0 4 seconds in other areas.
  • the recombination time of 1Z10 '° sec is the value normally observed for polycrystalline Si films.
  • the electron current and the hole current of the normal source structure having no recombination center region are also shown by thin lines for reference.
  • That of the semiconductor device of the present invention also matches that of the conventional structure, and no difference is observed.
  • the increase in the applied current is proportional to the exponential function.
  • For the hole current there is a threshold voltage at which a current proportional to the applied voltage starts to flow exponentially. Below the threshold voltage, the behavior is as if the current becomes zero at zero applied voltage. Even in the normal structure, the hole current shows a value about two orders of magnitude larger than the electron current.
  • the hole current near the threshold voltage value is about three orders of magnitude higher than that of the conventional structure and the threshold voltage is 0.2 V when the source low-concentration n-type diffusion layer width is 4 Onm ⁇ or less. Is seen to decrease.
  • the above means that the source diffusion potential with respect to the hole current is reduced by 0.2 eV in the present semiconductor device structure as compared with the conventional structure.
  • the above value is twice the reduction value of the source diffusion potential of 0.1 eV due to the formation of the SiGe mixed crystal in the known source, indicating that the elimination of the substrate floating effect is further improved compared to the known method. I have.
  • the width of the source low-concentration n-type diffusion layer is desirably 0.1 ⁇ m or less.
  • the results in FIG. 10 relate to the forward characteristics when a positive voltage is applied to the channel region S 0 I substrate.
  • Numerical analysis was also performed on the reverse characteristics in which a positive voltage was applied to the n-type high concentration region.However, in the analysis results up to 3 V, the current was a value between 1/10 13 and 1Z10 15 A within the calculation error range. However, there was no difference from the normal structure. This result indicates that even if the same structure as in the source is formed in the drain, no problem such as an increase in leakage current occurs.
  • the semiconductor device according to the present invention has a symmetric structure with respect to the source and the drain, and is also effective for a so-called transfer MOS or the like in which the drain and the source are switched according to the circuit operating conditions to operate in both directions.
  • the presence of the recombination center region in the source and drain does not affect the drain-substrate capacitance at all, and the parasitic capacitance reduction effect of the thick buried oxide film, which is the largest feature of conventional SOI and MOS, is maintained. Is done.
  • the present invention is effective irrespective of the conductivity type of the semiconductor device, and is therefore effective for eliminating the substrate floating effect of SOI ⁇ CMOS.
  • FIG. 1 is a cross-sectional view of a conventional semiconductor device.
  • FIG. 2 is an explanatory view of an energy band of a substrate floating effect eliminating mechanism in a conventional semiconductor device.
  • FIG. 3 is an impurity distribution diagram in the depth direction of the source diffusion layer in the semiconductor device of the present invention.
  • 4A and 4B are an energy node diagram and a source equivalent circuit diagram illustrating a mechanism for eliminating a substrate floating effect in a semiconductor device of the present invention.
  • 5A and 5B are a cross-sectional view near a source diffusion layer and an equivalent circuit diagram in the semiconductor device of the present invention.
  • 6A and 6B are energy band diagrams illustrating a mechanism for eliminating a substrate floating effect by the semiconductor device of the present invention.
  • FIG. 7 is an analysis result regarding a substrate floating effect eliminating mechanism by the semiconductor device of the present invention.
  • FIG. 8 is a cross-sectional view of a source diffusion layer illustrating a mechanism for eliminating a substrate floating effect in a semiconductor device of the present invention.
  • FIG. 9 is an energy band diagram for explaining a mechanism for eliminating a substrate floating effect by the semiconductor device of the present invention.
  • FIG. 10 is an analysis result on a mechanism for eliminating a substrate floating effect by the semiconductor device of the present invention.
  • FIG. 11 is a sectional view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 12 is a sectional view of a first step in manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 13 is a sectional view of a second step in manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 14 is a sectional view of a third step of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 15 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 16 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 17 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 18 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 19 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 20 is a cross-sectional view of a first step in manufacturing a semiconductor device according to the seventh embodiment of the present invention.
  • FIG. 21 is a sectional view of a second step of the semiconductor device according to the seventh embodiment of the present invention.
  • FIG. 22 is a completed sectional view of a semiconductor device according to an eighth embodiment of the present invention.
  • FIG. 23 is a cross-sectional view showing the order of the manufacturing steps of the semiconductor device according to the eighth embodiment of the present invention c.
  • FIG. 24 is a cross-sectional view showing the order of the manufacturing steps of the semiconductor device according to the eighth embodiment of the present invention c 2 5 is a cross-sectional view c Figure 2 6 showing the manufacturing process sequence of the semiconductor device according to the eighth embodiment of the present invention, a ninth sectional view c showing the manufacturing process sequence of the semiconductor device according to an embodiment of the present invention 2 7 is a cross-sectional view c Figure 2 8 showing the manufacturing process sequence of the semiconductor device according to a ninth embodiment of the present invention, the finished cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention.
  • FIG. 29 is a completed sectional view of a semiconductor device according to a tenth embodiment of the present invention.
  • FIG. 30 is a completed sectional view of the semiconductor device according to the eleventh embodiment of the present invention.
  • FIG. 31 is a cross-sectional view of a completed semiconductor device according to the 12th embodiment of the present invention.
  • FIG. 32 is a sectional view showing the order of manufacturing steps of the semiconductor device according to the thirteenth embodiment of the present invention.
  • FIG. 33 is a completed sectional view of a semiconductor device according to a thirteenth embodiment of the present invention.
  • FIG. 34 is a completed sectional view of the semiconductor device according to the fourteenth embodiment of the present invention.
  • FIG. 35 is a sectional view showing the order of manufacturing steps of the semiconductor device according to the fourteenth embodiment of the present invention.
  • FIG. 36 is a sectional view showing the order of manufacturing the semiconductor device according to the fourteenth embodiment of the present invention.
  • FIG. 37 is a cross-sectional view showing the order of manufacturing steps of the semiconductor device according to the fourteenth embodiment of the present invention.
  • FIG. 38 is a cross-sectional view showing the order of manufacturing steps of the semiconductor device according to the fifteenth embodiment of the present invention.
  • FIG. 39 is a cross-sectional view showing a semiconductor device manufacturing process according to the fifteenth embodiment of the present invention.
  • FIG. 40 is a completed sectional view of a semiconductor device according to a fifteenth embodiment of the present invention.
  • FIG. 41 is a cross-sectional view showing the order of manufacturing the semiconductor device according to the sixteenth embodiment of the present invention.
  • FIG. 42 is a completed sectional view of a semiconductor device according to a sixteenth embodiment of the present invention.
  • FIG. 43 is a cross-sectional view showing the order of the manufacturing process of the semiconductor device according to the seventeenth embodiment of the present invention.
  • FIG. 44 is a completed sectional view of a semiconductor device according to a seventeenth embodiment of the present invention.
  • FIGS. 45A and 45B are explanatory diagrams of an as-necessary write / read storage device for explaining an application example of the embodiment of the present invention.
  • FIGS. 46A and 46B are explanatory diagrams of a constant write / read storage device for explaining another application example of the embodiment of the present invention.
  • FIG. 47 is a logic circuit diagram for explaining another application example of the embodiment of the present invention.
  • FIG. 48 is an explanatory diagram of a computer configuration for explaining still another application example of the embodiment of the present invention.
  • FIG. 49 is an explanatory diagram of an asynchronous transmission mode system for explaining another application example of the embodiment of the present invention.
  • FIG. 50 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention.
  • FIG. 51 is a sectional view of a semiconductor device according to a ninth embodiment of the present invention.
  • FIGS. 11 to 14 are cross-sectional views showing the steps of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 11 is a completed cross-sectional view thereof.
  • ion implantation of p and subsequent heat treatment are performed using the gate protective insulating film 7 and the gate side wall insulating film 8 as an implantation preventing mask, the junction ends reach the oxide film 2, and the effective gate length is 15 O nm, and the maximum impurity concentration in the surface forming the source 9 and drain 1 0 by the low-concentration n-type diffusion layer so that Do a 1 x 1 0 1 Vcm 3.
  • a high concentration p-type diffusion layer 11 having a maximum impurity concentration of 2 ⁇ 10 19 / cm 3 was formed inside the low concentration n-type source 9 and the drain 10 by ion implantation of BF 2 .
  • High-concentration p-type diffusion layer 1 1 Minimum width between side junction and low-concentration source 9 or low-concentration drain junction is 50 nm, high-concentration P-type diffusion layer 11 It was about 3 O nm (FIG. 12).
  • a W film 12 having a thickness of 15 O nm was deposited on the entire surface by sputtering, and was patterned so as to cover at least the surfaces of the high-concentration n-type diffusion layers 91 and 101.
  • the W film 12 may be based on the selective chemical vapor deposition method on the Si surface (FIG. 14).
  • a wiring protection insulating film 13 is deposited and an opening is formed at a desired position based on a known method of manufacturing a semiconductor device. Further, a source electrode 14 and a drain electrode 1 are formed by vapor deposition of wiring metal and patterning thereof. Wiring including 5 etc. was formed (Fig. 11).
  • the withstand voltage between the source and the drain of the semiconductor device manufactured through this manufacturing process is 4.7 V, which is about 1 compared with the conventional structure SOI ⁇ MOS of the same size without the p-type diffusion layer 11 in the source. .5 V, and a breakdown voltage equivalent to that of MOS with the same dimensions normally manufactured on a semiconductor substrate could be secured.
  • the current-voltage characteristics no abnormal bump-like characteristics called kink characteristics were observed, and the characteristics were normal.
  • the existence of a leak current at a low gate voltage conventionally observed in SOI / MOS was not observed. No change was found in the leakage current and the threshold voltage even when the drain voltage was changed.
  • the semiconductor device according to the present embodiment has been completely eliminated from the characteristics associated with the substrate floating effect. Since the current-voltage characteristics of the semiconductor device according to the present embodiment show normal characteristics, the semiconductor device shows high resistance homogeneity with the n-type high concentration diffusion layers 91 and 101 and is formed inside the source and the drain. It was also found that the p-type high-concentration diffused layer 11 had no adverse effect. This is because the region on the side of the p-type high-concentration diffusion layer 11 is composed of n-type low-concentration diffusion layers 9 and 10, and the surface channel region, which is the current path, is the n-type low-concentration diffusion layer 91 and 101.
  • the holes that are minority carriers generated in the lower substrate of the channel are not in the n-type high-concentration diffusion layer 91 but in the p-type high-concentration diffusion layer 11 through the n-type low-concentration diffusion layer 9. It is thought to be injected. That is, it is considered that the presence of the n-type high-concentration diffusion layer 91 has no effect on the current transfer in the channel.
  • the drain-to-substrate capacitance of the semiconductor device according to this example was also measured, but the capacitance value was equivalent to that of the conventional SOI'MOS, despite the presence of the p-type high-concentration diffusion layer 11. It was as small as about 1/10 of the value for the same size of MOS.
  • the p-type high concentration diffusion layer 11 in the drain is surrounded by the n-type low concentration diffusion layer 10, and a depletion layer is formed in the p-type high concentration diffusion layer 11 by the drain electric field. It is considered that the capacitance is determined by the thick insulating film 2.
  • the single-crystal Si layer 3 is extremely thin at 100 nm, and the substrate impurity concentration in the channel region is set as low as 1 ⁇ 10 17 / cm 3 . Therefore, the neutral region does not exist in the single crystal Si layer 3 in the channel region under the gate voltage condition higher than the threshold voltage due to the limitation of the charge amount in the single crystal Si layer 3, and the single crystal Si layer 3 is in a completely depleted state. This can effectively induce mobile charges in the channel, which is the current drive source, and is suitable for increasing the current. That is, it is known that it is suitable for low voltage and high speed operation.
  • a fully depleted MOS without a substrate floating phenomenon Indicate that it can be provided at a low price only by a conventional method of manufacturing a semiconductor device.
  • FIG. 15 is a view showing a completed cross section of the semiconductor device according to the second embodiment of the present invention.
  • the wiring protective film 13 is formed so that the high-concentration n-type diffusion layers 91 and 101 are not formed, and the source / drain electrodes 14 and 15 reach the high-concentration p-type diffusion layer 11.
  • the single crystal Si film was slightly etched in the step of forming an opening in the substrate.
  • the semiconductor device according to the present embodiment does not show a decrease in the breakdown voltage between the source and the drain, a bump-like characteristic in the current-voltage characteristic, a negative-direction fluctuation in the threshold voltage, and the like.
  • FIG. 16 is a view showing a completed cross section of the semiconductor device according to the third embodiment of the present invention.
  • the element isolation insulating film 4 was formed, and the active regions of the single-crystal Si film 3 were separated from each other. Region 31 was set.
  • a gate oxide film 5, a gate electrode 61, a gate protection insulating film 7, and a gate sidewall insulating film 8 were formed on the low-concentration n-type region 31 and the low-concentration p-type region 3.
  • a low-resistance polycrystalline Si film was used as the gate electrode 61.
  • B ions are selectively implanted only into the low-concentration n-type region 31 and the heat treatment thereafter reaches the oxide film 2 and the surface impurity concentration is 5 XI 0
  • Low-concentration p-type diffusion layers 90 and 100 of 1 cm 3 were formed.
  • As ion implantation is performed so that the maximum impurity concentration is 1 ⁇ 10 ′ Vcm 3 inside the active region and the low impurity concentration p-type diffusion layers 90 and 100 are located inside the n-type diffusion layer 1. 10 were formed.
  • P ions are selectively implanted into the low-concentration P-type region 3 using the gate electrode 61 and the gate side wall insulating film 8 as a mask, and the surface has a maximum concentration of 3 ⁇ 10 18 / cm 3 and an acid.
  • a low-concentration n-type diffusion layer reaching the oxide film 2 was formed, and a source 9 and a drain 10 were formed.
  • an ion implantation of Ge having a surface concentration of 1 ⁇ 10 2 Vcm 3 was performed in the source 9 and the drain 10 to form a Si ⁇ Ge eutectic layer 16 in the source 9 and the drain. .
  • the wiring protection insulating film 13 is deposited, an opening is formed at a desired position, and the wiring is formed.
  • a wiring including a ground potential line 17, an output terminal 18 and a power supply voltage line 19 was formed by vapor deposition and patterning of a metal film for use.
  • CMOS of this example various symptoms caused by the substrate floating effect could not be observed for any of the pMOS and the nMOS. Furthermore, the through current due to the substrate floating effect unique to SOICMOS generated between the ground potential line 17 and the power supply line 19 due to the negative fluctuation of the nM0S threshold voltage and the positive fluctuation of the pMOS threshold voltage It was not observed.
  • the absence of the substrate floating effect in the pMOS means that electrons, which are minority carriers generated in the single-crystal Si film 31 below the channel, are injected toward the n-type diffusion layer 110, and the source has a low concentration p. It is considered that the electrons reaching the diffusion layer 100 disappear by recombination in the depletion layer at the junction between the n-type diffusion layer 110 and the p-type diffusion layer 100.
  • FIG. 17 is a view showing a completed cross section of a semiconductor device according to a fourth embodiment of the present invention.
  • ion implantation of B was performed instead of ion implantation of Ge to form a high-concentration p-type diffusion layer 11 inside the low-concentration n-type diffusion layers 9 and 10.
  • the high-concentration p-type diffusion layer 11 reached the oxide film 2, and the maximum impurity concentration of 2 ⁇ 10 ig / cm 3 was set so as to be located within 80 nm from the surface of the source 9.
  • the pMOS is based on the same reason as in the third embodiment, and even in the nMOS, holes, which are a small number of carriers generated in the channel lower single-crystal Si film 3, are p-type diffusion layers 11 1 It is thought that the holes injected toward the source and reached the source low-concentration n-type diffusion layer 10 disappear by recombination at the depletion layer at the junction between the p-type diffusion layer 11 and the n-type diffusion layer 10 .
  • the ion source is unstable, and it is not necessary to perform the ion implantation of Ge which requires a large ion current reaching a composition ratio of about 10%. Measures against the substrate floating effect were taken.
  • FIG. 18 is a view showing a completed cross section of a semiconductor device according to a fifth embodiment of the present invention.
  • an S0I substrate having a thickness of 300 nm of the single-crystal Si film 3 on the oxide film 2 was used, and the n-type diffusion layers 9 and 10 and the p-type diffusion layers 90 and 100 were formed. 150 nm junction depth Set to.
  • the p-type diffusion layer 9 0 and 1 0 0 as interior positioned above the selectively formed n-type diffusion layer 1 1 0 high concentration p-type diffusion layer 9 2 and 1 0 2 BF 2
  • the n-type diffusion layer 110 is formed!
  • -Type diffusion layers 92 and 102 were electrically short-circuited at high piles.
  • the maximum impurity concentration of the high-concentration p-type diffusion layers 92 and 102 was on the surface, and was set to 1 ⁇ 10 20 / cm 3 .
  • the drain-to-substrate capacitance in the pMOS shows a capacitance value equivalent to that of the conventional SOI.MOS, which is about 1/10 of the value of the MOS of the same dimensions usually manufactured on the semiconductor substrate. It was small.
  • the result is that the n-type high-concentration diffusion layer 110 in the drain is surrounded by the p-type low-concentration diffusion layer 100, and the n-type high-concentration diffusion layer 110 is depleted by the drain electric field. It is considered that the layer is not formed and the capacitance is determined by the thick insulating film 2.
  • the single-crystal Si layers 3 and 31 are relatively thick at 300, In the substrate region, a depletion layer and a neutral region force ⁇ exist, that is, a so-called partially depleted structure is obtained even when a gate voltage higher than the threshold voltage is applied.
  • the partially depleted structure is slightly lower than the fully depleted structure at low voltage and high speed operation, but can be easily manufactured under conventional manufacturing conditions using a conventional semiconductor substrate. It is shown that the semiconductor device according to the present embodiment can provide a countermeasure against the substrate floating of the partially depleted structure MOS at low cost.
  • FIG. 19 is a view showing a completed cross section of the semiconductor device according to the sixth embodiment of the present invention.
  • ion implantation of B was performed instead of ion implantation of Ge, and a high-concentration p-type diffusion layer 11 was formed inside the low-concentration n-type diffusion layers 9 and 10, and subsequently a high-concentration p-type diffusion layer 11 was formed.
  • As ion implantation for forming n-type diffusion layers 91 and 101 was performed.
  • the maximum impurity concentration was set to 5 ⁇ 10 20 / cm 3 at the surface part by As ion implantation, but this resulted in the generation of crystal defects at the upper junction of the p-type diffusion layer 11 and the P-type diffusion layer. 11 and the high concentration n-type diffusion layers 91 and 101 were electrically short-circuited with high resistance.
  • the drain-to-substrate capacitance of both pM0S and nMOS shows the same capacitance value as that of the conventional S0IMOS, which is about the same as the value of the MOS of the same size usually manufactured on the semiconductor substrate. It was as small as 1 Z 10.
  • the n-type high-concentration diffusion layer 110 in the drain is surrounded by the p-type low-concentration diffusion layer 100, and the p-type high-concentration diffusion layer 11 is surrounded by the low-concentration diffusion layer 10 It is considered that no depletion layer is formed in the n-type high-concentration diffusion layer 110 and the p-type high-concentration diffusion layer 11 due to the drain electric field, and the capacitance is determined by the thick insulating film 2.
  • FIG. 20 is a sectional view showing a manufacturing process of the semiconductor device according to the seventh embodiment of the present invention
  • FIG. 21 is a view showing a completed section thereof.
  • a high-resistance polycrystalline Si film 20 having a thickness of 100 nm and a silicon oxide film 21 having a thickness of 10 were formed between the oxide film 2 and the single-crystal Si film 3.
  • a multi-layer SOI substrate was used.
  • the thickness of the single-crystal Si film 3 is 100 nm
  • the impurity concentration of the p-type low concentration active region 3 and the n-type low concentration active region 31 is 1 ⁇ 10 16 / cm 3 , respectively.
  • Set low that is, in this example, a fully depleted complementary MOS field effect transistor was manufactured.
  • the high-resistance polycrystalline Si film immediately below the region where the nMOS gate electrode 7 is to be formed is formed.
  • a high-concentration p-type impurity region 22 having an impurity concentration of 2 ⁇ 10 1 cm 3 is added to a high-resistance polycrystalline Si film 20 immediately below a region where a pMOS gate electrode 7 is to be formed.
  • 1 0 l 8 / cm 3 comprising a high concentration of preformed ⁇ -type impurity region 2 3 (FIG. 2
  • the semiconductor device was manufactured in the sixth embodiment from the state of FIG. 20, the high-concentration p-type diffusion layer 11 formed in the source of the nMOS, the high-concentration n-type diffusion layer 91 on the top, and the pMOS
  • the conditions relating to the junction depth of the high-concentration n-type diffusion layer 110 in the source and the high-concentration p-type diffusion layer 92 in the upper part were as in Example 1.
  • a W film 12 was selectively deposited on the entire surface of the source and drain except for the gate and the gate side wall insulating film portion according to Example 1.
  • the source-drain current at a gate and drain voltage of 2 V of the semiconductor device according to the present embodiment was at least 1.4 times larger than that of pMOS and nMOS.
  • an extremely steep drain conductance characteristic was obtained as compared with the semiconductor device of Example 6.
  • the delay time per stage was 12 ps, which was 6 ps faster than the ring oscillator according to the sixth embodiment.
  • Such ultra-high-speed, high-current characteristics are such that the high-concentration p-type impurity region 22 and the high-concentration n-type impurity region 23 act as a punch-through prevention mechanism, and the thin silicon oxide film 21 is formed at a high temperature during the manufacturing process. Since it acts as an impurity diffusion mask for heat treatment, the impurity concentration of the P-type low-concentration active region 3 and the n-type low-concentration active region 31 forming the channel can be set to an extremely low concentration, and the mobility due to impurity scattering can be reduced. It is considered that the deterioration was prevented.
  • FIGS. 23 to 25 are sectional views showing the order of manufacturing steps of the semiconductor device according to the eighth embodiment of the present invention, and FIG. 22 is a completed sectional view.
  • a silicon oxide film (hereinafter simply referred to as an oxide film) 2 having a thickness of 500 nm and a silicon oxide film having a thickness of 10 O nm are formed on a support substrate 1 made of a single crystal Si having a diameter of 12.5 cm.
  • a S 0 I substrate consisting of a single crystal Si layer 3 with p conductivity type, resistivity of 10 ⁇ , and plane orientation of (100) by well-known M 0 S field effect transistor Film 4, a gate oxide film 5 having a thickness of 5 cm, a gate electrode 6 made of an n-type low-resistance polycrystalline Si film, and a gate protection insulating film 7 were formed.
  • B ions Prior to the formation of the gate oxide film 5, B ions were implanted into the single-crystal Si layer 3 so that the threshold voltage became 0.1 V.
  • the gate length is 20 O nm.
  • the junction end reaches the oxide film 2
  • the effective gate length is 15 O nm.
  • the single-crystal Si layer 3 maintained the single-crystal property.
  • a deposited insulating film having a thickness of 5 O nm is formed on the entire surface, and the insulating film is selectively left only on the side walls of the gate by anisotropic dry etching.
  • a first sidewall insulating film 8 was formed.
  • a semiconductor device based on the present example in which the thickness condition of the gate sidewall insulating film 8 was changed from 10 to 20 nm at an interval was also manufactured separately.
  • a high-concentration p-type region 11 having a maximum impurity concentration of 2 ⁇ 10 19 / cm 3 was formed at the interface with the oxide film 2 inside the low-concentration n-type source 9 and the drain 10 by ion implantation of BF 2 .
  • the width of the low-concentration n-type diffusion layer 9 remaining on the side surface of the high-concentration p-type region 11 was finally 4 O nm.
  • the acceleration energy may be set so that the maximum impurity concentration is in oxide film 2.
  • the high-concentration P-type region 11 was converted to amorphous by the above ion implantation (Fig. 23).
  • the surface concentration 2 X 1 0 2 Vcm 3 becomes high-concentration n-type regions 9 1 and 1 0 1 a high concentration p-type diffusion layer 1 1 on the shape forming did.
  • a short heat treatment at 100 ° C for 10 seconds was performed to activate the implanted ions, but the high-concentration P-type region 11 was fine except for the lateral region immediately below the gate. It was polycrystalline with a particle size of about 1 O nm in thickness.
  • the junction depth of the high-concentration n-type regions 91 and 101 was about 40 nm (FIG. 24).
  • a 15 O nm thick W film 12 was selectively deposited on the exposed Si surface by a chemical vapor reaction.
  • the W film 12 may be formed by sputtering over the entire surface and by patterning so as to cover at least the high-concentration n-type regions 91 and 101 surfaces.
  • a wiring protection insulating film 13 was deposited using a silicon oxide film to which phosphorus was added (FIG. 25).
  • an opening is formed in a desired portion of the wiring protective insulating film 13, and further, a source electrode 14, a drain electrode 15 and the like are formed by vapor deposition of wiring metal and patterning thereof. Wiring was formed.
  • the film thickness of the single crystal Si layer 3 in the final step was reduced to 5 O nm by the cleaning treatment in the manufacturing step (FIG. 22).
  • the withstand voltage between the source and the drain of the semiconductor device according to the present embodiment manufactured through the above-described manufacturing process is 4.7 V, which is smaller than that of the conventional structure SOIMOS having the same dimensions without the p-type diffusion layer 11 in the source.
  • By about 1.5 V it was possible to secure a breakdown voltage equivalent to that of MOS transistors of the same dimensions normally manufactured on semiconductor substrates.
  • no abnormal bump-like characteristics called kink characteristics were observed. showed that.
  • the source-drain current-gate voltage characteristics are possible to secure.
  • the interval from the high-concentration p-type region 1 1 end to the low-concentration n-type diffusion layer junction was observed from 10 ⁇ ⁇ ⁇ from bottom to 20. No observation was made, and it was clear that it was the most favorable. In the structure in which one end of the high-concentration p-type region 11 is beyond the low-concentration n-type diffusion layer junction, the substrate floating effect could not be eliminated.
  • the semiconductor device according to the present embodiment is effective for eliminating the SOIMOS substrate floating effect, and the recrystallization of the polycrystalline injected holes of the high-concentration p-type region 11 formed in contact with the oxide film 2 It was speculated that it would work well as a center.
  • the single-crystal Si layer 3 is as thin as 5 O nm, and the substrate impurity concentration in the channel region is set as low as 1 ⁇ 10 ′ Vcm 3 . Therefore, the neutral region does not exist in the single-crystal Si layer 3 in the channel region under the gate voltage condition higher than the threshold voltage due to the limitation of the charge amount in the single-crystal Si layer 3, and the single-crystal Si layer 3 is in a completely depleted state. This can effectively induce mobile charges in the channel, which is the current drive source, and is suitable for increasing the current. That is, it is suitable for low voltage and high speed operation.
  • FIG. 28 is a completed sectional view thereof.
  • Si films 92 and 102 to which phosphorus was added at a high concentration were selectively formed in the above-mentioned etching region, and a heat treatment at 65 ° C. for 10 minutes was performed to activate the film.
  • the source and drain consisted of a high-concentration n-type region.
  • the formation of the Si films 92 and 102 may be performed under any of the conditions of single crystal epitaxial selective growth and polycrystalline selective growth. Further, the Si film deposited on the entire surface may be formed by patterning.
  • the high-concentration n-type may be based on, for example, ion implantation instead of the simultaneous addition of impurities when forming the Si film.
  • the above-mentioned Si films 92 and 102 are formed from the viewpoint of reducing the source resistance as if the Si films 92 and 102 had a surface formed above the initial surface before etching. The structure is desirable (Fig. 27).
  • the semiconductor device according to the present embodiment manufactured through the above-described manufacturing process, no characteristic associated with the substrate floating effect was observed similarly to the semiconductor device according to the eighth embodiment, and a normal fully depleted SOI MOS characteristic was obtained.
  • the high-concentration p-type region 11 including the interface with the high-concentration n-type regions 9 and 10 can be formed into a steep high-concentration distribution, so that the impurity concentration increases.
  • the recombination time, which is reduced accordingly, can be further reduced, and the injected holes can be more efficiently eliminated as compared with the semiconductor device of the first embodiment. That is, it is more effective in eliminating the substrate floating effect.
  • FIG. 29 is a completed sectional view of a semiconductor device according to another embodiment (No. 10) of the present invention.
  • the high-concentration P-type region 11 is selectively removed except for a part adjacent to the gate sidewall insulating film 8, and then the Si film 92, and The semiconductor device was manufactured by performing the manufacturing steps after the selective formation of silicon and silicon.
  • the selective removal of the high-concentration P-type region 11 was performed using a photomask, but a material different from the gate sidewall insulating film 8 from the state shown in Fig. 26 was used in order to guarantee self-alignment with the gate electrode.
  • the second sidewall insulating film may be selectively formed by (silicon nitride film) and the high-concentration P-type region 11 may be selectively removed using the second sidewall insulating film as a mask. Further selective removal Alternatively, the high-concentration P-type region 11 may be reduced by performing high-concentration n-type ion implantation using the second sidewall insulating film as a mask on the high-concentration p-type region 11 (FIG. 29). ).
  • the drain-substrate capacitance is reduced in proportion to the selective removal area of the high-concentration p-type region 11 with respect to the drain region having the same shape as the source region.
  • the capacitance was reduced to the same level as that of a normal SOI MOS without the high-concentration p-type region 11.
  • the capacitance value of a normal SOI MOS is about 1/10 of the value of a MOS of the same size usually manufactured on a semiconductor substrate.
  • FIG. 30 is a completed sectional view of a semiconductor device according to another embodiment (11) of the present invention.
  • Example 8 an SOI substrate having a thickness of 20 O nm was used as the single-crystal Si layer 3, the formation region of the high-concentration P-type region 11 was separated from the oxide film 2 interface, and the low-concentration n-type diffusion It was configured to be adjacent to the oxide film 2 via the layers 9 and 10. That is, the high-concentration p-type region 11 has a structure completely isolated from the outside by the low-concentration n-type diffusion layers 9 and 10. Other manufacturing steps were in accordance with Example 1 (FIG. 30).
  • the semiconductor device according to the present embodiment manufactured through the above manufacturing process exhibits a low junction capacitance value equivalent to that of the conventional SOI * MOS, despite the presence of the high-concentration P-type region 11 in the drain region.
  • the value was as small as about 1/10 of the value of MOS of the same size usually manufactured on a semiconductor substrate.
  • the above result shows that the high-concentration p-type region 11 in the drain is surrounded by the low-concentration n-type diffusion layer 10, and no depletion layer is formed in the high-concentration p-type region 11 by the drain electric field. It is considered that the capacitance is determined by the thickness and the oxide film 2.
  • FIG. 31 is a completed sectional view of a semiconductor device according to another embodiment (No. 12) of the present invention.
  • Example 8 an S 0 I substrate having a thickness of 500 nm was used as the single crystal Si layer 3, and the active regions of the single crystal Si film 3 were separated from each other by forming an element isolation insulating film 4. After that, ion implantation was performed on a part of the active region according to a desired circuit configuration to obtain a low-concentration n-type region 31.
  • the gate oxide film 5, the gate electrode 61, the gate protection insulating film 7, and the gate sidewalls were formed on the low-concentration n-type region 31 and the low-concentration p-type region 3.
  • An edge film 8 was formed.
  • a W film was used as the gate electrode 61.
  • the gate electrode 61 and the gate side wall insulating film 8 as a mask, only the low-concentration n-type region 31 is selectively ion-implanted with B and then subjected to a heat treatment to have a junction depth of 20 O nm.
  • Low-concentration p-type diffusion layers 90 and 100 having an impurity concentration of 5 ⁇ 10 18 / cm 3 were formed.
  • As is ion-implanted so that the maximum impurity concentration is 5 ⁇ 10 2 cm 3 inside the active region and the low-concentration p-type diffusion layers 90 and 100 are located inside the high-concentration n-type region 1. 10 were formed.
  • the high-concentration n-type region 110 was not single-crystallized even after the activation heat treatment due to the impurity concentration higher than the solid solution limit, and a polycrystalline crystal defect region was retained.
  • P ions are selectively implanted into the low-concentration P-type region 3 using the gate electrode 61 and the gate sidewall insulating film 8 as a mask, and the maximum concentration is 3 ⁇ 10 18 / cm 3 at the surface , and 20
  • a low-concentration n-type diffusion layer having a junction depth of O nm was formed, and was used as a source 9 and a drain 10.
  • the ground potential line 17, the output terminal 18 and the power supply voltage line 19 are formed by depositing the wiring protective insulating film 13 and opening it at a desired location, depositing a wiring metal film and patterning the same. Was formed.
  • the pMOS and the nMOS could not observe any symptoms caused by the substrate floating effect.
  • SOI ⁇ CMOS penetrates due to the substrate floating effect peculiar to SOI and CMOS caused by the negative fluctuation of the nMOS threshold voltage and the positive fluctuation of the pMOS threshold voltage. No current was observed.
  • the absence of the substrate floating effect in p MOS indicates that electrons, which are a small number of carriers generated in the channel single crystal Si film 31, were injected toward the high-concentration n-type region 110, and the crystal defect occurred. It is thought that it disappears due to recombination center based on the pit.
  • the capacitance between the drain substrate in the PMOS shows a capacitance value equivalent to that of the conventional SOI ⁇ MOS, and is approximately 1 Z 1 of the value of the MOS of the same size usually manufactured on the semiconductor substrate. It was a small thing of 0.
  • the above result is The high-concentration n-type region 110 in the rain is surrounded by the p-type low-concentration diffusion layer 100, and no depletion layer is formed in the high-concentration n-type region 110 due to the drain electric field. It is considered that the amount is determined by the thick insulating film 2.
  • the single-crystal Si layers 3 and 31 are relatively thick at 50 O nm, and in the substrate region below the channel region, the depletion layer and the neutral region are applied even when a gate voltage higher than the threshold voltage is applied.
  • a so-called partially depleted structure in which a region exists is obtained.
  • the partially depleted structure is slightly lower than the fully depleted structure at low voltage and high speed operation, it can be easily manufactured under conventional manufacturing conditions using a conventional semiconductor substrate. This shows that the semiconductor device according to the present embodiment can provide a countermeasure against the substrate floating of the partially depleted structure MOS at low cost.
  • FIG. 32 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment (the thirteenth) of the present invention
  • FIG. 33 is a completed sectional view thereof.
  • the thickness of the single-crystal Si film 3 was set to 200, and the high-resistance multilayer having a thickness of 100 nm was formed between the oxide film 2 and the single-crystal Si layer 3 having a thickness of 200 nm.
  • a multi-layer SOI substrate having a crystalline Si film 20 and a 10 nm thick silicon oxide film 21 was used.
  • the thickness of the single-crystal Si film 3 is 10 O nm, and the impurity concentration of the p-type low concentration active region 3 and the n-type low concentration active region 31 is 1 ⁇ 10 16 cm 3 , respectively.
  • Set low That is, in this example, a completely depleted complementary MOS field effect transistor was manufactured.
  • the high-resistance polycrystalline Si directly under the region where the nMOS gate electrode 7 is to be formed is formed prior to the formation of the gate oxide film 5, the gate electrode 6, the gate protection insulating film 7, and the gate sidewall insulating film 8, the high-resistance polycrystalline Si directly under the region where the nMOS gate electrode 7 is to be formed is formed.
  • a high-concentration p-type impurity region 22 having an impurity concentration of 2 ⁇ 10 1 cm 3 is formed in the film 20, and an impurity concentration 2 is formed in the high-resistance polycrystalline Si film 20 immediately below the region where the p-MOS gate electrode 7 is to be formed.
  • the X 1 0 1 8 / cm 3 comprising a high concentration n-type impurity region 2 3 preformed (FIG. 2).
  • a semiconductor device was manufactured according to the embodiment 12 from the state of FIG. 32. However, a high-concentration n-type region 91 and a high-concentration n-type region 91 were formed above the high-concentration p-type region 11 formed in the source of nMOS. The high-concentration p-type regions 92 were respectively formed above the high-concentration n-type regions 110 in the source in FIG. Each of the above junction depths was the same as the condition in Example 11 described above. Further, a W film 12 was selectively deposited on the entire surface of the source and drain except for the gate and gate sidewall insulating films according to Example 4 (FIG. 33).
  • the delay time per stage was 12 ps, which was 6 ps faster than the ring oscillator according to the fifth embodiment.
  • the high-concentration p-type impurity region 22 and the high-concentration n-type impurity region 23 act as a punch-through prevention mechanism, and the thin silicon oxide film 21 acts as an impurity diffusion mask for high-temperature heat treatment during the manufacturing process. Therefore, the ultra-high-speed and large-current characteristics of the semiconductor device according to the present embodiment can be set to extremely low impurity concentrations in the p-type low-concentration active region 3 and the n-type low-concentration active region 31 forming the channel. It is considered that the mobility was prevented from deteriorating due to impurity scattering.
  • FIGS. 34 to 37 are sectional views showing the order of manufacturing steps of the semiconductor device according to the fourteenth embodiment of the present invention, and FIG. 34 is a completed sectional view thereof.
  • An S0I substrate consisting of a single crystal Si layer 3 having a thickness of 100 Qcm and a plane orientation of (100) is formed on a S0I substrate by a known method of manufacturing an M0S field-effect transistor.
  • a gate oxide film 5 a gate electrode 6 made of an n-type low-resistance polycrystalline Si film, and a gate protection insulating film 7 were formed. Prior to the formation of the gate oxide film 5, B ions were implanted into the single-crystal Si layer 3 so that the threshold voltage became 0.1 V.
  • the gate length is 20 O nm.
  • ion implantation of p and subsequent heat treatment are performed using the gate protection insulating film 7 and the gate electrode 6 as an implantation blocking mask, the junction ends reach the oxide film 2, the effective gate length is 15 O nm, and the surface is maximum impurity concentration formed a 2 XI 0, 6 / cm 3 and the source 9 and drain 1 0 by the low-concentration n-type diffusion layer as made in.
  • ion implantation of As and subsequent heat treatment are performed, resulting in high-concentration n-type diffusion. Layers 91 and 101 were formed.
  • the single-crystal Si layer 3 maintained single-crystallinity (FIG. 35).
  • a 50-nm-thick deposited insulating film is formed on the entire surface, and the above-mentioned insulating film is selectively left only on the gate side wall by anisotropic dry etching to form a gate side wall insulating film 8.
  • a semiconductor device based on the present embodiment in which the minimum film thickness is changed to 20 nm and the maximum film thickness is set to 0.5 / im at intervals of 10 to 100 is also used. Manufactured separately.
  • Si ions were implanted under the conditions of a dose of 3 ⁇ 10 1 cm 2 so that the concentration was maximized at the interface between the low concentration n-type source 9 and the oxide film 2 inside the drain 10.
  • a heat treatment was performed at 800 ° C. for 10 minutes.
  • Observation of the cross section of a sample separately manufactured under the same conditions with a transmission electron microscope revealed that twins of fine crystal grains, that is, crystal defect regions 11 were formed near the oxide film 2 interface. became.
  • the acceleration energy may be set so that the maximum concentration is in oxide film 2.
  • ion implantation for forming the crystal defect region 11 does not need to be Si as an ion species, and rare gas elements such as Ne and Ar, halogen elements such as F and C1, It has been found that the same effect can be obtained even with a group 14 element such as C and Ge. However, it has been found that the ion implantation of the n-conductivity-type element in the Si single crystal like P has no effect as described later. ( Figure 36).
  • a 150 nm thick W film 12 was selectively deposited on the exposed Si surface by a chemical vapor reaction.
  • the W film 12 may be formed by sputtering over the entire surface and by patterning so as to cover at least the high-concentration n-type regions 91 and 101 surfaces.
  • a wiring protection insulating film 13 was deposited using a silicon oxide film to which phosphorus was added (FIG. 37).
  • openings are formed at desired locations in the wiring protection insulating film 13 based on a known method of manufacturing a semiconductor device, and further, a source electrode 14 and a drain electrode 15 are formed by depositing and patterning wiring metal. The wiring including was formed. ( Figure 34).
  • the semiconductor device according to the present embodiment manufactured through the above manufacturing process has a source-drain withstand voltage of 4.7 V and a conventional structure SOI MOS having the same dimensions without the p-type diffusion layer 11 in the source. About 1.5 V higher than normal, usually manufactured on semiconductor substrates A breakdown voltage equivalent to that of MOS of the same dimensions could be secured. Also, in the current-voltage characteristics, no abnormal bump-like characteristics called kink characteristics were observed, and the characteristics were normal. Furthermore, in the source-drain current-gate voltage characteristics, the existence of a leak current at a low gate voltage conventionally observed in SOI / MOS was not observed. Also, no change was found in the leakage current and the threshold voltage even when the drain voltage was changed.
  • the semiconductor device according to the present example was completely eliminated from the characteristics associated with the substrate floating effect.
  • the current-voltage characteristics of the semiconductor device according to this example showed normal characteristics, and it was also found that the crystal defect region 11 formed inside the source and the drain had no adverse effect.
  • the elimination of the above substrate floating effect according to the present embodiment is achieved by changing the thickness of the gate side wall insulating film 8 according to the present embodiment and changing the thickness of the gate defect side wall insulating film 8 from the end of the crystal defect region 11 to the low concentration n-type diffusion layer.
  • the crystal defect region 11 was formed based on the P ion implantation, no elimination of the substrate floating effect was found.
  • the semiconductor device according to the present embodiment is effective in eliminating the substrate floating effect of SOIMOS is effective in regenerating holes into which polycrystals in the crystal defect region 11 formed in contact with the oxide film 2 are injected. It was presumed that it sufficiently acted as a crystal center.
  • the single-crystal Si layer 3 is relatively thick at 20 O nm, and in the substrate region below the channel region, even if a gate voltage equal to or higher than the threshold voltage is applied, the single-crystal Si layer 3 becomes in a depletion layer.
  • a so-called partially depleted structure having a neutral region is obtained.
  • the partially depleted structure is slightly lower than the fully depleted structure at low voltage and high speed operation, it can be easily manufactured under conventional manufacturing conditions using a conventional semiconductor substrate. This shows that the semiconductor device according to the present embodiment can provide a countermeasure against floating of the partially depleted structure MS substrate at low cost.
  • FIG. 38 to 40 are sectional views showing the order of manufacturing steps of a semiconductor device according to another embodiment of the present invention, and FIG. 40 is a complete sectional view thereof.
  • the gate protection insulating film 7 is used as a mask from the state in which the steps up to the formation of the element isolation insulating film 4, the gate oxide film 5, the gate electrode 6, and the gate protection insulating film 7 based on the embodiment 14 are performed.
  • High-concentration ion implantation with low acceleration energy of 2 keV of As, junction depth 1 O nm, surface impurity concentration 1 X Shallow junction n-type high concentration diffusion layers 95 and 105 of 102 and / cm 3 were formed.
  • a gate sidewall insulating film 8 having a thickness of 100 nm is formed in accordance with the first embodiment, and high-concentration ion implantation of P is performed using the gate sidewall insulating film 8 as a mask, and a junction depth of 10 O nm
  • the low resistance source diffusion layer 91 and the low resistance drain diffusion layer 101 were formed (FIG. 38).
  • a wiring protection insulating film 13 was deposited and an opening was formed at a desired location.
  • the n-type low concentration diffusion layer 9 having a minimum impurity concentration of 1 ⁇ 10 16 / cm 3 contacting the lower part of the low resistance source diffusion layer 9 1 and reaching the base oxide film 2 is formed. Formed.
  • the n-type low concentration diffusion layer 10 is simultaneously formed also at the bottom of the drain diffusion layer. After performing a heat treatment for adjusting the activation and diffusion depth of the n-type low concentration diffusion layers 9 and 10, a deposition film 13 1 made of a different material from the wiring protection insulating film 13 is formed on the side surface of the opening. It was selectively left using the dry etching technique.
  • the opening side wall insulating film 13 1 has a meaning that a film serving as an ion implantation mask has a constant thickness from the opening on the side wall, and even if it exists on the bottom of the opening, there is no problem in the next step. Does not occur. From this state, high-energy ion implantation of Si using the opening side wall film 13 1 as a mask was performed based on the conditions of the above Example 14, and the crystal defect region 11 was formed in the n-type low concentration diffusion layer 9. An oxide film was formed near the interface between the two. In the above manufacturing process, the method of using the open side wall film 13 1 to adjust the distance from the end of the crystal defect region 11 to the junction of the n-type low concentration diffusion layer 9 has been described. It may be based on a method of adjusting the depth by heat treatment. In this case, the step of forming the side wall film 131 can be omitted (FIG. 39).
  • FIG. 40 a cross-sectional view of a semiconductor device according to a step of forming a wiring material after removing the opening side wall film 131 is illustrated, but the opening side wall film is left as desired. This does not cause any problems (Fig. 40).
  • the semiconductor device according to the present embodiment manufactured through the above-described manufacturing process, similar to the semiconductor device according to Embodiment 14 described above, no characteristic associated with the substrate floating effect is observed, and a normal partially depleted SOIMOS characteristic is obtained. I got it. Further, in the semiconductor device according to the present embodiment, the elimination of the substrate floating effect can be realized only in the contact hole region. Therefore, there is no restriction on the shape of the source / drain diffusion layer near the gate electrode end that determines the transistor characteristics. Therefore, according to this embodiment, desired transistor characteristics can be realized without the influence of the substrate floating effect.
  • FIG. 41 is a sectional view showing a semiconductor device manufacturing process according to another embodiment (16th) of the present invention
  • FIG. 42 is a completed sectional view thereof.
  • Example 14 after the active region of the single-crystal Si film 3 was separated from each other by forming an element isolation insulating film 4 using a SOI substrate having a thickness of 50 O nm as the single-crystal Si layer 3 According to a desired circuit configuration, a part of the active region was ion-implanted to form a low-concentration n-type region 31.
  • a gate oxide film 5, a gate electrode 61, and a gate protection insulating film 7 were formed on the low-concentration n-type region 31 and the low-concentration P-type region 3 according to Example 14 described above.
  • a W film was used as the gate electrode 61. From this state, ion implantation was performed using the gate electrode 61 as a mask according to Example 14 described above. The above-described ion implantation is performed in the low-concentration P-type region 3 in accordance with the above-described embodiment, by performing P ion implantation for forming the low-concentration n-type diffusion layers 9 and 10 and forming the high-concentration n-type diffusion layer 9K101.
  • low-concentration p-type diffusion layers 90 and 100 are formed by B ion implantation, and high-concentration P-type diffusion layers 92 and 100 are formed. Formed two.
  • the low-concentration n-type diffusion layers 9 and 10 and the low-concentration P-type diffusion layers 90 and 100 are formed so as to reach the oxide film 2, and the maximum impurity concentration is finally 1 ⁇ 10 ′ Vcm.
  • the silicon nitride film is selectively left in the nMOS formation region, and the silicon nitride film is formed only on the side wall of the nMOS gate by anisotropic dry etching.
  • a gate sidewall insulating film 8 having a thickness of 10 O nm.
  • an oxide film was selectively left in the pMOS formation region, and a 20-nm-thick gate sidewall insulating film 8 of an oxide film was formed only on the sidewall of the pMOS gate by anisotropic dry etching.
  • the gate sidewall insulating films 8 of the pMOS and the nMOS may have the same thickness and the same material, if desired.
  • Ar ions are implanted at a dose of 5 ⁇ 10 15 / cm 3 so as to reach the oxide film 2 interface, and the low-concentration n-type diffusion layer 9 is formed.
  • a crystal defect region 11 was buried therein.
  • the formation of the crystal defect region 11 is due to Ar Irrespective of the ion implantation, the ion implantation of Si or the like as in the first embodiment may be used. Due to the influence of the base oxide film 2, the crystal defect region 11 was not monocrystallized in the region in contact with the base oxide film 2 even by the recrystallization heat treatment, and a polycrystalline crystal defect region was retained (FIG. 4). 1).
  • the wiring protection insulating film 13 is deposited and opened at a desired location, and the wiring metal film is deposited and patterned to form a ground potential line 17, an output terminal 18 and a power supply voltage line.
  • a wiring including 19 was formed (FIG. 42).
  • the CMOS, and the pMOS and the nMOS according to the present embodiment manufactured through the above manufacturing process no symptom caused by the substrate floating effect could be observed in any of the pMOS and the nMOS. Furthermore, a through current caused by the substrate floating effect peculiar to SO ICMOS generated between the ground potential line 17 and the power supply voltage line 19 due to the negative fluctuation of the nMOS threshold voltage and the positive fluctuation of the pMOS threshold voltage is also observed. Was not done.
  • the substrate floating effect of the nMOS and the pMOS can be eliminated by the same ion implantation process, and the performance of the CMOS can be improved at low cost without complicating the manufacturing process.
  • the substrate floating effect of the nMOS and the pMOS can be eliminated by the same ion implantation process, and the performance of the CMOS can be improved at low cost without complicating the manufacturing process.
  • the crystal defect region 11 acting as a recrystallization center and the low concentration in the lower part of the channel! ) Type gate region 3 or gate sidewall insulating film 8 for determining the distance between low-concentration n-type regions 31 was formed so as to have a different thickness between nM0S and pM0S.
  • the above is intended to correct the junction depth in consideration of the fact that the junction depth is different due to the difference in impurities between the low-concentration P-type diffusion layers 90 and 100 and the low-concentration n-type diffusion layers 9 and 10.
  • the maximum impurity concentration of the low-concentration p-type diffusion layers 90 and 100 and the low-concentration n-type diffusion layers 9 and 10 is 1 ⁇ 10 15 / cm 3 or more, and 1 ⁇ 10 1 cm 3 It is desirable that the value be in the range of 1 ⁇ 10 16 to 5 ⁇ 10 ′ 7 / cm 3 . This in 5 X 1 0 'Vcm 3 or less, elimination of substrate floating phenomenon is particularly pronounced Chikaraku, whereas 1 X 1 0 16 / cm 3 1/1 0 12 A about the reverse characteristics of the pn junction in the following Small current is generated, which may result in transistor leakage current.
  • the ion implantation process for forming the crystal defect region 11 may be performed only once in the CMOS, and the amorphous formation can be achieved at the interface with the base oxide film 2 in consideration of the thickness of the SOI layer. I just need.
  • the ion implanted element may be any material that does not cause a change in conductivity type in the low-concentration P-type diffusion layers 90 and 100 and the low-concentration n-type diffusion layers 9 and 10. It is preferable to use halogen elements such as Si, Ge, C, etc., and F, C1, etc., and further, rare gas elements such as Ne, Ar, etc.
  • FIG. 43 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment (17th) of the present invention
  • FIG. 44 is a completed sectional view thereof.
  • the thickness of the single-crystal Si film 3 was set to 100 nm, and the high-resistance of 100 nm was formed between the oxide film 2 and the single-crystal Si film 3 having a thickness of 200 nm.
  • a multi-layer SOI substrate having a polycrystalline Si film 20 and a 10 nm thick silicon oxide film 21 was used.
  • the impurity concentration of the p-type low-concentration active region 3 and the n-type low-concentration active region 31 in the single-crystal Si film 3 was set to an extremely low value of 1 ⁇ 10 ′ Vcm 3 , respectively. That is, in this example, a fully depleted phase-trapping MOS field-effect transistor was manufactured.
  • the high-resistance polycrystalline Si immediately below the region where the nMOS gate electrode 7 is to be formed is formed prior to the formation of the gate oxide film 5, the gate electrode 6, the gate protection insulating film 7, and the gate sidewall insulating film 8, the high-resistance polycrystalline Si immediately below the region where the nMOS gate electrode 7 is to be formed is formed.
  • a high-concentration P-type impurity region 22 having an impurity concentration of 2 ⁇ 10 1 cm 3 is formed in the film 20, and an impurity concentration 2 is formed in the high-resistance polycrystalline Si film 20 directly below the region where the pMOS gate electrode 7 is to be formed. It was preformed X 1 0 1 cm 3 comprising a high concentration n-type impurity region 2 3 (4 3).
  • a semiconductor device was manufactured from the state shown in FIG. 43 according to Example 16 above. However, in the low-concentration n-type diffusion layer 9 adjacent to the lower part of the nMOS source high-concentration n-type diffusion layer 9 1, and the source in the pMOS A recombination center region 11 composed of a crystal defect layer is formed in the low-concentration p-type diffusion layer 90 adjacent to the lower portion of the high-concentration p-type diffusion layer 90 by an Ar ion implantation process so as to be in contact with the base oxide film 2. did.
  • the junction depth of the source high-concentration n-type diffusion layer 91 and the high-concentration p-type diffusion layer 102 was set to about 5 Ornn.
  • the low-concentration n-type diffusion layer 9 and the low-concentration P-type diffusion layer 90 are configured so that their bottoms are in contact with the base oxide film 2 and their maximum impurity concentrations are from 1 ⁇ 10 16 to 2 ⁇ 10,7 . It was set as become / cm 3. Further, a W film 12 having a thickness of 10 O nm based on a chemical vapor reaction was selectively deposited on the entire surface of the source and drain except for the gate and gate sidewall insulating film portions, and then wiring was performed in accordance with the third embodiment. By forming the protective insulating film 13 and opening it at a desired location, and further depositing a wiring metal film and patterning the same, wiring including the ground potential line 17, the output terminal 18 and the power supply voltage line 19 is formed. Formed (Fig. 44).
  • the pMOS and the nMOS are not observed with any symptom caused by the floating substrate effect as in the above embodiment.
  • the source / drain current at a gate and drain voltage of 2 V of the semiconductor device according to the present embodiment is at least 1.4 times larger than that of the semiconductor device of Embodiment 16 in both pMOS and nMOS. Currentization has been achieved. In the non-saturation characteristic region where the power is also low and the drain voltage is low, an extremely steep drain conductance characteristic was obtained as compared with the semiconductor device of Example 16 described above.
  • the delay time per stage was 12 ps, which was as high as 6 ps as compared with the ring oscillator according to the third embodiment.
  • the high-concentration p-type impurity region 22 and the high-concentration n-type impurity region 23 act as a punch-through prevention mechanism, and the thin silicon oxide film 21 serves as an impurity diffusion mask for high-temperature heat treatment during the manufacturing process. Therefore, the ultra-high-speed and large-current characteristics of the semiconductor device according to the present embodiment make it possible to set the impurity concentration of the P-type low-concentration active region 3 and the n-type low-concentration active region 31 constituting the channel to an extremely low concentration. It is considered that the deterioration of mobility due to impurity scattering was prevented.
  • the single-crystal Si layer 3 is extremely thin at 50 feet, and the substrate impurity concentration in the channel region is set as low as 1 ⁇ 10 ′ Vcm 3 . Therefore, the neutral region does not exist in the single-crystal Si layer 3 in the channel region under the gate voltage condition higher than the threshold voltage due to the limitation of the charge amount in the single-crystal Si layer 3, and the single-crystal Si layer 3 is in a completely depleted state. This can effectively induce mobile charges in the channel, which is the current drive source, and is suitable for increasing the current. That is, it is suitable for low voltage and high speed operation.
  • FIGS. 45 to 49 below illustrate examples of application of the semiconductor device disclosed in the embodiments described above.
  • FIGS. 45A and 45B are diagrams showing application examples of the semiconductor device according to the embodiment of the present invention.
  • a random access memory device (referred to as DRAM) is constituted by a semiconductor device based on the present invention.
  • the memory cell that is one storage unit is
  • the semiconductor device according to the present invention is formed by connecting one semiconductor device and one capacitance element Cs in series, and is connected to a bit line as a data transmission line and a word line for input / output control.
  • the random access memory device is composed of a memory cell array in which memory cells are arranged in rows and columns and a control peripheral circuit.
  • the peripheral circuit is also composed of the semiconductor device of the present invention.
  • the column address signal and the row address signal are shifted to reduce the number of address signal terminals for memory cell selection, and the multiplexed and applied force ⁇ RAS and CAS are each pulse signal, and clock generators 1 and 2 are used. Under control, the address signal is distributed to the row decoder and the column decoder.
  • Specific address lines and bit lines are selected according to address signals distributed to the row decoder and the column decoder by an address buffer as a buffer circuit.
  • a sense amplifier using a flip-flop type amplifier is connected to each bit line, and amplifies a signal read from a memory cell.
  • the pulse signal WE controls the switching between writing and reading by controlling the writing clock generator.
  • D is a write and read signal.
  • each of the semiconductor devices constituting this application example is constituted by the semiconductor device according to the present invention, a high-speed operation in which the access time can be reduced by 30% or more compared with the conventional device can be realized.
  • the worst-case refresh characteristics were 0.5 seconds, which was a 10-fold improvement over the past.
  • the high-speed operation described above is due to the effect of reducing the parasitic capacitance by the SOI structure, and the increase in current based on the seventh embodiment.
  • the improvement of the refresh characteristics is based on the reduction of the junction area by the SOI structure and the elimination of the threshold voltage fluctuation by eliminating the substrate floating effect.
  • FIGS. 46A and 46B are diagrams showing another application example of the semiconductor device according to the embodiment of the present invention.
  • This example is an example in which a constant write / read type storage device (referred to as SRAM) is constituted by a semiconductor device based on the present invention.
  • a memory cell as one storage unit is composed of two sets of complementary MOSs according to the present invention and two MOSs (referred to as transfer MOSs) for controlling signal input / output, as shown in FIG. 46B. It consists of.
  • This SRAM is composed of a memory cell array in which memory cells are arranged in rows and columns and a control peripheral circuit, and the peripheral circuit is also composed of the semiconductor device of the present invention.
  • Configuration of this example The configuration is basically the same as that of Figs. 45A and 45B, and an address transition detector is provided to achieve the high speed and low power consumption of the SRAM. Controlling.
  • the row decoder is composed of two stages, a predecoder and a main decoder.
  • the chip select is a circuit for avoiding contention between information writing and reading data by the signals CS and WE, and making the write cycle time and the read cycle time almost equal to enable high-speed operation.
  • the power supply voltage can be reduced from 3.5 V to 2.0 V and the access time can be reduced by 30% or more compared to the conventional device, because each of the semiconductor devices constituting the semiconductor device of this example is a semiconductor device according to the present invention.
  • the high speed that can be achieved was realized. This is due to the effect of reducing the parasitic capacitance by the SOI structure, the increase in current based on the seventh embodiment, and the drastic improvement in drain conductance at low voltage. Furthermore, the threshold voltage fluctuation due to the elimination of the substrate floating effect has been eliminated, and the operation range of the sense amplifier has been reduced to enable higher speed.
  • FIG. 47 is a diagram showing still another application example of the semiconductor device according to the embodiment of the present invention.
  • This example is an example in which a logic circuit device is configured using a semiconductor device according to the present invention.
  • the figure shows an example of a composite gate circuit.
  • the present invention is applied to a logic circuit including a NAND circuit and a NOR circuit in a composite gate circuit by a semiconductor device according to the present invention.
  • each of the semiconductor devices constituting the semiconductor device of the present embodiment is constituted by the semiconductor device according to the present invention, the delay time can be reduced by 20% or more compared with the conventional logic circuit device. This is due to the effect of reducing the parasitic capacitance by the SOI structure, the increase in current according to the seventh embodiment, and the drastic improvement in drain conductance at low voltage.
  • FIG. 1 Another application example will be described with reference to a computer configuration diagram in FIG. This example is an example in which the semiconductor device of the present invention is applied to a high-speed large-scale computer in which a plurality of processors 500 for processing instructions and operations are connected in parallel.
  • the semiconductor device 500 of the present invention having 10 to 30 pixels on one side includes the device 500, the system control device 501, the main storage device 502, and the like.
  • a processor 500 for processing these instructions and calculations, a system controller 501, and a data communication interface 503 composed of a compound semiconductor device are mounted on the same ceramic substrate 506. Further, the data communication interface 503 and the data communication control device 504 are mounted on the same ceramic substrate 507.
  • the ceramic substrates on which the ceramic substrates 506 and 507 and the main storage device 502 were mounted were mounted on a substrate having a size of about 50 cm on a side or smaller, thereby forming a central processing unit 508 for a computer. .
  • the data communication in the central processing unit 508, the data communication between a plurality of central processing units, or the data communication between the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted are illustrated by arrows in FIG. The operation was performed through an optical fiber 510 indicated by a dotted line.
  • a processor 500 for processing instructions and operations, a system controller 501, and a main storage device 502 are formed by using the semiconductor device according to the present invention in parallel, and operate at high speed, and Since communication is performed using light as a medium, the number of command processing operations per second could be greatly increased.
  • FIG. 49 is a diagram showing still another application example of the semiconductor device according to the embodiment of the present invention.
  • the present example is a signal transmission processing device constituted by the semiconductor device according to the present invention, particularly a signal transmission processing device relating to an asynchronous transmission system (referred to as an ATM switch).
  • the information signal transmitted in series at a very high speed by an optical fiber is converted into an electric signal (0 / E conversion) and is converted into a parallel signal (SZP conversion). It was introduced into an integrated circuit (BFMLS I) composed of a semiconductor device based on the invention.
  • the electrical signal that has been addressed by the integrated circuit is output via a serialized (P / S conversion) and optical signal (E / 0 conversion) optical fiber.
  • the BFMLS I consists of a multiplexer (MUX), a buffer memory (BFM), and a separator (DMUX).
  • MUX multiplexer
  • BFM buffer memory
  • DMUX separator
  • the BFM LSI is controlled by a memory control LSI and an LSI (empty address FIFO memory LSI) having an empty address distribution control function.
  • This signal transmission processor is an ultra-high-speed transmission signal sent regardless of the address to be transmitted.
  • the BFM LSI is constituted by the semiconductor device based on the present invention, and the operation speed is three times faster and less expensive than the conventional BFMLSI. It has become possible to reduce the storage capacity of ML SI to about 1/3 that of the conventional model. As a result, the manufacturing cost of the ATM exchanger was reduced.
  • FIG. 50 is a view showing a completed cross section of the semiconductor device according to the eighteenth embodiment of the present invention.
  • Example 6 instead of the ion implantation for forming the high-concentration n-type diffusion layers 91 and 101, the selective removal of the Si layer on the high-concentration P-type diffusion layer 11 and the high-concentration n The polycrystalline Si film 24 to which the type impurity was added was selectively left.
  • ion implantation for forming high-concentration p-type diffusion layers 92 and 102 selective removal of Si layer on high-concentration n-type diffusion layer 110 and high-concentration p-type impurities Selective remaining of the added polycrystalline Si film 25 was performed.
  • a method of selectively depositing only the Si exposed surface based on a low-pressure chemical vapor reaction using dichlorosilane as a raw material was used for selectively leaving the polycrystalline Si film 25.
  • it may be formed by depositing amorphous or polycrystalline Si over the entire surface, implanting P and n-type impurities at desired locations with high concentration ions, and then patterning the Si film. Good.
  • CMOS of the present example no symptom caused by the substrate floating effect was observed for any of pMOS and nMoS as in the semiconductor device of Example 6.
  • a polycrystalline Si film doped with a high concentration n-type impurity and a polycrystalline Si film doped with a high concentration P-type impurity Good ohmic characteristics were exhibited between 25 and the high-concentration n-type diffusion layer 110 due to the presence of the crystal grain boundaries of the polycrystalline film.
  • the polycrystalline Si films 24 and 25 can be made thicker so as to reach the upper part of the monocrystalline Si film surface if necessary and to be located on the side of the gate electrode, so that the source resistance can be reduced. .
  • FIG. 51 is a view showing a completed cross section of a semiconductor device according to another embodiment (No. 19) of the present invention. It is.
  • Example 6 a single crystal Si substrate 30 having the same specification as the single crystal Si layer 3 and having a thickness of 62 ⁇ m was used in place of the SOI substrate as a substrate constituting pMOS and nMOS.
  • c instead of the low-concentration n-type region 31 and the low-concentration p-type region 3, a low-concentration n-type well 32 and a low-concentration P-type well 33 are formed based on a known method for manufacturing a semiconductor device.
  • a stacked film of the high-concentration n-type polycrystalline Si film 40 and the W film 12 is formed on the high-concentration n-type diffusion layers 91 and 101, and the high-concentration p-type diffusion layer 92 is formed.
  • a stacked film of a high-concentration p-type polycrystalline Si film 41 and a W film 12 was formed to reduce source resistance.
  • both the pMOS and the nMOS are caused by a cell potential floating effect such as a threshold voltage fluctuation, although no electrode for supplying a cell potential is provided. No cord symptoms were observed. In other words, the need for a fixed gel potential fixed electrode, which was required in the conventional complementary MOS, was eliminated, thereby contributing to a reduction in chip occupation area. Further, in the semiconductor device according to the present embodiment, the source resistance could be reduced by the effect of the laminated film of the low-resistance polycrystalline film and the W film stacked on the source.
  • the substrate floating effect of pMOS on the SOI substrate which was impossible in the past, can be solved by a low-cost manufacturing method. Therefore, according to the present invention, the substrate floating effect can be completely eliminated by a low-cost manufacturing method for CMOS on the SOI substrate. Thus, a low-voltage, low-power, ultra-high-speed semiconductor device and a system including the semiconductor device can be provided.

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Abstract

La présente invention concerne un transistor bipolaire parasite dans lequel des porteurs minoritaires (AS) produits dans un substrat silicium sur isolant (1) par injection des porteurs (AS) dans la source d'un transistor MOS formé sur le substrat (1). Une zone dont la conductivité est opposée à celle de la couche à diffusion de source (11) du transistor MOS et un mécanisme de centres de recombinaison sont formés dans la couche à diffusion de source (11).
PCT/JP1996/002184 1995-08-07 1996-08-02 Dispositif a semiconducteur et procede de fabrication WO1997006564A1 (fr)

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GB2358084A (en) * 2000-01-07 2001-07-11 Seiko Epson Corp Field effect transistors
US6770517B2 (en) 1997-06-19 2004-08-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
JP2008192760A (ja) * 2007-02-02 2008-08-21 Oki Electric Ind Co Ltd 半導体装置、半導体装置の製造方法及びその使用方法
WO2016166930A1 (fr) * 2015-04-15 2016-10-20 信越半導体株式会社 Procédé de fabrication de dispositif à semi-conducteur et procédé d'évaluation de dispositif à semi-conducteur
WO2018020961A1 (fr) * 2016-07-26 2018-02-01 信越半導体株式会社 Procédé de fabrication de dispositif à semi-conducteur et procédé d'évaluation de dispositif à semi-conducteur

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US6770517B2 (en) 1997-06-19 2004-08-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
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WO2016166930A1 (fr) * 2015-04-15 2016-10-20 信越半導体株式会社 Procédé de fabrication de dispositif à semi-conducteur et procédé d'évaluation de dispositif à semi-conducteur
JP2016207682A (ja) * 2015-04-15 2016-12-08 信越半導体株式会社 半導体装置の製造方法及び半導体装置の評価方法
WO2018020961A1 (fr) * 2016-07-26 2018-02-01 信越半導体株式会社 Procédé de fabrication de dispositif à semi-conducteur et procédé d'évaluation de dispositif à semi-conducteur
JP2018018872A (ja) * 2016-07-26 2018-02-01 信越半導体株式会社 半導体装置の製造方法及び半導体装置の評価方法
US10886129B2 (en) 2016-07-26 2021-01-05 Shin-Etsu Handotai Co., Ltd. Method for manufacturing semiconductor device and method for evaluating semiconductor device

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