WO1996037960A2 - Plan de gestion de puissance configurable - Google Patents

Plan de gestion de puissance configurable Download PDF

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Publication number
WO1996037960A2
WO1996037960A2 PCT/US1996/007571 US9607571W WO9637960A2 WO 1996037960 A2 WO1996037960 A2 WO 1996037960A2 US 9607571 W US9607571 W US 9607571W WO 9637960 A2 WO9637960 A2 WO 9637960A2
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WO
WIPO (PCT)
Prior art keywords
clock
power management
management system
circuit
oscillator
Prior art date
Application number
PCT/US1996/007571
Other languages
English (en)
Other versions
WO1996037960A3 (fr
Inventor
Michael J. Shay
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to EP96916586A priority Critical patent/EP0772911B1/fr
Priority to DE69629780T priority patent/DE69629780T2/de
Publication of WO1996037960A2 publication Critical patent/WO1996037960A2/fr
Publication of WO1996037960A3 publication Critical patent/WO1996037960A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L3/00—Starting of generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to power management systems, and more particularly, to a configurable power management system.
  • the present invention provides an oscillator interface for use in a power management system.
  • An interface circuit interfaces with an external oscillator used as a source of oscillations.
  • a clock stabihzauon filter masks out spu ⁇ ous crystal frequencies in the oscillations dunng start-up of the power management system following an enabling of a feedback loop
  • the clock stabihzauon filter has circuitry which provides that the oscillauons will start with a ⁇ s g transiuon after filtering.
  • a bypassing circuit enables the clock stabihzauon filter when the external oscillator is a crystal oscillator and bypasses the clock stabihzauon filter when the external oscillator is a can oscillator.
  • a masking circuit masks the oscillauons from the rest of the power management system.
  • the masking circuit has circuitry which disables the clock masking after a falling edge of the oscillauons and starts back up with a rising transition of the oscillations
  • the present mvenuon also provides a power recycle circuit for use in a power management system.
  • An input receives a clock signal.
  • a detecuon circuit for senses a minimum disable pulse when a clock signal is received and when a clock signal is not received.
  • a power recycle circuit generates a power recycle signal in response to the minimum disable pulse.
  • a state machine holds the power recycle signal for at least two clock cycles.
  • the present invenuon also provides a pad clock and self test circuit for use in a power management system.
  • An input receives an oscillator clock.
  • a clock generauon circuit generates at a clock output a first pad clock having a frequency approximately equal to one-half a frequency of the oscillator clock, a second pad clock having a frequency that is forced equal to a programmable fracuon of the frequency of the oscillator clock, and a low signal.
  • the clock generauon circuit has a first operaung mode in which the second pad clock is generated and a second mode in which internal signals of the power management system can be observed and the clock output is forced to a known level
  • the present invenuon also provides a clock enable circuit for use in a power management svstem
  • a clock branch generator generates a first clock signal to d ⁇ ve a se ⁇ uenual device which is internal to the power management system.
  • a clock enabling/disabling circuit disables the first clock after a falling edge on an internal source clock, holds the first clock low du ⁇ ng disabling, re-enables the first clock after a falling edge of the internal source clock, and subsequently begins a first ⁇ se of the first clock with a next ⁇ sing transition of the internal source clock
  • the clock enabling/disabling circuitry does not stop an external CPU core clock when the external CPU is actively performing a bus cycle
  • the present invention also provi ⁇ es a power level detect circuit for use m a power management system
  • An analog voltage-level detector interface has a programmable ovemde function for provi ⁇ m ⁇ a digitally encoded voltage level as an outDut which is used for global confi urauon.
  • An input receives an analog enable signal to turn on a DC-current source of an external voltage-level detector and a read strobe A voltage-level detector input is sampled
  • the present invention also provides an internal source clock generation circuit for use in a power management system.
  • a synchronous counter with a synchronous load to a count of one and an asynchronous clear has a plurality of count output signals.
  • a first multiplexer having two outputs is coupled to the synchronous counter and receives the plurality of count output signals.
  • a second multiplexer having one output is coupled to the first multiplexer.
  • a flip-flop is coupled to the output of the second multiplexer, and a clock referenced to an external oscillator clock samples an
  • the present invention also provides a power-save mode change detection circuit for use in a power management system including an internal source clock, a first bank of flip-flops coupled to the internal source clock, and a second bank of flip-flops coupled to the internal source clock.
  • a comparator compares the first and second banks of flip-flops and generates an equality signal when there is a difference between storage values of the first and second banks of flip-flops.
  • a change indicator is asserted when a power-save mode is asserted in one of the first and second banks of flip-flops.
  • the change indicator is sampled with a clock which is referenced to a falling edge of a system clock, and a synchronous load 1 pulse is generated until a next rising edge of an internally qualified reference an external oscillator clock.
  • FIG. 1 is a block diagram illustrating a power management system in accordance with the present invention.
  • FIG. 2 is a block diagram illustrating a system which incorporates the power management system shown in Figure 1.
  • Figure 3 is a schematic diagram illustrating the configuration unit shown in Figure 1.
  • Figure 4 is a schematic diagram illustrating the external oscillator interface shown in Figure 1.
  • Figure 5A is a schematic diagram illustrating the powergood qualification block shown in Figure 1.
  • Figure 5B is a state diagram illustrating the operation of the powergood qualification schematic shown in Figure 5A.
  • Figure 6 is a schematic diagram illustrating the pad clock and self test block shown in Figure 1.
  • Figures 7A and 7B are schematic diagrams illustrating the clock enable block shown in Figure 1.
  • Figures 8 and 9 are schematic diagrams illustrating the power level detect block shown in Figure 1.
  • Figure 10 is a schematic diagram illustrating the internal source clock generation block shown in Figure 1.
  • Figure 11 is a schematic diagram illustrating the power-save mode change detection block shown in Figure 1.
  • FIG. 1 there is illustrated a power management system 30 in accordance with the present invention.
  • the power management system 30 is ideal for being implemented in the system 32.
  • the system 32 is described in the data sheet entitled "Elentari Optimized 32-bit 486-class Controller With On-chip Peripherals for Embedded Systems", authored by National Semiconductor Corporation of Santa Clara. California, a copy of which is attached hereto as Appendix A and is incorporated herein by reference.
  • the system 32 includes a CPU 34, a DMA controller 36, a DRAM memory controller 38, a PCMCIA controller 40, a bus interface unit (BIU) 42, an ECP parallel port 44, an LCD controller 46, as well as other components.
  • BIU bus interface unit
  • ECP parallel port 44 an LCD controller 46
  • other components such as other components.
  • Appendix B is a copy of a document entitled “Elentari Core Internal Bus Spec” which is also incorporated herein by reference.
  • Appendix C is a copy of a document entitled “Internal Peripheral Bus Signals” which is also incorporated herein by reference.
  • the power management system 30 includes a number of power saving mechanisms that can be combined to achieve comprehensive power savings under a variety of system conditions.
  • the core processor 34 power consumption can be controlled by varying the processor/system clock frequency.
  • the internal CPU clock can be divided by 4, 8, 16, 32 or 64.
  • the internal processor clock will be disabled.
  • an crystal oscillator circuit or external oscillator it can be disabled. For maximum power savings, all internal clocks can be disabled (even the real-time clock oscillator).
  • Some peripherals notably the timer 48 and the PCMCIA interface 40 can be switched between a fixed frequency (external oscillator/2) and the CPU clock. When the CPU clock is being divided, this can reduce their power consumption. Note that the clocks for other on-board peripherals can be individually or globally controlled.
  • the power management control registers discussed below, the internal clocks to the DMA controller 36, the ECP port 44, the three-wire interface 50, the timer 48, the LCD controller 46, the DRAM controller 38, the PCMCIA controller 40 and the UART 52 can be disabled.
  • the power management system 30 can programmed the of use CMOS level I/Os or TTL level I/O settings in the system 32.
  • the external SYSCLK can be disabled via a bit in the Power Management Control Register.
  • the power management system 30 includes several modes of operation which are listed here in decreasing power consumption order (i.e., full power to least power).
  • In the Normal Mode all clocks are at full speed, with the Timer, PCMCIA, SYSCLK connected to cpu_dock or external OSC/2, and the UART, DRAM refresh logic, and LCD Controller connected to OSC dock, and the RTC connected to RTC_osc.
  • In the Power Save Mode first, the CPU clock is divided by 4, 8, 16, 32 or 64, with the Timer, PCMCIA, SYSCLK connected to external OSC/2, the UART, DRAM logic, and LCD Controller connected to OSC, and the RTC connected to RTC_osc.
  • the CPU clock is divided by 4, 8, 16, 32 or 64 with the Timer, PCMCIA, SYSCLK connected to cpu_clk, UART, DRAM logic, LCD Controller connected to OSC, and RTC connected to RTC_osc.
  • Peripheral Power Down Mode the individual Peripherals can be disabled.
  • Idle Mode the CPU clock is disabled with all peripherals unaffected, and RTC connected to RTC_osc.
  • the Crystal Oscillator Circuit Disable/Power Down Mode first, if a crystal oscillator circuit is being used to drive d e system 32, this mode will disable the oscillator circuit (NOTE: after being turned back on, it will take approximately 1 msec for the external crystal to stabilize).
  • Power Down mode will disable all the system 32 clocks except for the RTC_osc. (NOTE: This is much faster upon recovery, as there is no stabilization delay). It should be noted that the RTC oscillator is always enabled even during power down mode; it can be disabled if desired.
  • the Timer 48, PCMCIA 40, SYSCLK 1) uses cpu_clk (full speed or divided by 4 8, 16, 32 or 64); 2) or can use external OSC_CLK/2 (when cpu_clk is divided); 3) can be individually disabled.
  • the UART 52, DRAM refresh logic, LCD Controller 46 1) Connected to OSC; 2) can be individually disabled.
  • the ECP 44 and the Three-wire Serial Interface 50 1) Connected to OSC_CLK/2; 2) can be individually disabled.
  • the DMA Controller 36 and Bus Interface Unit 42 1) Uses cpu_clk (full speed or divided).
  • the DRAM Controller 38 1) Must use OSC_CLK for DRAM refresh cycles; 2) Sequencer can selectably use cpu_clk or 2*cpu_clk; 3) For state machine logic, must use cpu_clk.
  • the Real-Time Clock 1) Uses RTC_ose - typically always enabled, but it can be disabled through the RTC interface.
  • the Global Peripheral Clock Disable Enable 1) Controls DMA Controller, ECP, Three- ire Interface, and UART.
  • the power management system 30 includes several power management modes. Power saving features include the following. In Idle Mode the internal clock to the CPU 34 will be disabled. All enabled peripheral blocks will continue to operate. Any interrupt or reset will re-enable the internal clock to the CPU 34. It should be noted that when the CPU 34 is in Idle Mode, the instruction cache cannot snoop. Normally, the cache will snoop the addresses to see if a cache address is being updated. If so, it flushes the cache. Therefore, the user's can take the appropriate action when the CPU 34 is idled. Also, when the CPU 34 is in Idle Mode, the BIU 42 is designed to mimic the CPU 34 during DMA interchanges between memory and peripherals.
  • the BIU 42 By responding to DRQs and generating DACKs, HOLDs and HOLDAs signals as required, the BIU 42 eliminates the need to reactivate the CPU 34 during such transfers as screen updates from memory to the LCD controller 46. This gives the designer added flexibility in conserving power while maintaining basic system functions.
  • a Power-save Mode reduces the internal CPU 34/system clock's frequency by dividing the internal CPU clock by 4, 8, 16, 32 or 64 (Refer to Power Management Register 1 for more information)
  • the internal clocks for the UART 52, DRAM refresh logic, LCD Conttoller 46 and RTC will be unaffected in this mode.
  • the Timer, PCMCIA and SYSCLK all have selectable clock sources between a fixed frequency, which is the external oscillator/2 and cpu_clk. Only when a cpu_clk source is selected will these clocks be affected by Power-save mode.
  • the Crystal Oscillator Circuit Disable function disables the feedback output of the crystal oscillator circuit (i.e. forces OSCX2 low). Normally, the feedback output is used to provide a high-gain feedback to an external crystal to start, stabilize, and maintain a reference oscillation from the crystal. If the feedback is disabled the oscillation will stop. After the feedback output is re-enabled, it takes approximately 1 msec for the external crystal to start and stabilize. On-chip, there is a lowpass filter and counter to insure that none of the start-up and stabilize oscillations are allowed to pass into the rest of the chip. If an external TTL or CMOS oscillator is used then the feedback output can be disabled to save power. Also, the low-pass filter and counter can be bypassed by setting bit 7 of Power Management Configuration Register 4. This latter action may be useful when an external TTL or CMOS oscillator is used.
  • the power-up sequence is as follows: 1) Configure the LCD control registers; 2) Apply V DD (5V or 3V) to the display; 3) Enable the LCD clock from the power management registers - this must be done within 20 msec of applying V DD ; 4) Enable the LCD controller. 5) Within 20 msec, max after applying the LCD clock, apply V EE (22V/-26V) to the display.
  • the power-down sequence is as follows: 1) Remove V EE from the display: 2) Disable the LCD controller; 3) Within 20 msec, of removing V EE , disable the LCD clock; 4) Within 20 msec, of removing the LCD clock, remove V DD from the display. The LCD clock should never be disabled when the LCD is enabled.
  • the internal clocks for various internal peripherals may be individually enabled/disabled via bits of Power Management Registers 2 and 3 (discussed below).
  • a peripheral's internal clock should only be disabled if that internal peripheral is not to be used.
  • With respect to global enable/disable of peripheral clocks when bit 7 of Power Management Register 2 is set to a one, the internal clocks to the DMA Controller 36, ECP 44, Three- Wire Interface 50, and UART logic 52 will all be disabled. When that bit is a zero, the individual peripheral clock enable/disable bits will determine if the individual peripheral clocks are enabled or not.
  • the DRAM 38 and LCD Controllers 46, PCMCIA 40, BIU 42 and Timer 48 are not affected by global clock enabling/disabling.
  • the system 32 I/Os are power supply-level configurable.
  • the power management system 30 controls voltage sensing and setting for I/O supply-level configuration.
  • the power management system 30 has the capability to set the operating voltage through firmware (Bit 5 of Power Management Register 4).
  • the power management system 30 includes several Power Management Configuration Registers.
  • the Configuration Register Unit (CRU) 54 contains the configuration registers for controlling the operation of the power management system 30.
  • the CRU 54 also contains a peripheral bus interface for reading and writing of the configuration registers.
  • Power Management Register One 56 is a read/write register and has an I/O map address of EF90h.
  • the bit assignments are as follows. Bit 7 is reserved. Bit 6 is the Idle Mode selection bit IDLE. A “1" sets the chip in Idle Mode (cpu_clk disabled). All resets and interrupts force this bit to a "0". Bit 6 is the oscillator disable bit COSCD — CPU (used with crystal oscillator). A "1" disables the CPU oscillator. All resets and interrupts force this bit to a "0”. Bit 4 is a Power-down Mode selection bit PDM (used with external OSC). A “1" sets the chip to Power-down Mode. All resets and interrupts force this bit to a "0".
  • PDM Power-down Mode selection bit
  • Bit 3 is Power-save Mode selection bit PSVM (divides cpu_clk). A “1" sets the chip to the Power-save Mode. All resets force this bit to a "0".
  • Bits 2-0 are Power-save Mode clock division bits SVB[2:0]. All resets force these bits to a "0". Table A illustrates the operation of these bits.
  • Power Management Register Two 58 is a read/w ⁇ te register and has an I/O map address of EF91h.
  • the bit assignments are as follows.
  • Bit 7 is a Global pe ⁇ pheral clock disabling selecUon bit GDIS. A “1” causes global pe ⁇ pheral clock disabling. All resets force this bit to a "0”.
  • Bit 6 is ECP clock disable selection bit ECP. A “1” disables the ECP clock. All resets force this bit to a "0”.
  • Bit 5 is an LCD clock disable selection bit LCD. A “1” disables the LCD clock. All resets force this bit to a "0”.
  • the LCD Conttoller 46 is not affected by global clock enabling/disabling (GDIS, bit 7).
  • Bit 4 is a DMA clock disabling selecUon bit DMA. A “1” disables the DMA clock All resets force this bit to a "0”.
  • Bit 3 is a timer block clock disabling selection bit TIMR. A “1” disables the Timer Clock. All resets force this bit to a "0”. The ttmer is not affected by global clock enabling/disabling (GDIS, bit 7).
  • Bit 2 is a three- wire block clock disabling selecUon bit TWIR. A “1” disables the Three-wire Clock. All resets force this bit to a "0”.
  • Bit 1 is a DRAM block clock disabling selection bit DRAM. A “1” disables the DRAM Clock.
  • Bit 0 is a UART block clock disabling bit UART. A “1” disables the UART Clock. All resets force this bit to a "0".
  • Power Management Register Three 60 is a read/w ⁇ te register and has an I O map address of EF92h.
  • the bit assignments are as follows. Bit 7 is reserved. Bit 6 is an External Driver Configurauon bit DRVCON for system bus and DRAM interface I/Os. This bit only has an affect when the interface SETV bit is set to a "1". A "1" guarantees CMOS level output voltages/drive. A “0” guarantees TTL level output voltage/drive (low noise I/O configurauon). Bit 5 is a PCMCIA Clock reference Selecuon bit PCS. A “1” corresponds to Cpu_clk clock reference (affected by Power Save Mode), and a "0" corresponds to standard clock reference (not affected by Power Save Mode).
  • Bit 4 is a PCMCIA block clock disabling selection bit PCMCIA. A “1” disables the PCMCIA clock. All resets force this bit to a "0".
  • Bit 3 is a Timer Clock reference Selection bit TCS. A “1 " corresponds to Cpu_clk clock reference (affected by Power Save Mode), and a "0" co ⁇ esponds to standard clock reference (not affected by Power Save Mode) All resets force this bit to a "0”.
  • Bit 2 is a SYSCLK clock disabling selection bit SYSCLK. A “1” disables the SYSCLK Only PWRGOOD reset forces this bit to a "0).
  • Bit 1 is a SYSCLK reference Selection bit SCS.
  • a “1” corresponds to Cpu_clk clock reference (affected by Power Save Mode), and a “0” corresponds to standard clock reference ( not affected by Power Save Mode) Only PWRGOOD reset forces this bit to a "0".
  • Bit 0 is a DRAM sequencer clock frequency mode bit SEQU.
  • a “ 1 " sets the same frequency as the Cpu_clk clock reference, and a “0" doubles the frequency of the Cpu_clk clock reference. Only PWRGOOD reset forces this bit to a "0".
  • Power Management Register Four 62 is a read/w ⁇ te register and has an I/O map address of EF93h.
  • the bit assignments are as follows Bit 7 is an external clock source desc ⁇ ption bit CAN_OSC A " 1 " co ⁇ esponds to a CMOS or TTL oscillator, and a "0" corresponds to a crystal oscillator Onl PWRGOOD reset forces this bit to a "0".
  • Bit 6 is reserved.
  • Bit 5 is a software setting of Operattng Voltage bit SETV. A “1" sets 5V operaung voltage, and a "0” sets 3 3V operaung voltage (default) Only PWRGOOD reset forces this bit to a "0".
  • Bits 4-0 are reserved
  • the power management system 30 includes seven other major paruuons Refer ⁇ ng to Figure 4, the External Oscillator Interface (EOI) 64 contains the circuitry that interfaces with an external oscillator
  • the external oscillator may be a crystal or a can
  • the circuitry is responsible for controlling the feedback loop of the analog interface to the external crystal When the feedback look is enabled, the external crystal is forced to oscillate, when disabled the external crystal can not oscillate If a can oscillator is used the feedback conttol does not affect the operaUon of the external oscillator, and thus an oscillaUon will pass into the external interface circuitry whether or not the feedback look is enabled
  • Feedback disabling may be reset to an enabled state by any one of the following ways: powe ⁇ ng-down and back-up, sending out a watchdog reset (the watchdog timer is d ⁇ ven by a separate clock coming from the real-Ume clock), and a maskable or non-maskable interrupt
  • the feedback loop is enabled by programming a one in the COSCD bit in configura
  • the EOI 64 also contains a clock stabihzauon filter for masking out spu ⁇ ous crystal frequencies du ⁇ ng its start-up following the enabling of the feedback loop
  • the filter is used when crystals are the source of oscillauons; otherwise, when an external can oscillator is used (programmed as the clock source), the filter is bypassed
  • the bypassing is controlled by programming the CAN_OSC bit in configurauon register four 62 to a "1" Circuitry is used to guarantee that clock will come up after f ⁇ lte ⁇ ng, starting with a ⁇ smg transition, without any logic-generated spu ⁇ ous glitches
  • the EOI 64 contains a circuit that masks the incoming clock from the rest of the power management block as well as the rest of the chip (independent of the previously desc ⁇ bed functionality).
  • the circuit allows an external frequency to come into the part but stay isolated within the EOI 54.
  • the clock masking is enabled by programming a one in the PDM bit in configurauon register one 56 to a "1".
  • General clock masking may be reset to an enabled state by any one of the following ways- powe ⁇ ng- down and back-up, sending out a watchdog reset (the watchdog umer is d ⁇ ven by a separate clock coming from the real-Ume clock), and a maskable or non-maskable interrupt Circuitry is used to guarantee that the clock masking is disabled after a falling edge and starts back up with a nsmg transition, without any logic-generated spu ⁇ ous glitches (Power Down Mode)
  • the Powergood Quahficauon (PQ) block 66 contains a detection mechanism for sensing a minimum PWRGOOD disable pulse The detector will detect a PWRGOOD disable pulse independent of whether or not a clock is present When a PWRGOOD disable occurs, a power recycle signal is immediately generated and held
  • the PQ block contains a state machine that guarantees that a power recycle indication is held for at least 2 clock cycles This minimum duration of time is adequate to insure mat the power recycle can be processed in other design blocks, such as for example, in asserting a power-up reset
  • the signal powergood_ ⁇ nt is an asynchronous reset that forces the state machine back to state 00 when asserted
  • the Pad Clock and Self Test (PCST) block 68 provides conttol of the Pad_clk which is an output buffer to the external world
  • the PCST block will provide one of the following three configurable conditions Type 1 ) a clock whose frequency is constantly one-half that of the external oscillator, Type 2) a clock whose frequency is ' generally" one- half that of the external oscillator but is forced equal to a programmable fraction of this frequency when in power-save mode, or, Type 3) disabled low
  • the Pad_clk may be brought in and out of disabling into the previous modes without g tching similar to methods used in the CEB
  • the PCST has two non- standard operating modes which are the In-circuit emulator mode and the test mode Du ⁇ ng In-circuit emulator mode operation as determined by the Icemode signal being active, the Pad_clk's output is designed to be closely m-phase with the clock generated for the embedded CPU In test mode as determined by the Test signal being active the PCST is configured to allow
  • the clock branches and internal source clocks are selectably muxed out to Pad_clk.
  • the selection of which clock is driven out is controlled by programming of the lower nibble of configuration register four 62.
  • the Test_lvl_en signal is active logic level of Pad_clk is equal to the logic level of Test_hi_lowz.
  • the Clock Enable Block (CEB) 70 block contains the clock branch generators for each of the clocks coming out of the power management block driving internal sequential devices.
  • the clock enabling/disabling circuitry is guaranteed to be glitch-free. That is, clocks are disabled after a falling edge on the internal source clocks, are held low during disabling, and are re- enabled after falling edge of the source clock (enabling during the low part of the source clock), and will subsequently begin the first rise with the next rising transition of the internal source clock, without any logic-generated spurious glitches.
  • Special system-level considerations are taken into account for Idle mode assertion. Idle is configurable stoppage of the Clock going to the embedded CPU 34.
  • the main consideration is to not stop the Cpu_core_clk when the embedded CPU 34 is actively performing a bus cycle.
  • the process involved in stopping the embedded CPU 34 is to provide an Idlreq to system control logic and for the system control logic to send back an Idlack which is sampled by the CEB 70 to generate a glitch-free disable.
  • Idle is disabled by deasserting Idfreq and receiving back a deasserted Idlack by the system conttol logic.
  • the clock will be restarted glitch-free.
  • IDLE Mode The source clocks for the CEB 70 are of type 1, type 2, and a 2x frequency version of type 2. Most of the clocks are generated from one or the other of these source clocks, however, the Timer_clk and Pcmcia_clk may be configured to have either Type 1 or Type 2 clocks. (Global and Individual Peripheral Disable Mode).
  • the Power-Level Detect (PLD) 72 acts as an analog voltage-level detector interface with programmable override. It provides the digitally encoded voltage level as an output which is used for global configuration.
  • An analog enable, D3VEN from configuration register three 60 is available to turn on the DC-current sources of an external voltage-level detector and a read strobe.
  • CHK3V from configuration register three 60 is also available to sample the voltage-level detector input, Pup3V. After the detector input has been sampled, both the CHK3V and D3VEN can be deasserted. It is important to assert D3VEN before CHK3V and deassert in the reverse order so that a correct operational state of Pup3v is captured.
  • the default output of the PLD 72 after a hard reset is one, on port Three.
  • the analog interface functions may be bypassed, and thus, the output signal THREE may be driven under configuration conttol by the SETV input directly from configuration register three 60.
  • the power management system 30 controls the voltage sensing and setting for the I/Os.
  • the power management system 30 described has the capability to set the operating voltage configuration level through firmware and through voltage-level sensing.
  • the interface to an analog voltage sensing circuit is included in the power management block and is controlled by bits 4 and 6 of configuration register four 62.
  • Bit 4 enables the voltage detector. Since analog circuitry generally consumes DC cu ⁇ ent when active, the enable switch is used to switch the current on or off. The circuit is, therefore, only enabled when voltage detection is needed to reduce power consumption.
  • Bit 6 is used to latch and hold the level of the voltage detector. In this embodiment, the voltage detector needs to detect either a 3.3V or 5V supply level.
  • the output configuration level latched is either a Logic 1 or 0.
  • higher order A/Ds may be used if finer levels of voltage-level detection are needed.
  • the power configuration level is stored in configuration register four 62 bit 5. The level may be overridden by firmware.
  • This interface voltage detection scheme has been defined to discern voltages above and below a target detection trip point of for example, 4.0V. Thus, this particular application will have a different configuration level at 5.0V(+/-10 ) then at 3.3(+/-10%).
  • the Internal Source Clock Generation (ISCG) block 74 generates the internal source clocks. It contains a 7-bit synchronous counter with a synchronous load to a count of one and an asynchronous clear.
  • the block generates the type 2 and 2x frequency version of the type 2 internal source clocks.
  • the type 2 clock is generated by a feedback of the cpu_clk_z source clock output through a two-input mux driving (pre_cpu_clk) back into the D-input of the cpu_clk_z-generating flip flop which is sampled by a clock referenced to the external oscillator clock called osc_qualified (i.e., this is a divide-by-2 function); and in standard mode the 2x type 2 clock is essentially a buffered-and-muxed version of osc_qualified.
  • both the lx and 2x Type 2 clocks are created starting through the Synchronous counter to two separate divide-by-2 final clock generators.
  • the 2x clock will originate from YO of the counter (i.e., a 12 of osc_qualified) through the final divide-by-2 clock generator resulting in a divided-by-4 2x clock.
  • the lx clock will originate from Yl of the counter.
  • Yl of the counter is a divide-by-4 of osc_qualified, which is equal to a divide-by-2 of the "standard" cpu_clk.
  • the standard cpu_clk is the lx clock reference frequency.
  • Yl of the counter goes through the final divide-by-2 clock generator resulting in a divided-by-4 lx clock.
  • counter ports Yl and Y2 are used respectively, and so on up to divide-by-64.
  • the Power-Save Mode Change Detection (PSVMCD) block 76 is used to sample changes in the Power Save Mode control configuration registers, SVB[2:0] and PSVM.
  • Two banks of flip-flops sampled off of opposite edges of an internal source clock of type 2 are compared (i.e. clocks cpu_clk and cpu_clk_z). When there is a difference between the two, an intermediate indicator is asserted called equality_z. If power-save mode is asserted in either or both of the sampling banks, i.e. psvm_dl_5 or psvm_dl, then a psvm_change indicator is asserted.
  • load_l a synchronous pulse
  • osc_qualified an internally qualified reference to the external oscillator clock
  • the load_l pulse is generated by the PSVMCD 76 after the falling edge of the system clock and the load_l pulse is again deasserted prior to the rising edge of the next system clock.
  • the PSVMCD 76 is used to create and drive the load_l pulse into the ISCG at a specific time point in the period of the current system clock and provide synchronized power save mode conttol signals, i.e.

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  • Oscillators With Electromechanical Resonators (AREA)

Abstract

Cette invention se rapporte à un système de gestion de puissance, dans lequel sont utilisés une interface d'oscillateur, un circuit de recyclage de puissance, une horloge à réseau atténuateur et un auto-test, un circuit de validation d'horloge, un circuit de détection de niveau de puissance, un circuit générateur d'impulsion d'horloge source interne, ainsi qu'un circuit de détection de passage en mode économie de puissance. Ladite interface d'oscillateur comprend un circuit d'interface destiné à établir une interface avec un oscillateur externe utilisé comme source d'oscillation. Un filtre de stabilisation d'horloge masque les fréquences parasites des oscillations du quartz lors du démarrage du système de gestion de puissance après une validation d'une boucle de réaction. Un filtre de stabilisation d'horloge possède les circuits qui font en sorte que les oscillations débutent avec une transition montante après filtrage. Un circuit de dérivation valide le filtre de stabilisation d'horloge, lorsque l'oscillateur externe est un oscillateur à quartz et pour contourner le filtre de stabilisation d'horloge, lorsque l'oscillateur externe est un oscillateur en boîtier. Un circuit de masquage masque les oscillations provenant du reste du système de gestion de puissance. Ce circuit de masquage possède des circuits qui invalident le masquage de l'horloge après un flanc arrière des oscillations et qui initialisent la sauvegarde lors d'une transition montante des oscillations.
PCT/US1996/007571 1995-05-26 1996-05-23 Plan de gestion de puissance configurable WO1996037960A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96916586A EP0772911B1 (fr) 1995-05-26 1996-05-23 Interface oscillateur pour systeme de gestion de puissance
DE69629780T DE69629780T2 (de) 1995-05-26 1996-05-23 Oszillator zur verwendung in einer leistungssteuersystem

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Application Number Priority Date Filing Date Title
US08/451,206 1995-05-26
US08/451,206 US5805923A (en) 1995-05-26 1995-05-26 Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used

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WO1996037960A2 true WO1996037960A2 (fr) 1996-11-28
WO1996037960A3 WO1996037960A3 (fr) 1997-02-06

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KR100430768B1 (ko) 2004-05-10
KR970705238A (ko) 1997-09-06
KR20030097635A (ko) 2003-12-31
US5805923A (en) 1998-09-08
KR100430769B1 (ko) 2004-05-10
KR20030097636A (ko) 2003-12-31
KR20030097634A (ko) 2003-12-31
DE69629780D1 (de) 2003-10-09
DE69629780T2 (de) 2004-07-15
KR20030097637A (ko) 2003-12-31
US6016071A (en) 2000-01-18
EP0772911B1 (fr) 2003-09-03
US6397338B2 (en) 2002-05-28
US6367021B1 (en) 2002-04-02
US6021501A (en) 2000-02-01
WO1996037960A3 (fr) 1997-02-06
KR100399662B1 (ko) 2004-03-24
US5926641A (en) 1999-07-20
US20010007113A1 (en) 2001-07-05
US5983014A (en) 1999-11-09
EP0772911A1 (fr) 1997-05-14

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