WO1996029731A1 - Dispositif a semi-conducteur et son procede de fabrication - Google Patents

Dispositif a semi-conducteur et son procede de fabrication Download PDF

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Publication number
WO1996029731A1
WO1996029731A1 PCT/JP1995/000482 JP9500482W WO9629731A1 WO 1996029731 A1 WO1996029731 A1 WO 1996029731A1 JP 9500482 W JP9500482 W JP 9500482W WO 9629731 A1 WO9629731 A1 WO 9629731A1
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WIPO (PCT)
Prior art keywords
oxidation
region
element isolation
semiconductor device
film
Prior art date
Application number
PCT/JP1995/000482
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English (en)
Japanese (ja)
Inventor
Hiroyuki Ohta
Hideo Miura
Shuji Ikeda
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/000482 priority Critical patent/WO1996029731A1/fr
Priority to TW084109622A priority patent/TW296463B/zh
Publication of WO1996029731A1 publication Critical patent/WO1996029731A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device and a method of manufacturing the same capable of obtaining good electrical characteristics of an element when performing high-density integration.
  • a LOCOS method (Local Oxidation of Silicon) or an improved method thereof has been used as an element isolation method of a semiconductor device.
  • a mask is formed in a portion to be an active region in a silicon wafer, and then thermally oxidized in a high-temperature oxidizing atmosphere to form a silicon in a portion other than an active region of a transistor called an element isolation region (field region). It forms a con oxide film.
  • a silicon oxide film called a Pad oxide film and a silicon nitride film called a mask are stacked on the surface of a silicon wafer, and after etching the silicon nitride film into a predetermined pattern, it is about 1000 * C.
  • the silicon wafer under the mask Since the silicon wafer under the mask is eroded by the oxide film due to the growth of the pars beak, the silicon wafer under the mask is removed by etching. The silicon oxide film is also shaved by that amount, and a predetermined oxide film thickness may not be obtained. Therefore, attempts have been made to minimize parse beaks.
  • the maximum separation from the interface between the silicon wafer 1 and the silicon oxide film 3 in the element isolation region to the surface of the silicon wafer 1 in the active region is defined.
  • Another important issue related to the above is prevention of crystal defects caused by stress generated during thermal oxidation.
  • the compressive stress generated at the lower end of the mask not only suppresses the growth of the parse beak, but also causes a problem of generating crystal defects (dislocations) in the silicon wafer. Since the lower end of the mask is a dissimilar material interface, which is a unique area, it is theoretically a place where stress diverges to infinity. At high temperatures near lOOOOt, where thermal oxidation occurs, the strength of the silicon wafer is reduced and dislocations are easily generated.
  • the machinability of the mask is excessively increased to suppress the purse beak. If an excessive pressure box stress is generated at the lower end of the mask, dislocations will be generated from this specific region. In other words, if the mask width decreases due to high integration, it is necessary to increase the pressure box stress at the lower end of the mask to suppress the purse beak, but this increase in the pressure stress leads to the generation of dislocations. There's a problem.
  • the bird's beak at the lower end of the mask is suppressed by using a highly rigid mask, and a certain degree of stress relaxation effect is provided by the silicon oxide film at the lower end of the mask. Is prevented.
  • the balance is made so as to achieve both a certain suppression of the parse beak and prevention of the occurrence of dislocation.
  • An object of the present invention is to provide a semiconductor device having good electrical characteristics without dislocations occurring in an active region when a silicon oxide film for element isolation is formed, even when a device has a high converging edge. It is to realize the manufacturing method. Further, another object of the present invention is to ensure a sufficient oxide film thickness for element isolation in a field region after removal of an oxide film under a mask even when high integration of the device is intended. An object of the present invention is to realize a semiconductor device and a method of manufacturing the same.
  • an oxidation-resistant region is formed by a silicon nitride film so as to cover a portion to be an active region on one surface of a semiconductor substrate, and the film is etched into a predetermined pattern.
  • an element isolation region is formed by thermal oxidation.
  • an oxidation resistant region is formed by a silicon nitride film.
  • the second oxidation-resistant film is a silicon nitride film or a silicon film.
  • an oxidation-resistant region is formed by a silicon nitride film so as to seed a portion to be an active region on one side of the semiconductor substrate, and the film is etched in a predetermined pattern.
  • a second oxidation-resistant film is formed so as to cover a portion to be an active region and a portion to be an element isolation region from above, and then an element engraving region is formed by thermal oxidation.
  • an oxidation-resistant region is formed by forming an oxidation-resistant film on one side of a semiconductor substrate, and then a thermal oxidation method is used in a method of manufacturing a semiconductor device in which an element engraving castle is formed by a thermal oxidation method.
  • a step of 0.01 ⁇ m or more was provided at the boundary between the oxidation-resistant region and a portion to be an element engraving region other than the oxidation-resistant region, so that the oxidation-resistant region was increased.
  • a corner formed between the step and the surface of the element isolation region of the semiconductor substrate is rounded or the angle of the corner is larger than 90 degrees.
  • a step of 0.01 m or more is provided at the boundary between the oxidation-resistant region and a portion to be an element isolation region other than the oxidation-resistant region. To do.
  • an oxide film for element isolation formed by thermal oxidation is subjected to CMP (Chemical Mechanical Positive Ising). Part of the semiconductor substrate is exposed by mechanical polishing.
  • the method includes the steps of: forming a silicon oxide film in contact with an element isolation film formed by thermal oxidation; The semiconductor substrate is partially exposed by the method.
  • a number of oxidation-resistant regions are formed on the semiconductor chip, and the film on the oxidation-resistant region depends on the width of the oxidation-resistant region. Is changed in several ways.
  • a large number of oxidation-resistant regions are formed on the semiconductor chip,
  • the thickness of the silicon oxide film on the oxidation-resistant region is changed between the portion of the oxidation-resistant region larger than the width and the portion of the oxidation-resistant region less than the predetermined width, and the thickness of the silicon oxide film on the oxidation-resistant region less than the predetermined width is changed.
  • the thickness of the silicon oxide film is made smaller than the thickness of the silicon oxide film on the oxidation-resistant region having a predetermined width or more.
  • a number of oxidation-resistant regions are formed on the semiconductor chip, and a portion of the oxidation-resistant region having a width equal to or larger than a predetermined width and a predetermined width are not formed. At least part of the silicon nitride film on the oxidation-resistant region having a width less than a predetermined width is directly in contact with the semiconductor substrate in the oxidation-resistant region.
  • the predetermined width is ⁇ .
  • At least a plurality of element isolation regions are formed around the memory cell portion and the peripheral circuit portion, and around the memory cell portion and the peripheral circuit portion.
  • the memory cells are at the ends of the element isolation regions having different stress values.
  • the stress value at the end of the element isolation region existing around the part should be equal to or greater than the stress value at the end of the element isolation region existing around the peripheral circuit part.
  • a plurality of active regions surrounded by element isolation regions are formed on one semiconductor chip, and at least two of the plurality of active regions are narrow in a semiconductor device having different widths from each other.
  • the stress value at the edge of the element isolation region around the active region may be larger than the stress value at the edge of the element isolation region around the wider active region.
  • a plurality of element isolation regions are formed on one semiconductor chip, and at least two of the plurality of element isolation regions have different stress values at the ends of the element isolation regions.
  • the stress value at the end of the element isolation region around the active region radiation of 1 am or more is equal to or greater than the stress value at the end of the element isolation region near the active region width of less than 1 ⁇ m. I will do it.
  • the shape of the element isolation region around the active region on one semiconductor chip is at least two or more.
  • a device in which a number of semiconductor elements are formed near the surface of a semiconductor substrate is called a semiconductor chip, and a device in which this semiconductor chip is packaged is called a semiconductor device.
  • the element and the chip are the semiconductor element and the semiconductor chip, respectively.
  • the high-temperature thermal oxidation refers to a processing method for oxidizing silicon by applying heat, such as a wet oxidation method and a dry oxidation method.
  • a mask is a single film or a plurality of films having an anti-oxidation function and formed so as to cover an active region.
  • the semiconductor substrate is a semiconductor wafer such as a silicon wafer, a gallium arsenide wafer, and a germanium wafer.
  • the element is each component before configuring a circuit such as a transistor, a resistor, and a capacitor.
  • the end of the element isolation region refers to a region from the lower end of the mask to a point where the thickness of the oxide film for element isolation does not increase.
  • the present invention by forming another silicon nitride film on the silicon nitride film mask, it is possible to reduce the concentration of stress generated at the edge of the silicon nitride film. That is, if only a silicon nitride film mask is used, a singular field is formed at the edge of the mask, and a large stress concentration that theoretically diverges to infinity occurs in the singular field, and crystal defects in the silicon wafer are generated. It may cause the occurrence of.
  • the mask width is reduced due to the high integration, it is necessary to increase the compressive stress at the mask edge to suppress the purse beak.
  • the present invention since stress is not excessively concentrated at one point at the mask edge, crystal box defects are prevented from occurring, and the pressure box stress necessary for suppressing the beak is reduced in the vicinity of the mask edge of the silicon nitride film. Can be generated at the same time. That is, according to the present invention, even when the device is highly integrated, a dislocation does not occur when the device isolation silicon oxide film is formed, and a semiconductor device having good electric characteristics can be produced. .
  • the active region is made higher than the element isolation region before oxidation. Keep it. Since this height difference is maintained to some extent even after element isolation oxidation, the active height can be increased even after element isolation oxidation. For this reason, even if further integration of the device is attempted, after removing the oxide film under the mask, the device isolation region should be sufficiently isolated. Since a sufficient oxide film thickness can be ensured, good element isolation characteristics can be obtained.
  • FIG. 1 is a sectional view of an embodiment of the first embodiment.
  • FIG. 2 is a cross-sectional view for explaining a manufacturing process of the first embodiment.
  • FIG. 3 is a cross-sectional view showing the relationship between the size of the step and the shear stress.
  • FIG. 4 is a cross-sectional view when a corner at the bottom of the step is rounded.
  • FIG. 5 is a cross-sectional view of the first embodiment when the shape of the step is changed.
  • FIG. 6 is a cross-sectional view showing the relationship between the angle of the step bottom and the shear stress.
  • FIG. 7 is a cross-sectional view for explaining a manufacturing process of the first embodiment.
  • FIG. 8 is a cross-sectional view for explaining a manufacturing process of the first embodiment.
  • FIG. 9 is a cross-sectional view for explaining a manufacturing process of the first embodiment.
  • FIG. 10 is a diagram defining the active height in the present specification.
  • FIG. 11 is a sectional view in which an active region is exposed using the CMP method of the first embodiment.
  • FIG. 12 is a flowchart for explaining the manufacturing process of the first embodiment.
  • FIG. 13 is a sectional view of the second embodiment.
  • FIG. 14 is a sectional view of the third embodiment.
  • FIG. 15 is a sectional view of the fourth embodiment.
  • FIG. 16 is a sectional view of the fifth embodiment.
  • FIG. 17 is a sectional view of the sixth embodiment.
  • FIG. 18 is a sectional view of the sixth embodiment when there is no step.
  • FIG. 19 is a cross-sectional view in the case where the silicon oxide film of the sixth embodiment is not formed.
  • FIG. 20 is a sectional view of the seventh embodiment.
  • FIG. 21 is a cross-sectional view in the case where the silicon oxide film of the seventh embodiment is not formed.
  • FIG. 22 is a cross-sectional view when the silicon film of the seventh embodiment is used.
  • FIG. 23 is a cross-sectional view when the silicon film of the seventh embodiment is used.
  • FIG. 24 is a cross-sectional view when a silicon film is used for the mask of the seventh embodiment.
  • FIG. 25 is a sectional view of the eighth embodiment.
  • FIG. 26 is a sectional view used for explaining the eighth embodiment.
  • FIG. 27 is a cross-sectional view used for explaining the eighth embodiment.
  • FIG. 28 is a sectional view of the eighth embodiment in which the silicon oxide film is not formed.
  • FIG. 29 is a sectional view of the ninth embodiment.
  • FIG. 30 is a cross-sectional view for explaining a manufacturing process in the ninth embodiment.
  • FIG. 31 is a cross-sectional view for explaining the manufacturing process of the ninth embodiment.
  • FIG. 32 is a cross-sectional view for explaining the manufacturing process of the ninth embodiment.
  • FIG. 33 is a sectional view of the ninth embodiment in which the silicon oxide film is not formed.
  • FIG. 34 is a sectional perspective view of the tenth embodiment.
  • FIG. 35 is a diagram showing a relationship between a mask width and dislocations.
  • FIG. 36 is a sectional perspective view of one mode of the tenth embodiment.
  • FIG. 37 is a sectional perspective view of one mode of the tenth embodiment.
  • FIG. 1 shows a sectional structure of an element isolation region immediately before thermal oxidation for forming an element isolation silicon oxide film 3.
  • This cross-sectional structure is such that a silicon oxide film 4 and a first silicon nitride film 5 are laminated only on a portion that will become an active region after thermal oxidation on a silicon wafer 1 having a step 2, and furthermore, a silicon wafer 1 and a first silicon
  • the second silicon nitride film 6 is deposited on the entire surface of the silicon nitride film 5 and on the portion of the silicon oxide film 4 not facing the silicon wafer 1 and the first silicon nitride film 5. .
  • the portion 9 is the mask, that is, the first silicon nitride film 5 and the second silicon nitride film 6 on the silicon wafer 1 in the active region.
  • This cross-sectional structure is formed by the following method.
  • a silicon oxide film 4 having a thickness of about 5 to 30 ntn is formed on a single-crystal silicon wafer 1 having a characteristic of, for example, p-type 10 ⁇ ⁇ cm for stress relaxation by thermal oxidation. Further, a first silicon nitride film 5 is deposited thereon to a thickness of 50 to 200 ⁇ to form a mask.
  • the silicon oxide film 4 and the first silicon nitride film 5 are formed by CVD (Chemical Vapor Deposition), preferably in a depressurized atmosphere in a range of 700 to 8001 :.
  • the first silicon nitride film 5 and the silicon oxide film 5 are formed only near the active region.
  • the width of the first silicon nitride film 5 is desirably wider than the width of the silicon oxide film 4.
  • silicon wafer 1 is slightly etched.
  • a step 2 is provided on the silicon wafer 1 at the lower end of the first silicon nitride film 5. If the step 2 is too small, the effect of reducing the stress is small, and the active height cannot be large. As shown in Fig. 3, dislocations occur in the active region during thermal oxidation below ⁇ ⁇ ⁇ ⁇ . Conversely, if it is too large, large ridges of oxide film will be formed at both ends of the mask. Therefore, it is desirable that this step 2 be in the range of about 10 to 100 nn.
  • the bottom of the step 2 be rounded as shown by an arrow in the figure as shown in FIG. 4 by adding an isotropic etching technique or the like.
  • By rounding the bottom of the step 2 it is possible to further reduce the stress at the lower end of the mask 9 as shown by the black dots in FIG.
  • the silicon oxide film 4 is slightly dissolved by immersing it in an aqueous solution containing hydrofluoric acid, and as shown in FIG.
  • the cavity 7 is formed by retreating the oxide film 4.
  • the amount of retreat is preferably about 100 to 100 nra.
  • the second silicon nitride film 6 is deposited by the decompression CVD method or the plasma CVD method.
  • a second silicon nitride film may be deposited by another manufacturing method. At this time, the cavity 7 is completely filled with the second silicon nitride film 6.
  • the second silicon nitride film has a high nitrogen content and is hard. Further, it is desirable to form the film at a high temperature of 780 or more because a dense film is obtained.
  • the silicon ⁇ -c 1 There may be an oxide film of about 5 nn or less on natural oxide film
  • the second silicon nitride film 6 is removed by a wet etching method or the like before the thermal oxidation. It is good to keep it.
  • the silicon nitride film 6 ′, the first silicon nitride film 5, and the silicon oxide film 4 are removed by wet etching or dry etching using a solution containing phosphoric acid. Then, the active region 8 is exposed on the surface to obtain the structure shown in FIG.
  • a silicon chamber siliconized film is formed by using a CMP (Chemical Mechanical Polishing) method.
  • CMP Chemical Mechanical Polishing
  • the first silicon nitride film 5 and the silicon oxide film 4 may be removed to expose the active region 8 on the surface.
  • the surface of the active region 8 and the surface of the element isolation oxide film 3 can be at the same height as shown in FIG.
  • Fig. 1 The structure shown in Fig. 1 was thermally oxidized, followed by CVD and other methods. Alternatively, the active region 8 may be exposed on the surface by CMP.
  • FIG. 12 shows a summary of the above steps.
  • a PN junction is formed by ion implantation, and then an electrode is formed on the active region. Then, connect the glue so as to be in contact with the electrode. After that, it is cut into individual chips to form signal derivation sections and packaged to form semiconductor devices.
  • the steps up to the semiconductor device g are the same, so the description is omitted.
  • the second silicon nitride film 6 is uniformly deposited on the silicon wafer 1 and the first silicon nitride film 5 by CVD or the like, and furthermore, the silicon wafer 1 and the first silicon nitride film 5 are formed. It is deposited so as to completely bury the cavity 7 at the boundary of the con-nitride film 5. For this reason, during thermal oxidation, a compressive stress that is not excessively concentrated at a point where crystal defects are generated but that is necessary to suppress parse beak is applied to the lower end of the first silicon nitride film 5. It can be generated nearby. Therefore, even when the element is highly integrated, no dislocation occurs when the element isolation silicon oxide film 3 is formed, and a semiconductor element having good electric characteristics can be produced.
  • the second silicon nitride film 6 is in contact with the silicon wafer 1 at the lower end of the mask 9 without the silicon oxide film 4 interposed therebetween, a purse beak grows. Hateful. Therefore, an oxide film is unlikely to grow on the silicon wafer 1 under the silicon oxide film 4, and a sufficient active height can be secured after the mask 9 is removed.
  • the active height can be increased by forming the step 2, so that the oxide film slightly grows under the mask 9. In this case, good element isolation characteristics can be obtained. Further, according to the present embodiment, by forming the step 2, the stress generated at the mask end can be reduced, and the occurrence of dislocation during thermal oxidation can be prevented.
  • the silicon wafer 1 and the first silicon nitride film 5 of the mask 9 come into direct contact with the second silicon nitride film 6.
  • This structure is effective in suppressing the growth of parsbeaks.
  • the silicon wafer 1 and the first silicon nitride film 5 are also in direct contact with each other via the silicon oxide film 4 at the mask edge as shown in Fig. 13. Thermal oxidation may be performed using an unstructured structure.
  • the feature of the present embodiment is that the step of immersion in an aqueous solution containing hydrofluoric acid can be omitted because the cavity 7 need not be formed.
  • the feature of the third embodiment is that the silicon wafer 1 and the first silicon nitride film 5 are in direct contact.
  • the parse beak is less likely to grow as compared with the first embodiment. Therefore, the oxide film is less likely to grow on the silicon wafer 1 under the first silicon nitride film 5, and a sufficient active height can be secured after removing the mask 9.
  • the active height can be increased by forming the step 2, so that the Good element isolation characteristics can be obtained even when an oxide film is grown under the mask 9.
  • FIG. 15 shows a second embodiment in which the second silicon nitride film 6 of the first embodiment is replaced with a silicon film 10.
  • the silicon film has a faster oxidation rate than the silicon nitride film during thermal oxidation, but unlike a silicon oxide film, it cannot diffuse an oxidant freely, so it is used as a weak oxidation-resistant film.
  • the lower end of the first silicon nitride film 5 is surrounded by the second silicon nitride film 6, whereas in the present embodiment, the lower end is surrounded by the relatively soft silicon film 10.
  • the silicon film 10 is preferably formed by a decompression CVD method or a plasma CVD method.
  • FIG. 16 shows the second embodiment in which the second silicon nitride film 6 of the third embodiment is replaced with a silicon film 10. There is no silicon oxide film 4 under the first silicon nitride film 5, and the first silicon nitride film 5 and the silicon wafer 1 are in direct contact with each other. 0 is deposited. In this embodiment, for the same reason as in the third and fourth embodiments, the magnitude of stress concentration at the lower end of the mask 9 is small, and dislocations are less likely to occur.
  • a part of the mask 9 is made of a silicon film 11.
  • a single-crystal silicon wafer having a silicon oxide film 4 on its surface is used.
  • a silicon film 11 is formed on 1 by using a CVD method or the like. Other steps are formed as shown in FIG. 17 in the same manner as in the first embodiment.
  • FIG. 19 shows a case where the silicon oxide film 4 is not provided, and a part of the mask 9 is a silicon film 11.
  • the silicon film 10 even when there is no step 2, or when the silicon film 10 is used in place of the second silicon nitride film 6, it has a function of suppressing a beak.
  • the presence of the silicon film 6 or the silicon film 10 has an effect of alleviating the stress concentration at the lower end of the mask 9.
  • the seventh embodiment will be described with reference to FIGS.
  • thermal oxidation is performed with the second silicon nitride film 6 covering only the first silicon nitride film 5, the silicon oxide film 4, and the step 2, and the silicon wafer 1 in the element isolation region is
  • the silicon oxide film 3 for element isolation is formed without being seeded by the second silicon nitride film 6.
  • the main points of the manufacturing method of this embodiment are as follows. First, a shape similar to that before the thermal oxidation of the first embodiment is obtained. After that, only the second silicon nitride film 6 covering the element isolation region is removed by a wet etching method or the like to expose the silicon wafer 1 in the element isolation region. Thereafter, thermal oxidation is performed by a wet oxidation method, and a silicon for element isolation of about 300 to 450 nm is applied to the element isolation region. An oxide film 3 is formed.
  • FIGS. 22 and 23 show configurations in which the second silicon nitride film 6 in FIGS. 20 and 21 is replaced with a silicon film 10.
  • a part of the mask 9 may be composed of the silicon film 11.
  • the same effect can be obtained by using a structure in which the silicon oxide film 4 is not provided and the silicon wafer 1 and the silicon film 11 are in contact with each other.
  • the eighth embodiment will be described with reference to FIGS. 25 to 28.
  • the second silicon nitride film 6 on the element isolation region and on the side surface of the mask 9 is gradually oxidized and integrated with the silicon oxide film 3 for element isolation.
  • the second silicon nitride film 6 is thick and remains even during thermal oxidation, and itself has a function of suppressing a parse beak. Therefore, if the oxidizing agent does not follow a long diffusion path from the bottom of step 2 to the top of step 2 during thermal oxidation, the silicon wafer 1 under the first silicon nitride film 5, that is, the active region cannot be oxidized. Therefore, the parse beak is difficult to extend under the mask 9.
  • the silicon nitride film 6 is not completely oxidized after the thermal oxidation, the silicon nitride film 6 ′ remains as shown in FIG. 26, and if the purge beak does not extend, the silicon nitride film 6 ′ After removing the first silicon nitride film 5 and the silicon oxide film 4, the silicon oxide film 3 for element isolation and the side surface of the active region are removed. There is a gap between them, and good element isolation characteristics cannot be obtained. Therefore, when the structure of FIG. 25 is thermally oxidized, it is necessary to control the thickness of the second silicon nitride film 6 so that the parse beak reaches the bottom of the step 2 just as shown in FIG.
  • the second silicon nitride film 5 It is similarly effective when silicon film 11 is used instead of film 6.
  • the ninth embodiment will be described with reference to FIGS. 29 to 33.
  • FIG. 29 shows a silicon film 11 deposited on the silicon oxide film 4, and the silicon wafer 1 in the element isolation region is exposed to ⁇ .
  • the first silicon nitride film 5 and the second silicon nitride film 6 are removed by etching as shown in FIG. At this time, since the silicon film 11 is harder than the silicon nitride film and serves as an etching stopper, it does not damage the silicon wafer 1 in the active region and has good electrical characteristics. Can be obtained.
  • a silicon oxide film 12 is deposited by, for example, a CVD method or a coating method.
  • a part or all of the silicon film 11, the silicon oxide film 4, and the silicon oxide film 3 for element isolation are removed by the CMP method, and the active region 8 is removed. Is flattened together with SS.
  • the thin film deposited on the flattening can be uniformly deposited, so that the reliability of the semiconductor device can be improved.
  • a structure in which the silicon oxide film 4 is not provided as shown in FIG. 33 or a silicon film 11 is used instead of the second silicon nitride film 6 although not shown. Similar effects can be obtained.
  • FIG. 34 is a partial sectional perspective view of a semiconductor chip 13 before thermal oxidation for forming a silicon oxide film 3 for element isolation. This embodiment is an embodiment in the case where the structure before thermal oxidation is changed depending on the width dimension of the active region in the semiconductor chip 13.
  • the stress generated at the lower end portion of the mask 9 is smaller than when the width of the mask 9 is wide. This difference in stress is significant during thermal oxidation, especially in the early stages of oxidation.
  • the wafer 1 is in contact with the first silicon nitride film 5.
  • the silicon is formed to prevent the occurrence of the dislocation.
  • the wafer 1 and the mask 9 are connected via the silicon oxide film 4. Since the silicon oxide film 4 is softer than the silicon wafer 1 and the mask 9 and exhibits a viscous behavior at a high temperature, the silicon oxide film 4 is sandwiched between the silicon wafer 1 and the mask 9. This has the effect of relaxing the stress at the end of the mask 9.
  • the stress at the end of the element isolation region of the peripheral circuit section 15 is larger than the stress at the end of the element isolation region of the wide portion of the mask 9. To become.
  • FIG. 35 shows a state where the silicon wafer 1 and the first silicon nitride film 5 are in contact with each other.
  • 4 is a graph showing the occurrence of dislocations when thermal oxidation at about 1 000 is performed.
  • the width of the mask 9 is 1 ⁇ or less, dislocations are observed in a state where the silicon wafer 1 and the first silicon nitride film 5 are in contact at the lower end of the mask 9. Therefore, when the width of the mask 9 is 1 ⁇ or less, it is desirable that the silicon wafer 1 and the first silicon nitride film 5 be in contact with at least the lower end of the mask 9.
  • the case where the width of the mask 9 is narrow is a case where the width is 1 ⁇ m or less.
  • the silicon wafer 1 and the first silicon nitride film 5 are connected via the silicon oxide film 4, a slight elongation of the parse beak is observed, but since the active width is wide, It is not a problem to maintain good electrical characteristics. That is, regardless of the width of the mask 9, a semiconductor device having good element isolation characteristics and electrical characteristics can be obtained ( note that the width of the mask 9 is narrow as in the memory cell portion 14).
  • the use of the method of forming the second silicon nitride film 6 as described in each of the above embodiments eliminates the possibility of dislocations.
  • FIG. 36 shows a case in which the element isolation structure is manufactured by the L0C0S method by changing the thickness of the silicon oxide film 4 for stress relaxation depending on the width of the active region in the semiconductor device 13. This is the case shown.
  • FIG. 36 is a partial cross-sectional perspective view of the semiconductor device immediately before thermal oxidation for forming the element isolation silicon oxide film 3.
  • the width of the mask 9 is narrow, as in the memory cell section 14, the stress generated at the mask edge is smaller than when the width of the mask 9 is wide, so that the risk of dislocation generation is reduced.
  • the thickness of the lower silicon oxide film 4 is It is thinner to suppress the growth of the pearl beak. Desirably, the thickness of the silicon oxide film 4 is changed when the mask width is 1 ⁇ m or less. According to the above method, a semiconductor device having good element isolation characteristics and electrical characteristics can be obtained regardless of the width of the mask 9. As shown in FIG.
  • the mask 9 and the silicon transistor 1 are in contact with each other over the entire surface, and when the mask width is large, the mask 9 and the silicon transistor 1 form the silicon oxide film 4.
  • the same effect can be obtained by thermally oxidizing the structure that is in contact with the structure.
  • the second silicon nitride film 6 may be replaced with the silicon film 10 as in the above-described embodiments, or the step 2 may not be provided. Further, a structure in which a part of the mask 9 is composed of the silicon film 11 may be used.
  • a semiconductor device having a plurality of types of element isolation regions after thermal oxidation is manufactured. Will be able to do so.
  • the following effects can be realized.
  • the end of the first silicon nitride film 5 becomes the end of the silicon nitride film. Since it is not a part, it does not become a stress singular field and the stress concentration field does not diverge. That is, even when the strength of the silicon wafer 1 is reduced in a high-temperature atmosphere during thermal oxidation, dislocations are prevented from being generated, and a semiconductor element having good electrical characteristics can be obtained.
  • the width of the mask 9 is reduced due to the high integration, it is necessary to increase the compressive stress at the lower end of the mask 9 to suppress the bird's beak.
  • one point at the lower end of the mask 9 is required. Since the stress is not excessively concentrated on the surface, it is possible to prevent the generation of crystal defects and generate the compressive stress necessary for suppressing the beak in the vicinity of the lower end of the first silicon nitride film 5. That is, the element Even when high integration is achieved, dislocations do not occur on the silicon layer 1 in the active region when the silicon oxide film 3 for element isolation is formed, and a semiconductor element having good electrical characteristics can be produced. be able to.
  • the step 2 is formed at the end of the first silicon nitride film 5 to achieve element isolation.
  • a large active height can be maintained after oxidation.
  • the integration of the element is further improved.
  • a sufficient oxide film thickness for element isolation can be secured in the element isolation region, so that a good element is obtained. Separation characteristics can be obtained.
  • the stress concentration at the end of the mask 9 can be dispersed and reduced. Therefore, even when the integration of elements is further increased, good element isolation characteristics can be obtained without generating dislocations at the end of the mask 9.
  • the present invention is effective not only for the memory cell section but also for the register and the memory section of the CPU section.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

L'invention concerne la formation d'une couche mince de silicium ou de nitrure de silicium sur un substrat de silicium et la formation d'une autre couche mince de nitrure de silicium sur le substrat. La couche mince de silicium et la couche mince de nitrure de silicium sont oxidées à chaud. Des gradins sont prévus aux extrémités du masque. Grâce à la présence de la couche mince de silicium ou de nitrure de silicium, les contraintes excessives ne se concentrent pas en un seul point des extrémités du masque, ce qui évite des défauts. Grâce aux gradins, l'épaisseur de la couche mince d'oxide est préservée dans la partie isolante de l'élément même lorsqu'une couche mince d'oxyde apparait sous le masque pendant l'oxydation à chaud.
PCT/JP1995/000482 1995-03-17 1995-03-17 Dispositif a semi-conducteur et son procede de fabrication WO1996029731A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP1995/000482 WO1996029731A1 (fr) 1995-03-17 1995-03-17 Dispositif a semi-conducteur et son procede de fabrication
TW084109622A TW296463B (fr) 1995-03-17 1995-09-14

Applications Claiming Priority (1)

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PCT/JP1995/000482 WO1996029731A1 (fr) 1995-03-17 1995-03-17 Dispositif a semi-conducteur et son procede de fabrication

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WO1996029731A1 true WO1996029731A1 (fr) 1996-09-26

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196514A (ja) * 2005-01-11 2006-07-27 Nec Electronics Corp 半導体装置及びその製造方法
JP2006310350A (ja) * 2005-04-26 2006-11-09 Ishikawajima Harima Heavy Ind Co Ltd 素子間分離領域の形成方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020529A (ja) * 1983-07-13 1985-02-01 Matsushita Electronics Corp 半導体装置の製造方法
JPS6266645A (ja) * 1985-09-18 1987-03-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPS62101034A (ja) * 1985-10-28 1987-05-11 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体基板表面の突起を除去する方法
JPS63271956A (ja) * 1987-04-28 1988-11-09 Seiko Instr & Electronics Ltd 半導体装置の素子分離形成方法
JPS6467958A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Semiconductor storage device and manufacture thereof
JPH01204443A (ja) * 1988-02-09 1989-08-17 Toshiba Corp 半導体装置の素子分離方法
JPH01253932A (ja) * 1988-04-01 1989-10-11 Mitsubishi Electric Corp 半導体装置の製造方法
JPH05218192A (ja) * 1992-02-05 1993-08-27 Sharp Corp 半導体素子の製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020529A (ja) * 1983-07-13 1985-02-01 Matsushita Electronics Corp 半導体装置の製造方法
JPS6266645A (ja) * 1985-09-18 1987-03-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPS62101034A (ja) * 1985-10-28 1987-05-11 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体基板表面の突起を除去する方法
JPS63271956A (ja) * 1987-04-28 1988-11-09 Seiko Instr & Electronics Ltd 半導体装置の素子分離形成方法
JPS6467958A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Semiconductor storage device and manufacture thereof
JPH01204443A (ja) * 1988-02-09 1989-08-17 Toshiba Corp 半導体装置の素子分離方法
JPH01253932A (ja) * 1988-04-01 1989-10-11 Mitsubishi Electric Corp 半導体装置の製造方法
JPH05218192A (ja) * 1992-02-05 1993-08-27 Sharp Corp 半導体素子の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196514A (ja) * 2005-01-11 2006-07-27 Nec Electronics Corp 半導体装置及びその製造方法
JP2006310350A (ja) * 2005-04-26 2006-11-09 Ishikawajima Harima Heavy Ind Co Ltd 素子間分離領域の形成方法

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