WO1996017382A1 - Lothöcker für die flip-chip-montage und verfahren zu dessen herstellung - Google Patents
Lothöcker für die flip-chip-montage und verfahren zu dessen herstellung Download PDFInfo
- Publication number
- WO1996017382A1 WO1996017382A1 PCT/DE1995/001590 DE9501590W WO9617382A1 WO 1996017382 A1 WO1996017382 A1 WO 1996017382A1 DE 9501590 W DE9501590 W DE 9501590W WO 9617382 A1 WO9617382 A1 WO 9617382A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- solder bump
- gold
- core
- solder
- diffusion barrier
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims description 36
- 239000010931 gold Substances 0.000 claims abstract description 58
- 229910052737 gold Inorganic materials 0.000 claims abstract description 58
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 57
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 44
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 22
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000010899 nucleation Methods 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 29
- 238000001465 metallisation Methods 0.000 claims description 9
- 238000007654 immersion Methods 0.000 claims description 7
- 230000035784 germination Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000009736 wetting Methods 0.000 claims description 3
- 229910000510 noble metal Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004140 cleaning Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229910000765 intermetallic Inorganic materials 0.000 abstract description 2
- 238000002406 microsurgery Methods 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 abstract 1
- 239000002667 nucleating agent Substances 0.000 abstract 1
- 230000006911 nucleation Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 44
- 239000011162 core material Substances 0.000 description 22
- 238000005476 soldering Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000002604 ultrasonography Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/13144—Gold [Au] as principal constituent
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- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/02—Soldered or welded connections
Definitions
- solder bumps made of a homogeneous alloy material, e.g. B. Pb / Sn 95/5 or eutectic composition.
- the bump metallization is applied, for example, by means of galvanic deposition processes or by vapor deposition.
- galvanic deposition processes or by vapor deposition.
- the invention is important for those areas of application in which the materials used for the substrates and / or pads (English: pads) allow soft and electrically highly conductive metal bumps, in particular gold bumps, and corresponding solders for the production of connections , especially flip-chip connections.
- pads allow soft and electrically highly conductive metal bumps, in particular gold bumps, and corresponding solders for the production of connections , especially flip-chip connections.
- Gold bumps are often used together with solder containing tin to make connections. Problems can arise due to intermetallic phases, which form extremely quickly with this material pairing.
- the strong reaction of the solder, ie the tin in the solder, with the gold leads to intermetallic compounds such as AuSn, AuSn 2 and AuSn 4 , which are brittle and have an adverse effect on the mechanical stability but also the electrical and thermal conductivity of the solder joints or -Have connections. Pores can even arise due to different diffusion coefficients (so-called Kirkendal effect), which are detrimental to the reliability of the connection.
- a soft-solderable layer can also be applied by dipping for special purposes. Tin or tin alloy or lead solder layers have proven to be favorable for this. While only gold compression or ultrasound connection techniques can be used for gold bumps without a nickel layer, gold bumps with a nickel layer can also be used for flip-chip soldering.
- a disadvantage of the known method is the cleaning step for the galvanic gold bumps, which is necessary for a good primer before the nickel plating. This Cleaning step slows down the production of the diffusion barrier layer on the gold bumps and reduces the maximum throughput in production.
- the object of the invention is to provide a solder bump with particularly good adhesion properties and to specify a method for its production which can be carried out simply, quickly and inexpensively.
- a solder bump according to the invention consists of a core to which at least one layer is applied.
- the solder bump core contains a high proportion of a metal which is soft and has good electrical conductivity and also enables the production of very small solder bump cores.
- a small proportion of a seeding material is contained in a solder bump core, which ensures good adhesion of a diffusion barrier layer on a solder bump core.
- a solder bump according to the invention consists of a core with a high proportion of gold, on which a layer is applied, which acts as a diffusion barrier layer between the gold in the core material of the solder bump and the solder material that comes into contact with the solder bump according to the invention.
- the core material of a solder bump according to the invention is not made of 100% gold, such as. B. in the known galvanic gold bumps, but also contains a small proportion of a material that serves as a seeding material for the material of the diffusion barrier layer subsequently to be applied to the core material of a solder bump.
- This seeding material contained in the core material brings about a good and reliable adhesion of the diffusion barrier layer to the core material Lothöckers according to the invention. Therefore, during the manufacturing process of this diffusion barrier layer, the otherwise necessary pretreatment to achieve a good primer, be it through a cleaning solution or a germination bath, can be dispensed with.
- the method steps for pretreating a solder bump core are no longer necessary, which means a considerable saving of time and thus allows a higher throughput.
- the first process step of the method according to the invention is that on a carrier material, for. B. on a wafer or a semiconductor chip, one or more solder bump cores are produced.
- a diffusion barrier layer is then deposited directly onto these cores without pretreatment. This is advantageously carried out using an electroless, autocatalytic process, as a result of which the diffusion barrier layer material is deposited only on the solder bump cores and not on the passivation layers in areas between the solder bumps.
- the layer thickness of a diffusion barrier layer can be adjusted very simply by the dwell time in the catalytic bath and can be made so large that a diffusion of gold or solder material, in particular tin, through this layer is excluded.
- the material of the diffusion barrier layer should neither diffuse into the core of the solder bump nor be dissolved by the solder material which will later come into contact with the solder bump during the soldering process.
- a further layer is applied to the diffusion barrier layer after a cleaning or rinsing process, which layer protects the diffusion barrier layer from oxidation and enables good solder wetting.
- a thin gold layer is preferably applied, this being best done by immersion in an immersion gold bath.
- This outer protective gold layer is so thin and thus the absolute gold content so low that the formation of intermetallic phases of this gold with the solder does not lead to an impairment of the mechanical stability of the solder connection. Since the inventive method a pretreatment of the Loth ⁇ cker core is unnecessary, it can be carried out particularly easily and quickly, so that it is also very suitable for the industrial scale.
- a solder bump core is preferably produced mechanically as a so-called ball bump.
- a conventional wire bonding device is used for this purpose, the software used and the holding device for the bonding wire being slightly modified in accordance with the requirements of ball bump production.
- the bonding wire is pressed onto a connection surface (pad), which together with the heat generated thereby and the applied ultrasound (eg thermosonic bonding) leads to a connection to the pad.
- the geometrical dimensions of a ball bump can be adjusted by the choice of the bonding parameters pressure (of the wire on the pad) and in particular the bonding wire diameter.
- the wire is cut through a flame device of the wire bonding device and the height of the ball bump is thus determined. In order to achieve larger bump heights, several, typically two to three, ball bumps of this type are often stacked on top of one another.
- the diffusion barrier layer is formed from nickel and / or palladium.
- palladium is used as the germination material. Therefore, commercially available wire material with a high proportion of gold and a low residual proportion of palladium can be used inexpensively to produce the mechanical ball bumps.
- mechanical ball bumps can be produced with comparatively little effort and thus inexpensively, in particular also on individual chips. B. as part of a prototype production. Their small space requirement, also in the manufacture, is an advantage which enables their use in fields of application which, in particular, cannot be tapped at all or only to a very limited extent by known galvanic gold bumps.
- its mechanical deformability can be adjusted in comparatively wide ranges both in the vertical and in the horizontal direction.
- a low deformability in the horizontal direction allows the production of gold ball bumps in the immediate vicinity without having to fear short circuits.
- a high degree of deformability in the vertical direction is a prerequisite for the slightly different heights of gold ball bumps, for. B. on a semiconductor chip during the soldering process and thus the planarity of the components connected to the bumps is achieved.
- the diffusion barrier layer applied to a solder bump core prevents the diffusion from the gold of the solder bump core to the solder, which comes into contact with the solder bump according to the invention, and vice versa.
- the electrical and thermal conductivity of such a diffusion barrier layer is high and the contact resistances to the neighboring layers, in particular to the solder bump core, are low.
- the mechanical properties, such as good adhesive strength and resistance to mechanical and thermal stresses, are met extremely well by the solder bump according to the invention.
- connection techniques are soldering methods in flip-chip technology in which the solder has been deposited on the substrate or in which the solder remains adhered to the bumps according to the invention by adhesive forces by immersion in liquid solder.
- soldering plugs according to the invention are to be carried out by the individual user in accordance with the application.
- Gold ball bumps are an inexpensive alternative to electroplated gold bumps.
- this bump metallization can also be used for the first time for flip-chip assembly with solder, in particular lead / tin solder.
- the small proportion of a seeding material in a gold ball bump also has the advantage that the pretreatment necessary for electroplated gold bumps to achieve a good primer for the applied diffusion barrier layer can be dispensed with. This means that the method according to the invention manages at least one whole process step less.
- An advantage of the simple and inexpensive process technology in the method according to the invention becomes particularly clear when applied to wafers with hundreds of bumps. This enables a very high throughput (high volume production) to be achieved in industrial production.
- the invention is described below with reference to an embodiment with reference to the drawing.
- the single figure shows the section of a silicon chip with a mechanically generated gold ball bump, onto which a diffusion barrier layer made of nickel and a gold contact metallization are deposited.
- gold ball bumps (4) are formed on the aluminum pads (2) of a silicon chip (1).
- the areas outside the aluminum pads are provided with electrically non-conductive passivation layers (3) for protection.
- Wire material with 98% gold and 2% palladium is used to manufacture the ball bumps with conventional wire bonders.
- only a section of the silicon chip with a single ball bump is shown in the figure.
- the gold ball bumps of the silicon chip are in one step in the second process step
- Commercial baths have proven to be suitable. With a dwell time of approx. 8 minutes and a growth rate of the nickel layer of approx. 25 ⁇ m per hour, a nickel layer of approx. 3 ⁇ m is deposited. After the nickel layer has been formed, it is rinsed in a water bath.
- the nickel-coated gold ball bumps on the silicon chip are then immersed in an immersion gold bath.
- the gold layer is deposited on a bump until a closed gold layer has formed and the exchange of ions with the nickel layer has ended.
- the immersion gold layer (6) formed has a maximum thickness of approximately 0.2 ⁇ m. This contact metallization made of gold has the advantage that it leads to a good wetting of the solder and also protects the nickel against oxidation.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/849,035 US5906312A (en) | 1994-12-02 | 1995-11-10 | Solder bump for flip chip assembly and method of its fabrication |
JP8518016A JPH10511226A (ja) | 1994-12-02 | 1995-11-10 | フリップチップ実装用はんだバンプおよびその製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEP4442960.6 | 1994-12-02 | ||
DE4442960A DE4442960C1 (de) | 1994-12-02 | 1994-12-02 | Lothöcker für die Flip-Chip-Montage und Verfahren zu dessen Herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996017382A1 true WO1996017382A1 (de) | 1996-06-06 |
Family
ID=6534757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1995/001590 WO1996017382A1 (de) | 1994-12-02 | 1995-11-10 | Lothöcker für die flip-chip-montage und verfahren zu dessen herstellung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5906312A (de) |
JP (1) | JPH10511226A (de) |
KR (1) | KR100373085B1 (de) |
DE (1) | DE4442960C1 (de) |
WO (1) | WO1996017382A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242106B1 (en) | 1998-05-13 | 2001-06-05 | W. C. Hereaeus Gmbh & Co. Kg | Fine wire made of a gold alloy, method for its production, and its use |
Families Citing this family (29)
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JP2962351B2 (ja) * | 1997-03-31 | 1999-10-12 | 日本電気株式会社 | 半導体チップへの接合構造及びそれを用いた半導体装置 |
DE19733954A1 (de) * | 1997-07-07 | 1999-01-14 | Heraeus Gmbh W C | Feinstdraht aus einer Goldlegierung, Verfahren zu seiner Herstellung und seine Verwendung |
EP0890987B1 (de) * | 1997-07-07 | 2003-03-05 | W.C. Heraeus GmbH & Co. KG | Feinstdraht aus einer Goldlegierung, Verfahren zu seiner Herstellung und seine Verwendung |
TW366548B (en) * | 1998-04-18 | 1999-08-11 | United Microelectronics Corp | Trench bump block and the application of the same |
US6164523A (en) * | 1998-07-01 | 2000-12-26 | Semiconductor Components Industries, Llc | Electronic component and method of manufacture |
DE19838418A1 (de) * | 1998-08-24 | 2000-03-02 | Delphi Automotive Systems Gmbh | Elektrische Anschlußvorrichtung sowie Verfahren zur Herstellung einer elektrischen Kontaktierung |
DE19921475C2 (de) * | 1999-05-08 | 2003-04-10 | Abb Patent Gmbh | Kontaktanordnung für Schalter, Schütze, ect. |
US6316286B1 (en) | 1999-10-13 | 2001-11-13 | Teraconnect, Inc. | Method of equalizing device heights on a chip |
DE60109339T2 (de) * | 2000-03-24 | 2006-01-12 | Texas Instruments Incorporated, Dallas | Verfahren zum Drahtbonden |
DE10025147C2 (de) * | 2000-05-20 | 2002-03-07 | Orga Kartensysteme Gmbh | Kontaktanordnung für mehrkomponentige Smart Cards |
US6492197B1 (en) * | 2000-05-23 | 2002-12-10 | Unitive Electronics Inc. | Trilayer/bilayer solder bumps and fabrication methods therefor |
US6643099B1 (en) | 2000-06-20 | 2003-11-04 | Seagate Technology Llc | Transducer formed on a sacrificial metal substrate |
US20020056742A1 (en) * | 2000-11-10 | 2002-05-16 | Rinne Glenn A. | Methods and systems for attaching substrates to one another using solder structures having portions with different melting points |
DE60108413T2 (de) * | 2000-11-10 | 2005-06-02 | Unitive Electronics, Inc. | Verfahren zum positionieren von komponenten mit hilfe flüssiger antriebsmittel und strukturen hierfür |
US6445069B1 (en) | 2001-01-22 | 2002-09-03 | Flip Chip Technologies, L.L.C. | Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor |
WO2004001837A2 (en) * | 2002-06-25 | 2003-12-31 | Unitive International Limited | Methods of forming electronic structures including conductive shunt layers and related structures |
US7531898B2 (en) * | 2002-06-25 | 2009-05-12 | Unitive International Limited | Non-Circular via holes for bumping pads and related structures |
US7547623B2 (en) * | 2002-06-25 | 2009-06-16 | Unitive International Limited | Methods of forming lead free solder bumps |
US7015590B2 (en) * | 2003-01-10 | 2006-03-21 | Samsung Electronics Co., Ltd. | Reinforced solder bump structure and method for forming a reinforced solder bump |
US6959856B2 (en) * | 2003-01-10 | 2005-11-01 | Samsung Electronics Co., Ltd. | Solder bump structure and method for forming a solder bump |
TWI225899B (en) * | 2003-02-18 | 2005-01-01 | Unitive Semiconductor Taiwan C | Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
JP4863746B2 (ja) * | 2006-03-27 | 2012-01-25 | 富士通株式会社 | 半導体装置およびその製造方法 |
US20080083993A1 (en) * | 2006-10-04 | 2008-04-10 | Texas Instruments Incorporated | Gold-Tin Solder Joints Having Reduced Embrittlement |
US7749887B2 (en) * | 2007-12-18 | 2010-07-06 | Micron Technology, Inc. | Methods of fluxless micro-piercing of solder balls, and resulting devices |
US8476757B2 (en) * | 2009-10-02 | 2013-07-02 | Northrop Grumman Systems Corporation | Flip chip interconnect method and design for GaAs MMIC applications |
JP5383460B2 (ja) * | 2009-12-04 | 2014-01-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US9620469B2 (en) | 2013-11-18 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming post-passivation interconnect structure |
FR3088018B1 (fr) * | 2018-11-06 | 2023-01-13 | Mbda France | Procede de liaison par brassage permettant d'ameliorer la tenue en fatigue de joints brases |
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US3893156A (en) * | 1973-06-29 | 1975-07-01 | Ibm | Novel beam lead integrated circuit structure and method for making the same including automatic registration of beam leads with corresponding dielectric substrate leads |
EP0256357A2 (de) * | 1986-08-11 | 1988-02-24 | International Business Machines Corporation | Halbleiterchip mit einer Höckerstruktur für automatische Bandmontage |
JPH02238630A (ja) * | 1989-03-11 | 1990-09-20 | Takehide Shirato | 半導体装置 |
US5028454A (en) * | 1989-10-16 | 1991-07-02 | Motorola Inc. | Electroless plating of portions of semiconductor devices and the like |
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DE2032872B2 (de) * | 1970-07-02 | 1975-03-20 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen weichlötfähiger Kontakte zum Einbau von Halbleiterbauelementen in Gehäuse |
US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JP2833996B2 (ja) * | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | フレキシブルフィルム及びこれを有する半導体装置 |
-
1994
- 1994-12-02 DE DE4442960A patent/DE4442960C1/de not_active Expired - Lifetime
-
1995
- 1995-11-10 US US08/849,035 patent/US5906312A/en not_active Expired - Fee Related
- 1995-11-10 JP JP8518016A patent/JPH10511226A/ja active Pending
- 1995-11-10 KR KR1019970703334A patent/KR100373085B1/ko not_active IP Right Cessation
- 1995-11-10 WO PCT/DE1995/001590 patent/WO1996017382A1/de active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3893156A (en) * | 1973-06-29 | 1975-07-01 | Ibm | Novel beam lead integrated circuit structure and method for making the same including automatic registration of beam leads with corresponding dielectric substrate leads |
EP0256357A2 (de) * | 1986-08-11 | 1988-02-24 | International Business Machines Corporation | Halbleiterchip mit einer Höckerstruktur für automatische Bandmontage |
JPH02238630A (ja) * | 1989-03-11 | 1990-09-20 | Takehide Shirato | 半導体装置 |
US5028454A (en) * | 1989-10-16 | 1991-07-02 | Motorola Inc. | Electroless plating of portions of semiconductor devices and the like |
Non-Patent Citations (1)
Title |
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PATENT ABSTRACTS OF JAPAN vol. 14, no. 553 (E - 1010) 7 December 1990 (1990-12-07) * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242106B1 (en) | 1998-05-13 | 2001-06-05 | W. C. Hereaeus Gmbh & Co. Kg | Fine wire made of a gold alloy, method for its production, and its use |
Also Published As
Publication number | Publication date |
---|---|
US5906312A (en) | 1999-05-25 |
JPH10511226A (ja) | 1998-10-27 |
KR970707584A (ko) | 1997-12-01 |
DE4442960C1 (de) | 1995-12-21 |
KR100373085B1 (ko) | 2003-06-19 |
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