WO1996007122A1 - Procede pour la production d'un dispositif d'affichage a cristaux liquide du type a matrice active - Google Patents

Procede pour la production d'un dispositif d'affichage a cristaux liquide du type a matrice active Download PDF

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Publication number
WO1996007122A1
WO1996007122A1 PCT/JP1995/000509 JP9500509W WO9607122A1 WO 1996007122 A1 WO1996007122 A1 WO 1996007122A1 JP 9500509 W JP9500509 W JP 9500509W WO 9607122 A1 WO9607122 A1 WO 9607122A1
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WO
WIPO (PCT)
Prior art keywords
signal line
liquid crystal
crystal display
video signal
display device
Prior art date
Application number
PCT/JP1995/000509
Other languages
English (en)
Japanese (ja)
Inventor
Minoru Hiroshima
Yuka Aoki
Hideaki Yamamoto
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1996007122A1 publication Critical patent/WO1996007122A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects

Definitions

  • the present invention relates to a liquid crystal display substrate, and more particularly to an active matrix type liquid crystal display substrate.
  • an active matrix type liquid crystal display substrate is a transparent substrate which is arranged to face each other via a liquid crystal, and a gate arranged in parallel with a surface of one of the transparent substrates on a liquid crystal side.
  • the line group and the drain line group are arranged so as to be insulated and cross each other.
  • the territory surrounded by each line becomes a pixel region, and these pixel regions are arranged in a matrix to constitute a display surface.
  • a switching element that is turned on by a scanning signal from a gate line and a video signal from a drain line are supplied to each of these elementary castles via the switching element.
  • Such liquid crystal display substrates have been increasingly driven in a so-called normally white mode from the viewpoint of good display performance. ing.
  • an object of the present invention is to provide a liquid crystal display substrate in which the above-mentioned white spot is not generated. To do that.
  • the present invention basically provides a display surface with each surface element arranged in a matrix, and a surface element electrode of each pixel.
  • a video signal is supplied from a drain line via a switching element that is turned on by a scanning signal from a gate line
  • the liquid crystal display substrate attenuates light transmission of liquid crystal in the pixel.
  • conduction processing is performed between the pixel electrode and this pixel electrode and the adjacent good line or drain line.
  • a white point display defect of a pixel is repaired to display a black point.
  • the signal line for conducting the conduction with the surface element electrode is not limited to the drain line, and the same effect can be obtained even with the gate line.
  • Such a liquid crystal display substrate can prevent the display surface from being disturbed by so-called white point display.
  • FIG. 1 is an explanatory view showing one embodiment of a method for manufacturing a liquid crystal display substrate according to the present invention.
  • FIG. 2 is a plan view of an essential part showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied and the periphery thereof.
  • FIG. 3 is a cross-sectional view showing one pixel and its periphery taken along a section line 3-3 in FIG.
  • FIG. 4 is a cross-sectional view of the additional capacitance C add taken along the line 4-14 in FIG.
  • FIG. 5 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.
  • FIG. 6 is a plan view of a panel for more specifically explaining the periphery of FIG. 5 in a slightly exaggerated manner.
  • FIG. 7 is an enlarged plan view of a corner of the display panel including the electrical connection portions of the upper and lower substrates.
  • Fig. 8a is a cross-sectional view near the panel angle
  • Fig. 8b is a cross-sectional view of a matrix element of the matrix
  • Fig. 8c is a cross-sectional view showing the vicinity of a video signal terminal.
  • FIG. 9a is a sectional view showing a scanning signal terminal
  • FIG. 9b is a sectional view showing a panel edge portion without an external connection terminal.
  • FIG. 10a is a plan view showing the vicinity of the connection between the gate terminal GTM and the gate signal line GL
  • FIG. 10b is a sectional view thereof.
  • FIG. 11a is a plan view showing the vicinity of the connection between the drain terminal DTM and the video signal line DL, and FIG. 11b is a sectional view thereof.
  • FIG. 12 is a circuit diagram including a matrix portion and its periphery of an active matrix type color liquid crystal display device.
  • FIG. 13 is a plan view showing the manufacturing process of processes A to C 'on the substrate SUB1 side.
  • FIG. 2 is a flowchart of a cross-sectional view of a section and a gate terminal section.
  • FIG. 14 is a flowchart of a cross-sectional view of a pixel portion and a good terminal portion showing a manufacturing process of processes D to F on the substrate SUB1 side.
  • FIG. 15 is a flowchart of a cross-sectional view of a surface element and a gate terminal showing a manufacturing process of processes G to H ′ on the substrate SUB 1 side.
  • FIG. 16 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes 1 to 1 ′′ on the substrate SUB 1 side.
  • FIG. 17 is an exploded perspective view of the liquid crystal display module.
  • FIG. 18 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.
  • FIG. 19 is a diagram showing a sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.
  • FIG. 20 is a cross-sectional view of a principal part showing a state where the tape carrier package TCP is connected to the video signal circuit terminal DTM of the liquid crystal display panel PNL.
  • FIG. 21 is a top view showing a connection state between the peripheral drive circuit board PCB1 (the upper surface is visible) and the power supply circuit circuit board PCB2 (the lower surface is visible).
  • FIGS. 22a to 22c are process diagrams for repairing the disconnection of the gate signal line GL.
  • FIG. 23 shows an embodiment of a photo-CVD apparatus used in the present invention.
  • FIGS. 24a to 24c are diagrams illustrating the process of repairing the disconnection of the video signal line D L.
  • FIG. 25 is an explanatory diagram showing a configuration for repairing a short circuit between the good signal line GL and the video signal line DL.
  • FIG. 26 is a diagram for explaining the white spot inspection method.
  • FIGS. 27A to 27C are process diagrams showing another embodiment for repairing the disconnection of the video signal line DL.
  • FIGS. 28A to 28C are process diagrams for explaining an embodiment for repairing a white spot defect.
  • FIGS. 29A to 29C are process diagrams for explaining another embodiment for repairing a white spot defect.
  • FIGS. 30a and 30b are views for explaining the scanning method of the laser beam 6 of the present invention.
  • FIGS. 31a and 31b are views showing another embodiment of the scanning method of the laser beam 6 of the present invention.
  • FIG. 32 is a diagram showing another embodiment of the optical CVD device used in the present invention.
  • FIGS. 33a and 33b are views showing the configuration of another embodiment of the present invention.
  • FIG. 34 a and FIG. 34 b are process diagrams showing a repair process based on the configuration shown in FIG. 33.
  • FIGS. 35a to 35c are diagrams showing the configuration of another embodiment of the present invention.
  • FIG. 36a and FIG. 36b are process diagrams showing a repair process based on the configuration shown in FIG.
  • FIGS. 37a and 37b are process diagrams for explaining another embodiment for repairing a white spot defect.
  • FIG. 2 is a plan view showing one pixel of an active matrix type color liquid crystal display device S to which the present invention is applied and the periphery thereof, and FIG. 3 is a sectional view taken along a section line 13 in FIG. FIG. 4 is a cross-sectional view taken along the line 4-14 in FIG. 2;
  • each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines). Line) It is located in the territory crossing with DL (in the area surrounded by four signal lines).
  • Each element is a thin film transistor Including Star TFT, transparent pixel electrode ITO1, and storage capacitor (additional capacitor) Cadd.
  • the scanning signal lines GL extend in the left-right direction in FIG.
  • the video signal lines DL extend in the vertical direction, and a plurality of video signal lines DL are arranged in the horizontal direction.
  • a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC layer, and the upper transparent glass substrate SUB2 side.
  • a color filter FIL and a black matrix pattern BM for shading are formed on the substrate.
  • silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2.
  • a light shielding film BM On the inner surface of the upper transparent glass substrate SUB 2 (liquid crystal LC side), there are a light shielding film BM, a color filter FIL, a protective film PSV 2, a common transparent surface electrode ITO 2 (C OM) and an upper alignment film OR 1 2 are sequentially stacked.
  • FIG. 5 shows the main part plane around the matrix part AR of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2, Fig. 6 shows a plane exaggerating the peripheral part, and Fig. 7
  • FIG. 7 is an enlarged plan view near the seal portion SL corresponding to the upper left corner of the panel in FIGS. 5 and 6.
  • Fig. 8b shows a cross-sectional view of the pixel section similar to Fig. 3
  • Fig. 8a shows a cross section taken along the line 8a-8a in Fig. 7,
  • Fig. 8c shows the video signal drive.
  • FIG. 3 is a diagram showing a cross-sectional view near a drain terminal DTM to which a circuit is to be connected. You.
  • FIG. 9a is a diagram showing a cross section near a gate terminal GTM to which a scanning circuit is to be connected
  • FIG. 9b is a diagram showing a cross section near a seal portion where there is no external connection terminal.
  • FIGS. 5 to 7 show the latter example. Both FIGS. 5 and 6 show the upper and lower glass substrates SUB 1 and SUB 2 after cutting, and FIG. 7 shows the state before cutting. LN indicates the edge of both substrates before cutting, and CT1 and CT2 indicate the positions of the substrates SUB1 and SUB2 to be cut, respectively.
  • the external connection terminal groups T g and T d are located on the upper transparent glass substrate SUB 2 so that they are exposed. The size is limited inside the lower transparent glass substrate SUB1.
  • Each of the terminal groups T g and T d is a scanning circuit connection terminal (gate terminal) GTM, a video signal circuit connection terminal (drain terminal) DTM, and their lead-out wiring portions, which will be described later.
  • the tape carrier package TCP (see Figs. 18 and 19) on which the chip CHI is mounted is named as a group of multiple units.
  • the lead wires from the matrix part of each group to the external connection terminal part are inclined toward the both ends. This is the package TC This is to match the terminals DTM and GTM of the display panel PNL with the arrangement pitch of P and the connection terminal pitch of each package TCP.
  • a pattern of a sealing portion S is formed along the edges thereof so as to seal the liquid crystal LC except for the liquid crystal inlet INJ.
  • the sealing material is made of, for example, epoxy resin.
  • the common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side was formed on at least one location on the lower transparent glass substrate SUB1 side by a silver paste material AGP at four corners of the panel in this embodiment. It is connected to the lead wiring INT.
  • the lead wiring I NT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.
  • Each of the alignment films ORI1, ORI2, the transparent pixel electrode IT01, and the common transparent surface electrode ITO2 is formed inside the seal portion SL.
  • Polarizers POL 1 and POL 2 are formed on the outer surfaces of lower transparent glass substrate SUB 1 and upper transparent glass substrate SUB 2, respectively.
  • Liquid crystal LC has a lower alignment film ORI 1 that sets the orientation of liquid crystal molecules and an upper alignment film. It is sealed in the area partitioned by the sealing part SL between the membrane and the ORI 2.
  • the lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.
  • liquid crystal LC is injected from the liquid crystal filling port INJ of the sealing part SL, the liquid crystal filling port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are cut. Assembled.
  • Each surface element is provided with a plurality (two) of thin film transistors TFT1 and TFT2 redundantly.
  • Each of the thin-film transistors TFT 1 and TFT 2 has substantially the same size (the same channel length and channel width), and has a gate electrode G, a gate insulating film GI, and an i-type (intrinsic). , Intrinsic, conductivity type determining impurities are not doped).
  • An i-type semiconductor layer AS made of amorphous silicon (S i), a pair of source electrodes SD 1 and a drain electrode SD 2 are provided. Note that the source and drain are originally determined by the bias polarity between them, and the polarity of this liquid crystal display device is reversed during operation, so the source and drain are switched during operation. I want to be understood. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
  • the gate electrode GT is formed in a shape projecting vertically from the scanning signal line GL (branched into a T-shape).
  • the gate electrode GT protrudes beyond the active area of each of the thin film transistors TFT 1 and TFT 2.
  • the respective gate electrodes GT of the thin-film transistors TFT 1 and TFT 2 are integrally formed (as a common gate electrode) and formed continuously with the scanning signal line GL.
  • the gate electrode GT is formed of a single-layer second conductive layer g2.
  • the second conductive layer g2 for example, an aluminum (A1) film formed by a sputter is used, and an anodic oxide film AOF of A1 is provided thereon.
  • the gate electrode GT is formed so as to completely loosen the i-type semiconductor layer AS (as viewed from below) and is larger than the i-type semiconductor layer AS so that external light or backlight does not hit the i-type semiconductor layer AS. It is devised.
  • the scanning signal line GL is composed of the second conductive layer g2.
  • the second conductive layer g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive layer g2 of the gate electrode GT, and is integrally formed. Further, an anodic oxide film A OF of A 1 is also provided on the scanning signal line GL.
  • the insulating film (gate insulating film) GI is used as a gate insulating film for applying an electric field to the i-type semiconductor layer AS together with the gate electrode GT in the thin film transistors TFT 1 and TFT 2.
  • Insulating film GI is gate It is formed above the electrodes GT and the scanning signal lines GL. Insulating film G
  • a silicon nitride film formed by plasma CVD is selected as I, and is formed to a thickness of 1200 to 270 A (about 200 A in the present embodiment). Is done.
  • the insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminal DTMGTM.
  • the insulating film GI also contributes to electrical insulation between the scanning signal line GL and the video signal line DL.
  • the i-type semiconductor layer AS is formed so as to be an independent island for each of the thin film transistors TFT1 and TFT2, and is made of amorphous silicon having a thickness of 200 to 220A. It is formed to a thickness (in the present embodiment, a film thickness of about 2000 A).
  • the layer d O is an N (+) type amorphous silicon semiconductor layer doped with phosphorus (P) for an ohmic contact, and an i-type semiconductor layer AS exists below.
  • the second conductive film d 2 (or the third conductive film d 3) is left only on the upper side.
  • the i-type semiconductor layer AS is located at the intersection of the scanning signal line GL and the video signal line DL.
  • the i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the video signal line DL at the intersection.
  • the transparent pixel electrode ITO1 constitutes one of the pixel electrodes of the liquid crystal display.
  • the transparent pixel electrode ITO1 is the source electrode of the thin-film transistor TFT1. It is connected to both the source electrode SD1 of SD1 and the thin film transistor TFT2. For this reason, even if a defect occurs in one of the thin film transistors TFT 1 and TFT 2, if the defect causes a side effect, an appropriate part is cut with a laser beam, etc. Since the other thin-film transistor is operating normally, it may be left alone.
  • the transparent pixel electrode ITO 1 is composed of the first conductive film d 1, and this first conductive film d 1 is
  • the transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering has a thickness of 100 to 200 mm (in this embodiment, (A film thickness of about 140 A). ⁇ Source electrode SD 1, drain electrode SD 2 ⁇
  • Each of the source electrode SD 1 and the drain electrode SD 2 is composed of a second conductive film d 2 in contact with the N (+) type semiconductor layer d 0 and a third conductive film d 3 formed thereon. ing.
  • the second conductive film d2 is formed using a chromium (Cr) film formed by sputtering to a thickness of 500 to 100 A (in the present embodiment, about 600 A). You. Since the stress increases when the Cr film is formed with a large thickness, the Cr film is formed within a thickness not exceeding about 200 OA. The Cr film improves the adhesion to the N (+) type semiconductor layer d 0 and prevents A 1 of the third conductive film d 3 from diffusing into the N (+) type semiconductor layer d 0 ( Used for so-called barrier layer purposes.
  • Cr chromium
  • a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (M 0 S i 2 , T i S i 2, T a S i 2 , WS i 2) film may be used.
  • the third conductive film d3 is formed with a thickness of 300 to 500 A by sputtering of Al (about 400 A in the present embodiment).
  • the A1 film has a smaller stress than the Cr film and can be formed to have a large thickness, and the resistance values of the source electrode SD1, the drain electrode SD2 and the video signal line DL are low. It has the function of ensuring that the gate electrode GT or the i-type semiconductor layer AS crosses a step (improves step coverage).
  • the N (+)-type semiconductor layer d0 is removed, that is, the N (+)-type semiconductor layer dO remaining on the i-type semiconductor layer AS becomes the second conductive film d2 and the third conductive layer d2. Portions other than the conductive film d3 are removed by self-alignment.
  • the N (+) type semiconductor layer d O is etched so as to remove the entire thickness thereof, the surface of the i type semiconductor layer AS is also slightly etched. May be controlled by the etching time.
  • the video signal line DL is composed of the second conductive film d2 and the third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2.
  • a protective film PSV1 is provided on the thin-film transistor TFT and the transparent pixel electrode ITO.
  • Protective film PSV 1 is mainly used for thin film transistors.
  • the protective film PSV1 is formed of, for example, a silicon oxide film / silicon nitride film formed by a plasma CVD device, and has a thickness of about ⁇ .
  • the protective film PSV1 is formed so as to surround the entire matrix portion AR, the peripheral portion is removed so as to expose the external connection terminals DTM and GTM, and the upper portion is removed.
  • the part connecting the common electrode COM on the transparent glass substrate SUB2 side to the lead-out wiring INT for connecting the external connection terminal of the lower transparent glass substrate SUB1 by silver paste AGP is also removed.
  • the thickness relationship between the protective film PSV1 and the gate insulating film GI the former is made thicker in consideration of the protective effect, and the latter is made thinner to increase the mutual conductance gm of the transistor. Therefore, as shown in FIG. 7, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect the peripheral portion as widely as possible.
  • a light shielding film BM is provided on the upper transparent glass substrate SUB2 side to prevent external light or backlight from entering the i-type semiconductor layer AS.
  • the square outline indicates the opening where the light shielding film BM is not formed on the ⁇ side.
  • the light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property.
  • the chromium film has a thickness of about 130 OA by a sparing. It is formed. Therefore, the i-type semiconductor layers AS of the thin film transistors TFT 1 and TFT 2 are sandwiched by the upper and lower light shielding films BM and the large gate electrodes GT, and are exposed to external natural light or backlight light. Will not hit.
  • the light-shielding film BM is formed in a grid around each pixel (so-called black matrix), and the grid separates the effective display area of one element. Therefore, the contour of each pixel is clearly defined by the light shielding film BM, and the contrast is improved. That is, the light-shielding film BM has two functions, that is, light-shielding and black matrix for the i-type semiconductor device AS.
  • the edge portion of the transparent pixel electrode ITO 1 on the root side in the rubbing direction (see the lower right portion in FIG. 2) is also shielded from light by the light shielding film BM, it is assumed that a domain occurs in the above portion. However, since the domain is not visible, the display characteristics are not degraded.
  • the light-shielding film BM is also formed in a frame shape on the peripheral part as shown in FIG. 6, and its pattern is continuous with the pattern of the matrix part shown in FIG. 2 having a plurality of openings in a dot shape. Is formed.
  • the light shielding film BM in the peripheral part is extended outside the seal part SL, and leakage light such as reflected light caused by a mounting machine such as a personal computer is matrices. It prevents entry into the task area.
  • the light-shielding film BM is fixed to the side of about 0.3 to about L.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.
  • Color filter FIL is red, green, green
  • the strip is formed by turning it over.
  • the color filter FIL is formed to be large enough to cover all of the transparent pixel electrode ITO 1, and the light shielding film BM is overlapped with the edge portion of the color filter FIL and the transparent pixel electrode ITO 1. It is formed on the ⁇ side of the periphery of 1.
  • the color filter FIL can be formed as follows. First, a dye base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base material other than the red filter formation region is removed by photolithography. Thereafter, the dyeing base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process.
  • a dye base material such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2
  • the dye base material other than the red filter formation region is removed by photolithography. Thereafter, the dyeing base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R.
  • a green filter G and a blue filter B are sequentially formed by performing a similar process.
  • the protective film PSV2 is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC.
  • the protective film PSV2 is made of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.
  • the common transparent pixel electrode I ⁇ 0 2 faces the transparent pixel electrode ITO 1 provided for each pixel on the lower transparent glass substrate SUB 1 side, and the optical state of the liquid crystal is the same as the pixel electrode ITO 1 and the common transparent pixel. It changes in response to the potential difference (electric field) between the electrodes ITO 2.
  • This common transparent pixel electrode I ⁇ 0 2 faces the transparent pixel electrode ITO 1 provided for each pixel on the lower transparent glass substrate SUB 1 side, and the optical state of the liquid crystal is the same as the pixel electrode ITO 1 and the common transparent pixel. It changes in response to the potential difference (electric field) between the electrodes ITO 2.
  • This common transparent pixel electrode I ⁇ 0 2 faces the transparent pixel electrode ITO 1 provided for each pixel on the lower transparent glass substrate SUB 1 side, and the optical state of the liquid crystal is the same as the pixel electrode ITO 1 and the common transparent pixel. It changes in response to the potential difference (electric field) between the electrodes ITO 2.
  • ITO 2 is configured such that a common voltage Vcom is applied.
  • the common voltage Vcom is the maximum voltage applied to the video signal line DL. /
  • the transparent pixel electrode I TOl is formed so as to overlap an adjacent scanning signal line GL at an end opposite to the end connected to the thin-film transistor TFT. As can be seen from FIG. 4, this superposition is performed by using a storage capacitor in which the transparent surface electrode ITO 1 is used as one electrode PL 2 and the adjacent scanning signal line GL is used as the other electrode PL 1.
  • Element (Yoshi Shizugame * Element) Constructs Cadd.
  • the dielectric film of the storage capacitance element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.
  • the storage capacitance element Cadd is formed in a portion of the scanning signal line GL where the width of the second conductive layer g2 is increased.
  • the portion of the second conductive layer g2 that intersects with the video signal line DL is thinned in order to reduce the probability of a short circuit with the video signal line DL.
  • the second conductive film d2 and the third conductive film d3 were formed so as to extend over the step even if the transparent pixel electrode ITOl was disconnected at the step of the electrode PL1 of the storage capacitor Cadd. The defect is compensated for by the island region. ⁇ Gate terminal section ⁇
  • FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, wherein FIG. 10a is a plane and FIG. 10b is A cross section taken along the line BB of FIG. 10a is shown. Note that this figure corresponds to the lower portion of FIG. 7, and the oblique wiring portion is represented by a straight line for convenience.
  • AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodizing. Therefore, this photoresist is removed after anodization, and the pattern AO shown in the figure is not left as a finished product, but the gate signal line GL has an oxide film AOF as shown in the sectional view. Are selectively formed, so that the trajectory remains.
  • second conductive layer g 2 is the oxide a 1 2 O 3 film AOF is formed the conductive portion of the downward surface of the layer body somewhat decreases.
  • the anodization is performed by setting the voltage and the like for an appropriate time so that the conductive portion remains.
  • the mask pattern AO does not intersect the scanning signal line GL with a single straight line, but intersects by bending in a crank shape.
  • the second conductive layer g 2 of the AL layer is hatched for easy understanding, but the area that is not anodized is putter-like in a comb shape. Since the hoisting force is generated in each case, the width of each one is narrowed, and a configuration in which a plurality of them are bundled in parallel is adopted. Rather, the aim is to minimize the probability of disconnection and sacrificing conductivity while preventing the generation of a hoisting force. Therefore, in this example, the portion corresponding to the root of the comb is also shifted along the mask AO.
  • the good terminal GTM has a good adhesion to the silicon oxide film SIO and has a first conductive layer g1 of a Cr layer having higher electric contact resistance than A1 and the like. 1 and the same level (same layer, simultaneous formation) of transparent conductive layer dl.
  • the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surface thereof have the conductive layers g2 and g1 due to pinholes and the like at the time of etching the conductive films d3 and d2. It remains as a result of covering the territory with a photoresist so that it cannot be etched together.
  • the I-layer O d1 extending to the right over the gate insulating film G I is a more thorough countermeasure.
  • the gate insulating film GI is formed on the right side of the boundary line
  • the protective film PSV1 is formed on the right side of the boundary line
  • the terminal portion GTM located on the left end comes out of them. Electrical contact with external circuits.
  • FIG. 7 only one pair of the gate signal line GL and the gate terminal is shown. However, as shown in FIG. 7, a plurality of such pairs are vertically arranged as shown in FIG. (See Fig. 6 and Fig. 7).
  • the left end of the gate terminal is extended beyond the cutting area CT1 of the substrate and short-circuited by the wiring SHg in the manufacturing process.
  • such a short-circuit line SH g is supplied with electricity during anodization and is oriented Useful for preventing electrostatic breakdown during rubbing of membrane ORI1.
  • FIGS. 11a and 11b show the connection from the video signal line DL to the external connection terminal DTM
  • FIG. 11a shows the plane
  • FIG. FIG. 11 shows a cross section taken along the line BB in FIG.
  • This figure corresponds to the vicinity of the upper right of FIG. 7, and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end (or lower end) of the substrate SUB1.
  • TSTd is a test terminal, which is not connected to an external circuit, but is wider than the wiring part so that probe needles can be contacted. Similarly, the width of the drain terminal DTM is wider than that of the wiring section so that it can be connected to an external circuit.
  • the test terminals TST d and the external connection drain terminals DTM are alternately arranged in a staggered pattern in the vertical direction, and the test terminals TST d do not reach the end of the substrate SUB 1 as shown in the figure. However, as shown in FIG. 7, the drain terminal DTM forms a terminal group Td (subscript omitted), and is further extended beyond the cutting line CT1 of the substrate SUB1 during the manufacturing process.
  • a drain connection terminal is connected to the other side of the matrix of the video signal line DL having the inspection terminal TST d, and conversely, a drain connection terminal of the video signal line DL having the drain connection terminal DTM is provided. Inspection terminals are connected to the other side of the matrix.
  • the drain connection terminal DTM is formed of two layers, the first conductive layer g1 of the Cr layer and the ITO layer d1, for the same reason as the gate terminal GTM described above.
  • the portion where the gate insulating film GI is removed is connected to the video signal line DL.
  • the semiconductor layer AS formed on the end of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape.
  • the protective film PSV 1 is removed as a matter of course for connection with an external circuit.
  • AO is the anodized mask described above, and its boundary is formed so as to greatly surround the entire matrix, and the mask is covered on the left side from the boundary in the figure. This pattern is not directly related since the second conductive layer g2 does not exist in the portion not covered by the pattern.
  • the lead-out wiring from the matrix part to the drain terminal part DTM is directly above the layers d1 and gl at the same level as the drain terminal part DTM.
  • the layers d 2 and d 3 at the same level as the video signal line DL are layered halfway through the seal part SL, but this minimizes the probability of disconnection and makes it easy to touch.
  • Protective film for d3 consisting of A1 layer? The aim is to protect as much as possible with the SV1 and the seal SL.
  • Figure 12 shows the connection diagram of the equivalent circuit of the display matrix and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement.
  • AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.
  • X means a video signal line DL
  • suffixes G, B, and R are added corresponding to green, white, and red pixels, respectively.
  • Y is the scanning signal 0 9
  • the line GL means that the subscripts 1, 2, 3,..., end are added according to the order of the scanning timing.
  • the video signal lines X are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.
  • the scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.
  • the SUP uses a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from a single voltage source, and CRT (cathode ray tube) information from a host (upper processing unit) for a TFT liquid crystal display device. It is a circuit that includes a circuit that exchanges information.
  • Holding capacity 1: The element C add works to reduce the influence of the gate potential change Vg on the midpoint potential (pixel electrode potential) Vic when the thin film transistor TFT is switched. This situation is expressed as follows.
  • Vlc ⁇ C gs / (C gs + C add + C pix) ⁇ X
  • Cgs is a parasitic capacitance formed between the gate electrode GT of the thin-film transistor TFT and the source electrode SD1
  • Cpix is a transparent pixel electrode ITO1 (PIX) and a common transparent pixel electrode IT02.
  • a Vlc represents a capacitance formed between the pixel electrode and (C OM) and represents a change in pixel electrode potential due to A Vg. This change A Vlc causes a DC component to be applied to the liquid crystal LC, but the larger the storage capacitance Cadd, the smaller the value. / 95/00509
  • the storage capacitor C add also has a function of extending the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time.
  • the reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and reduces the so-called burn-in, in which the previous image remains when the liquid crystal display screen is switched.
  • the gate electrode GT is large enough to completely cover the i-type semiconductor layer AS, the overlap between the source electrode SD 1 and the drain electrode SD 2 increases. Accordingly, the parasitic capacitance Cgs increases, and the midpoint potential Vic has an adverse effect that the gate (scanning) signal Vg becomes more susceptible to the influence.
  • the storage capacitor Cadd this disadvantage can be solved.
  • the storage capacitance of the storage capacitance element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4 ⁇ Cpix ⁇ Cadd ⁇ 8 ⁇ Cpix), and 8 to 3 compared to the parasitic capacitance Cgs, due to the harmful characteristics of the pixels. Set the value to about twice (8 ⁇ Cgs ⁇ Cadd ⁇ 32 ⁇ Cgs).
  • the first-stage scanning signal line GL (Y.) used only as a storage capacitor electrode line is set to the same potential as the common transparent pixel electrode IT02 (Vcom).
  • the first-stage scanning signal line is short-circuited to the common electrode COM through the terminal GT0, the lead line INT, the terminal DT0, and external wiring.
  • the first stage storage capacitor electrode line Y. Is connected to the scanning signal line Y end of the last stage, and is connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y from the vertical scanning circuit V. You may be connected to receive "Production method"
  • a silicon oxide film SIO is provided on both sides of a lower transparent glass substrate SUB 1 made of glass (trade name) by dip treatment, followed by baking for 500 minutes: 60 minutes. No.
  • a first conductive layer g 1 made of chromium having a thickness of 110 OA is provided on the lower transparent glass substrate SUB 1 by sputtering, and after photo processing, nitric acid is used as an etching solution.
  • the first conductive layer g1 is selectively etched with a ceramic ammonium solution.
  • an anodized bus line SHg for connecting the gate terminal GTM, the drain terminal DTM, and the gate terminal GTM, a bus line SHd for short-circuiting the drain terminal DTM, and anodized An anodic oxidation pad (not shown) connected to pass line SH g is formed.
  • Bus line S As shown in Fig. 7, the patterns of Hd and the bus line SHg are electrically connected by the lightning rod pattern PRT.
  • the second conductive layer g2 consisting of A1—Pd, A1—Si, A1—Si—Ti, A1-Si1Cu, etc. having a thickness of 280 A is sputtered. Provided by ring. After the photographic processing, the second conductive layer g 2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acid.
  • anodizing solution consisting of a solution of 3% tartaric acid adjusted to PH 6.25 ⁇ 0.05 with ammonia diluted 1: 9 with ethylene glycol solution to the substrate SUB 1 and Hita ⁇
  • formation current density is adjust as becomes 0. 5 m a cm 2 in (constant current Kasei).
  • row anodic oxidation until the required formation voltage 1 2 5 V to 1 2 0 3 film thickness given A is obtained. Thereafter, it is desirable to hold this state for several 10 minutes (constant voltage formation). This is important for obtaining a uniform A 1 2 ⁇ 3 film.
  • the second conductive layer g2 is anodized, and an anodized film AOF having a thickness of 180 OA is formed on the scanning signal line GL, the gate electrode GT, and the electrode PL1.
  • An inspection is performed to determine whether the scanning signal line GL formed of the second conductive layer g2 thus formed is normally connected and no disconnection has occurred.
  • the inspection is performed by bringing the probe into contact with gate terminals electrically connected to both ends of each scanning signal line GL and measuring the electric resistance of the scanning signal line GL.
  • FIGS. 22a to 22c show, for example, cross sections taken along line 2-2 in FIG. This cross section is, for example, visually shown, and the e information is obtained by some means.
  • the lower glass substrate SUB is placed on the X-Y stage 1 placed opposite to the microscope, and when a disconnection is found through the microscope. This can be done by associating the position of the XY stage with the position information. This location information will be used for later restoration.
  • a platinum (Pt) layer was formed by irradiating a laser beam in a specific atmosphere, as shown in Fig. 22b, at the broken portion of the scanning signal line GL shown in Fig. 22a.
  • the wire is repaired by the connection layer jn of the Pt layer.
  • FIG. 23 is a schematic configuration diagram showing one embodiment of a device for repairing this disconnection.
  • Peruger 2 having a built-in XY stage 1, and this Peruger 2 has a microscope arranged opposite to the XY stage 1.
  • Microscope / laser barrel 3 is installed.
  • the X-Y stage 1 has a lower transparent glass substrate SUB 1 to be inspected for disconnection.
  • the processed surface of the lower transparent glass substrate SUB 1 can face the microscope / laser mirror 3 over the entire area.
  • the drive of the X—Y stage 1 is controlled by the XY stage controller 4 so that the position of the disconnection can be opposed to the microscope / laser tube 3 by inputting the above-mentioned position information. Note that in this case, whether or not the opposing surfaces are surely determined can be determined by using the microscope in the microscope / laser barrel 3.
  • the laser beam 6 from the laser source 5 is guided to the microscope / laser barrel 3 so as to irradiate a broken portion of the scanning signal line GL.
  • the laser beam 6. may be, for example, an Ar laser or a YAG laser.
  • the wavelength of the Ar laser is 0.55 / zm
  • the wavelength of the YAG laser is 1.55 jum (second harmonic: 0.53 ⁇ )
  • the power is about 20 O mW and the beam diameter is 5 to 1 ⁇ .
  • Perugia The 2 ⁇ has decreased to the earthenware pots by supplying a mixed gas composed of as a material gas 7 (P t C l 2) 2 (CO) a gas and A r gas.
  • a mixed gas composed of as a material gas 7 (P t C l 2) 2 (CO) a gas and A r gas.
  • the so-called annealing is performed by the laser beam 6 so that the formation region of the Pt layer is clean.
  • the laser beam 6 is scanned from one side to the other side of the scanning signal line existing with the disconnection region therebetween as shown in FIG. 30a. As a result, it was confirmed that the Pt layer jn was easily formed.
  • the repair is performed in the Pt layer, but the present invention is not limited to this.
  • Cr, Mo, W, etc. Is also good.
  • the material gas 7 is Cr
  • a similar effect can be obtained by directly drawing In or the like without using the laser beam 6, for example, by using a focused ion beam method.
  • Ammonia gas, silane gas, and nitrogen gas are introduced into a plasma CVD apparatus to provide a 200 OA-thick Si nitride film, and silane gas and hydrogen gas are introduced into a plasma CVD apparatus to form a film.
  • silane gas and hydrogen gas are introduced into a plasma CVD apparatus, and an N (+)-type amorphous Provide a Si film.
  • the disconnection of the scanning signal line GL is formed as shown in FIG. 22c.
  • a first conductive film d1 made of an ITO film having a thickness of 140 OA is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, thereby forming the top layer of the gate terminal GTM and the drain terminal DTM and the transparent layer.
  • the pixel electrode ITO 1 is formed.
  • a second conductive film d 2 made of Cr with a thickness of 600 OA is provided by sputtering, and Al-Pd, A 1 — Si with a thickness of 400 A are further provided.
  • a 1 -Si—Ti, A 1 -Si 1 Cu, etc., and a third conductive film d 3 is provided by sputtering.
  • the third conductive film d3 is etched with the same liquid as in step B, and the second conductive film d2 is etched with the same liquid as in step A, so that the video signal line DL, the source electrode SD1, and the drain are etched.
  • the inspection is performed in the same manner as described in the steps C and C, by bringing the probe into contact with the drain terminals electrically connected to both ends of each video signal line DL.
  • Fig. 24a to Fig. 24c show the restoration when it is discovered that a part of the video signal line DL is broken.
  • FIGS. 24a to 24c show, for example, cross sections taken along the line 22-22 in FIG.
  • the repair of the disconnection in Fig. 24b is performed in the same manner as shown in step C '.
  • the protective film PSV 1 is formed by selectively etching the Si nitride film by a photolithography technique using SF 6 as a dry etching gas.
  • the disconnection of the video signal line DL is formed as shown in FIG. 24c.
  • FIG. 25 shows a configuration in which the scanning signal line GL and the video signal line DL can be repaired by cutting a part of the video signal line DL when the video signal line DL is short-circuited.
  • FIG. 3 is a plan view of the intersection of the scanning signal line GL and the video signal line DL, and shows that part of FIG. 2 in greater detail.
  • the video signal line D L is configured such that, at the intersection with the scanning signal line G L, a through hole H J extending in the longitudinal direction is provided at the center.
  • the-portion of the video signal line DL including this location is also combined with the through hole HJ.
  • the video signal line DL of the other part is separated by the cut part shown by the symbol CUT in the figure.
  • the restoration can be achieved by using the video signal lines DL of other portions as they are.
  • FIGS. 27a to 27c are views showing such a process.
  • FIG. 27a is a cross-sectional view taken along the line 25-25 in FIG. 25.
  • a laser beam is irradiated to the portion CUT to be cut in FIG. 25, and as shown in FIG. 27b, the protective film PSV 1 and the third conductive film d 3, Cutting is performed by removing the second conductive film d2 and the N (+) type semiconductor layer d0.
  • the protective film PSV j is formed at the cut portion using the laser beam 6 in the same manner as in the process C ′.
  • SiH 4 + NH 5 + N 2 is selected as the material gas 7 shown in FIG.
  • the repair of the disconnection of the scanning signal line GL or the video signal line DL was performed after its formation, that is, before the protective film PSV or the like was deposited on the upper surface.
  • the method is not limited to this, and may be performed after the protective film PSV is applied.
  • connection layer jn is formed as shown in the step C ′ or the step H ′, and As shown in I ′, a protective film PSV j can be formed.
  • the sequential formation of the connection layer j n and the protective film PSV j can be performed by simply using the apparatus shown in FIG. 23 and exchanging the material gas 7 supplied to the peruger 2.
  • FIG. 26 is a diagram showing a method of white spot inspection.
  • the thin film transistor TFT is turned on by applying a pressure from the pulse power supply P to the good signal line GL, and each transparent TFT is turned on from the video signal line DL via the turned on thin film transistor TFT.
  • the voltage E is supplied to the surface element electrode ITO l, thereby damaging the load Q to the storage capacitor C add corresponding to each transparent pixel electrode ITO l.
  • the charge Q harmed to each storage capacitance element C add is sequentially read out by the galvanometer A by turning on the corresponding thin film transistor TFT.
  • the transparent pixel electrode ITO 1 of the pixel and the transparent pixel electrode ITO 1 The video signal line DL adjacent to the transparent pixel electrode ITO1 is repaired by electrically short-circuiting with the conductive material JN.
  • the protective film PSV1 in the region where the conductive material is to be formed is, for example, the second film. As shown in Fig. 7, removal is performed using laser light.
  • the pixel when a video signal is supplied via the video signal line DL connected to the pixel, the pixel is displayed as a so-called black point, and is displayed as a white point. Will be lost.
  • the repair based on the presence or absence of this white spot was performed after the formation of the protective film PSV1, but was performed before the formation of the protective film PSV1.
  • the present invention is also applicable to a liquid crystal display substrate on which the protective film PSV1 is not formed.
  • the short circuit with the transparent surface element electrode I TOl is not always limited to the video signal line DL, and the same effect can be obtained even with the good signal line GL.
  • FIG. 28a is a diagram showing a cross section of the storage capacitor element C add portion, and the same reference numerals as in FIG. 4 are used.
  • the figure shows an example in which the correction is performed after the formation of the protective film PSV 1.
  • the protective film PSV1 which is an insulator covering the other electrode PL1, the gate insulating film GI, the anodic oxide film AOF, and the insulator covering the transparent pixel electrode ITOl
  • the protective film PSV 1 is removed using a laser beam.
  • a conductive material JN is formed on the other exposed electrode PL1 and the transparent pixel electrode ITO1, and white spot correction is performed by a conduction process.
  • FIGS. 29a to 29c show modified examples of the electrical connection example using the conductive material JN.
  • the protective film PSV1 which is an insulator covering the other electrode PL1, the gate insulating film GI, the anodic oxide film AOF, and the conductive film d on the transparent pixel electrode ITO1, as shown in Fig. 29b. 3.
  • a conductive material JN is formed on the conductive films d3 and d2 on the exposed other electrode PL1 and the transparent surface element electrode ITO1, and the whiteness is obtained by the conduction treatment. Point correction is performed.
  • the method shown in FIGS. 29a to 29c is suitable when the thickness of the transparent pixel electrode ITO1 is thin, and the conductive material JN is surely transparent through the conductive films d3 and d2. It is electrically connected to the pixel electrode ITO 1.
  • the present invention is not limited to the embodiments described above, and various improvements can make it easier and more reliable to repair a broken wire.
  • connection layer jn is formed on the There is a problem in reliability.
  • the broken wire can be repaired with high reliability by scanning while avoiding the foreign matter as shown in Fig. 30b.
  • connection layer jn covers or contacts the adjacent transparent surface electrode ITO l.
  • point defects are less noticeable than line defects due to disconnection, the embodiment shown in FIG. 30b is very effective as a simple and reliable method for repairing a disconnection.
  • connection layer j n may be formed by scanning the laser beam 6 a plurality of times.
  • FIG. 31a shows an example in which the connection layer is formed by scanning the laser beam 6 a plurality of times.
  • the first scan forms the first connection layer jnl
  • the second scan multiplies the wiring (in this example, the video signal line DL) by jn1.
  • a second connection layer jn 2 is formed in a portion beyond the boundary. Therefore, according to the embodiment of FIG. 31a, as shown in FIG. 31b, by increasing the thickness of the connection layer jn of the step formed by DL, the connection layer jn is increased. To prevent wire breakage and improve reliability.
  • the shape of the peruger 2 that forms a space in which the material gas 7 reacts with the laser beam 6 is not limited to that covering the entire substrate SUB 1 as shown in FIG. A substrate that covers a part of the substrate SUB 1 may be used.
  • the part of the substrate SUB 1 It is only necessary to cover the part with Perja (2a, 2b, 2c), so it is easy to repair the disconnection, the device can be reduced in size, and the board can be inserted and removed entirely.
  • the feature is that it is easy to mass-produce.
  • the peruger 2 in order to maintain the airtightness inside the peruger 2, the peruger 2 is composed of a plurality of bells 2a, 2b, 2c, and a large number of spaces are provided between each peruger.
  • vacuum evacuation OUT
  • an inert gas 8 such as N 2 is supplied to maintain airtightness with the atmosphere.
  • a replaceable window 9 is provided at the inlet of the laser beam 6.
  • the material of the window 9 preferably has good transparency, and the embodiment shown in FIG. 32 uses quartz glass.
  • the film is formed also in the laser light inlet, and there is a problem that the transmittance of the inlet decreases during long use.
  • the quartz glass replaceable by making the quartz glass replaceable, the problem that the transparency of the quartz glass is reduced can be solved.
  • FIG. 33 is an explanatory diagram showing another embodiment of the restoration when a white spot occurs.
  • a protective film PSV1 was previously applied to all of the transparent pixel electrodes ITO in each pixel on the video signal line DL. 0 9
  • FIG. 33b is a cross-sectional view taken along line b—b in FIG. 33a.
  • a laser beam is irradiated from the lower transparent glass substrate SUB1 side, and as shown in Fig. 34b.
  • the protection film PSV 1 can be destroyed by the laser beam to connect the video signal line DL and the extension ex of the transparent element ITO 1. As a result, the white spot defect is corrected.
  • FIGS. 35a to 35c show still another embodiment.
  • FIG. 35b is a diagram showing a cross section of the lower transparent glass substrate SUB1 when the present invention is applied to a liquid crystal display panel having a structure in which the transparent pixel electrode ITO1 is provided below the gate insulating film GI. is there.
  • FIG. 35a shows a plan view in the case where the transparent pixel electrode ITO1 is provided with the extension eX
  • FIG. 35c shows a plan view in the case where the video signal line DL is provided with the extension eX.
  • the extended portion ex is irradiated with laser light 6 through the glass surface to dissolve the gate insulating film GI and the transparent pixel electrode ITO l as shown in 36b.
  • the transparent pixel electrode ITO 1 and the video signal line DL can be connected.
  • the laser beam 6 is radiated to the extension part eX through the lower transparent glass substrate SUB1 to perform the correction work, so that the white inspection and correction can be performed after the liquid crystal display panel is completed.
  • the white spot inspection can be performed to correct the defect.
  • the gate signal line GL may be connected to the extending part ex of the transparent pixel electrode IT01.
  • FIGS. 37a to 37b are diagrams showing an example in which the gate signal line GL is connected to the extending portion e X of the transparent pixel electrode ITO1.
  • the storage capacitor C ad d is used as the extension e X.
  • the laser beam 6 is applied to the extending portion e X from the lower transparent glass substrate SUB 1 side to perform a defect correction work.
  • the gate edge film GI and the anodic oxide film AOF are destroyed by the laser beam to connect the gate signal line GL and the extending part eX of the transparent pixel electrode ITO1.
  • FIG. 17 is an exploded perspective view showing each component of the liquid crystal display module MDL.
  • SHD is a frame-shaped shield case (metal frame) made of metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a pack light, and BLS is a back light.
  • the light support and the LCA are the lower case, and the respective members are stacked in the vertical arrangement as shown in the figure to assemble the module MDL.
  • the entire module MDL is fixed by claws CL and hooks FK provided on the shield case SHD.
  • the intermediate frame MFR is formed in a frame shape so that an opening corresponding to the display window L CW is provided, and the shape and thickness of the diffusion plate SPB, the back light support BLS, and various circuit components are formed in the frame portion. Irregularities and heat radiation openings are provided.
  • the lower case LCA also serves as a reflector for the backlight, and has a reflection peak RM corresponding to the fluorescent tube BL so as to efficiently reflect the light.
  • FIG. 18 is a top view showing a state where the video signal drive circuits He and Ho and the vertical scanning circuit V are connected to the display panel PNL shown in FIG. 5 and the like.
  • CHI is a drive IC chip for moving the display panel PNL (the lower three are drive IC chips for the vertical scanning circuit, and the six on the left and right are drive IC chips for the video signal drive circuit).
  • TCP is a tape carrier package or PCB in which the driving IC chip CHI is mounted by the tape-automated 'bonding method (TAB), as described later in Figs. 19 and 20.
  • Reference numeral 1 denotes a drive circuit board on which the above-described TCP, capacitor CDS, etc. are mounted, and is divided into three.
  • FGP is a frame ground pad, and panel-like pieces FG provided by cutting into the shield case SHD are soldered.
  • FC is the lower drive circuit This is a flat cable that electrically connects the printed circuit board PCB1 to the left drive circuit board PCB1 and the lower drive circuit board PCB1 to the right drive circuit board PCB1.
  • the flat cable FC is composed of a striped polyethylene layer and a striped polyethylene layer (tin bronze material plated with Sn) as shown in the figure. Use a vinyl alcohol layer that is supported by sandwiches between and.
  • FIG. 18 is a diagram showing the cross-sectional structure of the tape carrier package TCP that constitutes the scanning signal drive circuit V and the video signal drive circuits He and Ho and has the integrated circuit chip CHI mounted on a flexible wiring board.
  • FIG. 20 is a cross-sectional view of a main part of the liquid crystal display panel, showing a state where it is connected to a video signal circuit terminal DTM in this example.
  • TTB is an input terminal / wiring portion of the integrated circuit CHI
  • TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu.
  • the bonding pad PAD of the integrated circuit CHI is connected to the lead by the so-called face-down bonding method.
  • the outer ends of the terminals TTB and TTM correspond to the inputs and outputs of the semiconductor integrated circuit chip CHI, respectively, and are anisotropically connected to the CR TZ TFT conversion circuit and power supply circuit SUP by soldering or the like.
  • the package TCP covers the protective film PSV 1 whose tip end has exposed the connection terminal D TM on the panel PNL side.
  • the external connection terminal DTM (GTM) is covered with at least one of the protective film PSV1 and the package TCP, so that it is resistant to electric touch.
  • BF 1 and BF 2 are base films made of polyimide or the like, and SRS is a solder resist film for masking so that no extra solder is attached during soldering.
  • the wiring sections TTB and TTM are adhered to the base films BF1 and BF2 with an adhesive BIN.
  • the gap between the upper and lower glass substrates outside the seal part SL is cleaned and protected by epoxy resin EPX, etc., and between the package TCP and the upper substrate SUB 2 is further filled with silicone resin SIL to multiplex protection. ing.
  • the drive circuit board PCB2 of the liquid crystal display section LCD held and stored in the intermediate frame MFR has an L-shape as shown in FIG.
  • This drive circuit board PCB2 has a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from a single voltage source, and a CRT (cathode ray tube) from a host (upper processing unit).
  • SUP which includes a circuit that converts information for use into information for TFT liquid crystal display devices, is installed.
  • CJ is a connector connection part to which a connector (not shown) to be connected to the outside is connected.
  • Drive circuit board PCB 2 and inverter circuit board PCB 3 are intermediate frames by a back light cable. Through the connector hole provided in the MFR And are electrically connected.
  • the drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a bendable flat cable FC.
  • the drive circuit board PCB 2 is placed on the back side of the drive circuit board PCB 1 by bending the flat cable FC by 180 °, and is fitted into a predetermined recess of the intermediate frame MFR. .

Abstract

Substrat d'affichage à cristaux liquides, dans lequel un plan d'affichage est constitué de pixels disposés en matrice. La lumière qui traverse les pixels en cristaux liquides est atténuée selon des signaux vidéo fournis à des électrodes de pixel reliées par une ligne de drain à des dispositifs de commutation, lesquels sont activés par un signal de balayage venant d'une ligne de porte. Lorsque certains pixels n'atténuent pas la lumière parce qu'ils ne reçoivent pas de signal de balayage ou de signal vidéo, leurs électrodes sont connectées à la ligne de porte ou de drain adjacente, afin d'éliminer les défauts de points blancs.
PCT/JP1995/000509 1994-08-30 1995-03-20 Procede pour la production d'un dispositif d'affichage a cristaux liquide du type a matrice active WO1996007122A1 (fr)

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JP6/204990 1994-08-30
JP20499094 1994-08-30

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WO1996007122A1 true WO1996007122A1 (fr) 1996-03-07

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PCT/JP1995/000509 WO1996007122A1 (fr) 1994-08-30 1995-03-20 Procede pour la production d'un dispositif d'affichage a cristaux liquide du type a matrice active

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CN100343743C (zh) * 2003-06-24 2007-10-17 统宝光电股份有限公司 液晶显示器的激光修补方法与结构
JP2009105168A (ja) * 2007-10-22 2009-05-14 Omron Corp レーザ加工装置及びレーザ加工方法

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JPH03127325U (fr) * 1990-04-02 1991-12-20
JPH0416930A (ja) * 1990-05-11 1992-01-21 Sharp Corp アクティブマトリクス型表示装置
JPH0421823A (ja) * 1990-05-16 1992-01-24 Hosiden Corp 液晶表示素子の点欠陥の黒欠陥化法及び液晶表示素子
JPH04331923A (ja) * 1991-05-08 1992-11-19 Sharp Corp アクティブマトリクス表示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100343743C (zh) * 2003-06-24 2007-10-17 统宝光电股份有限公司 液晶显示器的激光修补方法与结构
JP2009105168A (ja) * 2007-10-22 2009-05-14 Omron Corp レーザ加工装置及びレーザ加工方法

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