Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
  • H04L27/22—Demodulator circuits; Receiver circuits
  • H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
  • H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/0014—Carrier regulation
  • H04L2027/0024—Carrier regulation at the receiver end
  • H04L2027/0026—Correction of carrier offset
  • H04L2027/0032—Correction of carrier offset at baseband and passband
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/0014—Carrier regulation
  • H04L2027/0044—Control loops for carrier regulation
  • H04L2027/0053—Closed loops
  • H04L2027/0057—Closed loops quadrature phase
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/0014—Carrier regulation
  • H04L2027/0044—Control loops for carrier regulation
  • H04L2027/0063—Elements of loops
  • H04L2027/0065—Frequency error detectors

Definitions

• the invention relates to a method for
• Reception synchronization of the type specified in the preamble of claim 1 and a device for carrying out the method Reception synchronization of the type specified in the preamble of claim 1 and a device for carrying out the method.
• Satellite channel interference is caused by time-variant satellite channel properties, among other things because communication between the satellite and the moving vehicle can take place.
• the frequency control alone is too imprecise for such a highly precise reception synchronization. Therefore, it is already known to provide a phase control in addition to the frequency control after filtering adapted to the signal in order to correct the remaining phase errors of the signal.
• the phase detection recognizes further frequency deviations, which are additionally fed back to the frequency control loop. It is already known from the prior art to digitize the received signal after the intermediate frequency demodulation and to generate an in-phase and a quadrature component of the received signal in the subsequent demodulation.
• phase locked loop the phase error remaining after the frequency control is determined and, on the one hand, the further demodulator is readjusted and, on the other hand, the frequency control circuit is controlled in order to compensate for the frequency deviations resulting from the remaining phase errors even in the frequency control loop.
• the object of the present invention is therefore to further improve the synchronization accuracy and speed and to reduce the outlay on circuitry.
• frequency detection is carried out using digital signal values.
• these signal values are first fed to a filter that is already optimally adapted to the signal shape and properties of the transmitted signals.
• signals are analyzed in the frequency detection which, by largely eliminating interference and eliminating undesired properties of the transmission channel, permit a substantially improved frequency determination for controlling the input demodulator.
• the system for reception synchronization is constructed in two stages and has a frequency and a phase locked loop, so that a quick phase synchronization in the phase locked loop takes place with a slight residual frequency offset after the frequency detection.
• the OQPSK signals used in this context are used by
• Signal recovery fed to a quadrature demodulation, which generates an in-phase signal and a quadrature signal from the input signal after IF mixing, which are phase-shifted by 90 ° or T / 2 with respect to one another, where T corresponds to the duration of the bit period.
• phase control loop In the phase control loop, the remaining phase errors are determined and corrected using the in-phase and quadrature samples. With such digital It is particularly advantageous for signal samples that they are always taken at the energy maximum for both signal components.
• This state is now set for the phase controller in that the signal components are shifted by T / 2 against each other and a QPSK signal (Quadrature Phase Shift Keying) is thus obtained from the OQPSK signal for control purposes.
• the phase controller then always works with an optimal S / N ratio. With the residual frequency shift determined from this phase error, on the one hand the complex digital demodulator of the phase locked loop, but also the frequency locked loop is controlled in order to achieve effective control of the carrier frequencies of the receive modulators over the entire receiving system.
• Reception synchronization is brought about by the simple combination of a comparatively time-consuming frequency control with a fast phase control.
• this control loop is interrupted.
• the phase detector generates, in addition to a proportional signal component for fast phase control within the phase-locked loop, also an integral signal component that changes with a larger time constant in order to also adjust the carrier frequency of the NCO oscillator in the frequency control loop. Accordingly, it is not the frequency control loop that is decisive, but the fast phase control for the speed of the reception synchronization.
• This measure is further supported by the fact that there are no integrating, time-delaying low-pass filters, for example the waveform filter for interference suppression, in the phase-locked loop. The interference is cleared before Phase synchronization.
• FIG. 3 block diagram of a clock generator.
• the reception signal is received via an antenna 10 and fed to a frequency control loop via an IF demodulator 20.
• an in-phase and a quadrature signal are formed from the received signal by demodulation with a controllable carrier frequency signal. Only then is the respective signal components digitized, which can therefore be carried out with a higher frequency constancy in the baseband position.
• the digitized received signals are then filtered in a form filter 140 which is adapted to the signal behavior of the transceiver system, and only with the filtered signal components is frequency detection carried out on the one hand and phase detection in the downstream phase-locked loop on the other hand.
• phase and frequency synchronism In frequency detection, digital means by FFT (Fast Fourier Transformation) and iterative frequency determination are used to generate the Carrier frequency signal determines the necessary frequency value and thereby achieved that the carrier frequency can be set on average to within ⁇ 10 Hz. Since undisturbed signal processing and exact detection of the information impressed on the signal is not yet possible with this frequency detection and presetting of the carrier frequency, the actual phase and frequency synchronism must be achieved and maintained in the following phase locked loop 200.
• FFT Fast Fourier Transformation
• the output signal of the frequency control loop 100 is an OQPSK signal due to the transmission-side modulation method, i. H. the in-phase and quadrature components of the digital signal are out of phase by T / 2 and 90 °, respectively.
• This OQPSK signal is first demodulated in a complex manner in the phase locked loop 200 and converted into a QPSK signal by a T / 2 delay of the one signal component, so that the phase detection is carried out with these signal components which are time-shifted with respect to one another. Since the interference ratio in the bit maximum between sample values of the signal components of the QPSK signal is the lowest, the residual phase error is determined reliably and much more accurately from these in-phase and quadarature signal values. With this residual phase error, the carrier signal for the complex demodulation in the input of the phase locked loop is then readjusted.
• the QPSK signal analyzed during phase detection is decoupled for subsequent signal processing and information acquisition, which, like the OQPSK signal, is completely frequency and phase synchronous in the two-stage synchronization process by frequency and phase control. is coherently demodulated.
• a receiving device in which the antenna 10 is connected to an IF demodulator 20, which mixes the high-frequency received signal down into an IF frequency range.
• the IF demodulator 20 is generally constructed in several stages in order to convert signals from the GHz range into the kHz range.
• the IF demodulator 20 is connected to an analog demodulator 130 in the frequency control loop, the carrier frequency of which is generated by a controlled oscillator 131.
• the regulated oscillator 131 is implemented as an NCO (numeric controlled oscillator).
• NCO numeric controlled oscillator
• its carrier frequency should deviate from the carrier of the last IF stage by a maximum of ⁇ 1.5 kHz.
• the analog demodulator 130 is then followed by a two-channel analog low-pass filter 132 for eliminating the upper sidebands of the complex signal components generated during the modulation.
• the low-pass filter 132 acts as an anti-aliasing filter for the following two-channel A / D converter 135.
• a shape filter 140 is also connected, which is connected on the one hand to the phase control loop 200 and on the other hand to a data reduction stage 151.
• the digital form filter 140 for interference suppression is an FIR filter (finite Impulse Response) and especially adapted by appropriate selection of its coefficients to the properties of the transmitted signal and the transmission channel. Due to its low-pass character, it affects the synchronization speed and is therefore upstream of the phase synchronization, but not included in the phase-locked loop.
• the sampling rate of the in-phase and quadrature components is reduced by a factor of 4, for example, so that the frequency detector 150 connected downstream only has to process a reduced data sequence in order to detect the frequency offset of the complex signal, as will be explained below with reference to FIG 2 is explained.
• the frequency detector 150 is connected on the output side via the summer 160 to the oscillator 131, which in turn can be controlled with the corresponding digital carrier frequency values.
• the second input of the summing stage 160 is connected to the phase-locked loop, so that the frequency shifts detected in the phase-locked loop 200 are taken into account for the precise frequency setting or control of the oscillator 131.
• the frequency detection is interrupted after the initial carrier frequency value is determined and the oscillator 131 is preset. The synchronization speed is then no longer determined by the more time-consuming frequency detection, but by a fast phase detection and a particularly fast reception synchronization is guaranteed.
• a complex demodulator 210 which is connected to the output of the form filter 140 in the frequency control loop, forms the input of the phase locked loop.
• the feedback loop of the phase locked loop is essentially through a delay circuit 215, the phase detector 230 and the
• the digital control generator 250 which can be controlled by the phase detector 230, is closed, the control generator 250 already providing the complex signal required for the complex mixing in the demodulator 210 and thereby effecting the remaining phase and frequency correction.
• a clock generator 220 is connected to the outputs of the delay circuit 215 in order to generate a clock signal coupled to the data clock f ⁇ o in a phase- locked manner . It is connected on the output side to the A / D converter 135, so that the digitization of the input signal already takes place at a sampling rate adapted to the data clock f ⁇ o . It is also connected to a reduction circuit 216, which is connected upstream of the phase detector 230, in order to ensure that the data values are sampled at the bit maximum and thus signal evaluation at the energy maximum even when the sampling rate is reduced for the phase detector.
• the decoupling of the synchronized complex signal, i. H. of the in-phase and quadrature components from the phase-locked loop takes place after the delay circuit 215.
• the QPSK signal which is reduced in the sampling rate, is thus transmitted as an optimally synchronized signal for the further data and signal processing for information acquisition.
• FIG. 2 shows a more detailed illustration of the frequency detector 150, which despite the usually high computing effort ensures comparatively fast frequency detection, not least by a particularly effective iteration method.
• Those transmitted by the data reduction stage 151 in FIG. 1 Complex scan data are transmitted to an FFT module 152, which has an FFT memory 153 for this.
• This FFT memory 153 is followed by a complex FFT computer 154 for calculating the complex Fast Fourier Transform (FFT) from the stored samples.
• the amount spectrum, the maximum spectral value of which can be determined in the downstream maximum detector 156, is formed in an amount calculator 155.
• the frequency value of the maximum spectral value can be used to control an iterative frequency calculator 157 which, after being released by the CW detector 158, determines the frequency correction ⁇ f for readjusting the oscillator 131 in an iteration process by means of the sample values stored in the FFT memory 153 and the maximum spectral value.
• the frequency correction ⁇ f can be calculated using the following short program sequence.
• the upper limit I for the iteration depends on the number N of the FFT spectral values.
• the CW detector 158 is required for the signal. This is because the transmit and thus also the receive signal consist of OQPSK-modulated data signal parts and short burst parts, which are CW-modulated and added to the information parts solely for the purpose of synchronization. At the beginning of Synchronization must therefore primarily detect these CW components in order to activate the control loop, ie in this case the iterative frequency calculator 157.
• the FFT detector 152 is connected on the output side to an adder 159, so that on the one hand the frequency correction ⁇ f and on the other hand an estimated base frequency f e are added.
• the output frequency f oe of the adder 159 likewise forms the output value of the frequency detector 150 for controlling the summer 160 according to FIG. 1.
• the phase detector 230 has a phase controller 231 designed as a Costas controller with a downstream PI controller 232 (proportional-integral controller).
• PI controller 232 proportional-integral controller
• the in-phase and quadrature components of the pending QPSK signal are multiplied crosswise by a sign function of the other component.
• the phase difference A ⁇ of the in-phase and quadrature components then results from the difference between the products.
• This phase difference A ⁇ forms the input signal for the PI controller 232, the sum frequency f c of which is used with a proportional frequency component f cp and an integral frequency component f ci as the output signal of the phase detector 230 for controlling the digital control generator 250.
• the integral frequency component f ci is transmitted to the summer 160 via a further output, so that slow frequency changes which vary the integral frequency component f ci are already effective for the oscillator 131 and influence the primary frequency control.
• the regulated sum frequency f c determined in the phase detector 230 is then converted into a phase value ⁇ and converted with the aid of a sine / cosine computing device into the carrier signals required for phase-synchronous demodulation in the complex demodulator 210.
• the demodulator 210 has digital multipliers and summers, the representation of which is known and therefore can be dispensed with here.
• the clock generator 220 is driven with the QPSK signal.
• An energy value determination of the in-phase and quadrature signal components takes place in a squaring stage 221.
• the first and third digits are tapped from the downstream four-stage register 222, the difference A ⁇ ⁇ at the output of the subtractor 223 controlling a clock controller 225.
• the clock controller 225 is implemented as a PI controller, the output-side sum of the proportional and integral frequency components forms a frequency change ⁇ f ⁇ and adds the clock frequency to the data clock f ⁇ o
• the frequency f ⁇ o is the basic frequency for the sampling clock signal derived from the data clock of the system.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

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• 1993
  • 1993-10-15 DE DE19934335228 patent/DE4335228C2/de not_active Expired - Fee Related
• 1994
  • 1994-09-29 TW TW83108988A patent/TW247384B/zh active
  • 1994-10-08 WO PCT/EP1994/003324 patent/WO1995010909A1/de not_active Ceased

Patent Citations (3)

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