WO1995010122A1 - Halbleiterbauelement mit hoher durchbruchsspannung - Google Patents
Halbleiterbauelement mit hoher durchbruchsspannung Download PDFInfo
- Publication number
- WO1995010122A1 WO1995010122A1 PCT/EP1994/003266 EP9403266W WO9510122A1 WO 1995010122 A1 WO1995010122 A1 WO 1995010122A1 EP 9403266 W EP9403266 W EP 9403266W WO 9510122 A1 WO9510122 A1 WO 9510122A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor
- dielectric layer
- semiconductor component
- substrate
- zone
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 230000015556 catabolic process Effects 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000000903 blocking effect Effects 0.000 claims abstract description 8
- 230000005684 electric field Effects 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 229910005091 Si3N Inorganic materials 0.000 claims description 2
- 230000007423 decrease Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 5
- -1 cesium ions Chemical class 0.000 claims 4
- 239000000203 mixture Substances 0.000 claims 2
- 229910052796 boron Inorganic materials 0.000 claims 1
- 229910052792 caesium Inorganic materials 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 229910052740 iodine Inorganic materials 0.000 claims 1
- 239000011630 iodine Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Definitions
- the invention relates to a semiconductor component with at least one lateral semiconductor structure having a high breakdown voltage, comprising a substrate, a dielectric layer adjacent to the substrate, a lightly doped semiconductor zone arranged on the dielectric layer and with heavily doped semiconductor zones of the semiconductor component protrude into the lightly doped semiconductor zone from the surface of the semiconductor component.
- Such a semiconductor structure is from the article "Extension of the Resurf Principle to Dielectrically Isolated Power Devices" of the conference report Conf. Report. ISPSD 1991, Baltimore, pages 27-30. This is the typical structure of a lateral diode on a dielectric isolated substrate. Structures of this type, which can be assigned to the general term “smart power technology”, represent a link between digital controls and power components. This technology enables the integration of logic, protection and diagnostic functions in power components.
- An essential aspect of the technology mentioned is to integrate a plurality of power components on a so-called semiconductor wafer, which will be referred to in the following only as a semiconductor, the individual components being completely insulated from one another.
- the common arrangement of logic circuits and power components in one chip is described in the article "Impact of Dielectric Isolation Technology on Power ICs" of the conference report Conf. Report ISPSD 1991, Baltimore, pages 16-21.
- the insulation required in the case of a plurality of components is to be carried out in such a way that the respective component is electrically insulated on all sides with respect to the other adjacent semiconductor regions.
- the lateral insulation is usually carried out in such a way that trenches are etched around the component, which are then filled with a dielectric.
- the dielectric insulation parallel to the surface of the semiconductor, ie in the vertical direction, is carried out either by the formation of a pn junction loaded in the reverse direction or by using a dielectric, such as. B. silicon oxide.
- a dielectric such as. B. silicon oxide.
- dielectrically insulated semiconductor wafers consisting of a substrate, a dielectric layer adjacent to the substrate and a semiconductor zone arranged thereon.
- semiconductor wafers produced with direct connection technology are best suited for high-voltage components, since they ensure the best material properties of the semiconductor zone arranged on the dielectric layer.
- the maximum blocking voltages or breakdown voltages of the components achieved on electrically insulated semiconductor wafers are determined, on the one hand, by the insulating ability of the “buried dielectric” and, on the other hand, by the surface properties in the surface areas in which the pn junctions appear on the surface. To avoid a surface breakthrough, so-called field plates are used in the area of the pn junctions on the surface.
- the voltage breakdown is mainly limited by the fact that the entire voltage is built up between the generally grounded substrate and the high-potential, highly doped regions of the semiconductor components, which leads to high field strengths.
- the increase in the thickness of the semiconductor zone arranged on the dielectric layer leads to considerable difficulties for increasing the breakdown voltage, since with increasing thickness the effort for the lateral insulation by separating etching and subsequent filling with insulation material becomes difficult.
- the thickness of the buried dielectric cannot be made arbitrarily large, since otherwise an insufficient dissipation of the power loss must be accepted due to the insufficient thermal conductivity, which generally leads to thermal problems for the achievable parameters and the operation of the Leads components.
- thicknesses of the dielectric layer in the range from 0.5 to 4.5 ⁇ m have proven to be still usable.
- Another known measure for achieving higher breakdown voltages is the introduction of buried dopants at the interface with the dielectric layer, as can be seen from the patent specification DE-C2 38 06 164. This measure is shown there in FIG. 2. This results in a somewhat more favorable potential distribution in the components; nevertheless, the increase in breakdown voltage is relatively small and also depends on the thickness of the dielectric layer. The maximum reported breakdown voltage is 600 V for a silicon layer thickness of 20 ⁇ m. This is not sufficient for different areas of application. Another measure for achieving higher breakdown voltages is described in the article "Influence of the Backgate-Voltage on the Breakdown-Voltage of SOI Power Devices", Electrochemical Society Proceedings, Vol. 92-7, 1992, pp. 427-432.
- a particularly favorable potential distribution in the components and thus a significant increase in the breakdown voltage is achieved by applying a potential to the substrate that lies between the values of the source and drain potentials.
- the disadvantages of this measure are that the grounding of the substrate, which is required for many applications, cannot be maintained, and that the substrate potential affects all components integrated in the lightly doped semiconductor layer.
- a semiconductor structure that has higher breakdown voltages with the same or a smaller thickness of the semiconducting layer would be advantageous.
- the other component properties should not be affected.
- the invention has for its object to provide a semiconductor device having at least one semiconductor structure in which a sufficient 'high breakdown voltage can be realized even with a thin semiconductor layer in a technologically simple manner. At the same time, the introduction of additional recombination generation centers should be avoided.
- a further semiconductor zone includes, in particular, a first semiconductor zone which has a first conductivity type with a higher impurity concentration than the low-doped semiconductor zone, and a second semiconductor zone which has a impurity concentration which is higher than that of the second conductivity type Drift zone and which is outside the first semiconductor zone.
- Such an arrangement forms a diode.
- a blocking voltage of the diode which is positive with respect to the substrate potential
- positive charges are expediently stored in the dielectric layer and are laterally homogeneously arranged at least in the region between the first and the second semiconductor zone.
- the semiconductor structure can be designed in such a way that the first and second semiconductor zones extend as far as the dielectric layer or are at a distance therefrom.
- the (positive) charges in the dielectric layer are arranged at least in the region between the first and second semiconductor zones in such a way that their concentration is highest below the semiconductor zone with the greatest potential difference with respect to the substrate decreases laterally with increasing distance.
- 1 shows a conventional semiconductor structure with a diode and a lateral separation structure
- 2 shows a conventional semiconductor structure with a diode with a higher breakdown voltage and a lateral separation structure
- 3 shows a semiconductor structure with a first embodiment of a diode and with laterally homogeneously distributed fixed charges in the dielectric layer in cross section
- Fig. 4 shows a semiconductor structure with a second embodiment of a
- FIG. 6 a semiconductor structure with a second embodiment of a
- the arrangement shown in FIG. 1 consists of a semiconductor structure 1 formed by connection of a silicon substrate 1 a and an n-Si substrate 1 b according to the direct connection technique, with an oxide film 2 produced at the connection interface 3, hereinafter also dielectric Called Layer 2.
- part of the n-substrate 1b is etched as a trench at least as far as the oxide film 2, so that an island-shaped n-layer 4 is formed.
- the trench is filled by an oxide film 5 and by a layer of polycrystalline silicon 6.
- n-layer 4 there is a p + layer 8, surrounded by a p-layer 9, so that a diode is formed.
- n + layer 10 is produced in a surface part of the n layer for better contactability. Since the potential at the substrate 1 a is normally set to 0 V and since the thin oxide film has a relatively high dielectric constant, the major part of the reverse voltage applied to the diode lies in the depletion layer below the n + layer 10 Distribution of the electric field is described in DE-C2 38 06 164 in the article "Impact of Dielectric Isolation Technology on Power ICs" of the conference volume Conf. Report ISPSD 1991, Baltimore, pages 16-21.
- the diode arrangement shown in FIG. 2 according to DE-C2 38 06 164 is constructed similarly to that shown in FIG. 1, only here there is additionally an n-doped zone 7a on the bottom portion of the Si layer 4 and a highly doped zone 7b on Scope of layer 4 is formed.
- a suitable doping of these layers when a reverse bias voltage of the diode is applied, the layer 7a is depleted on the base section, a potential difference being generated in the lateral direction which divides the voltage between the electrodes A and K, as a result of which part of the applied voltage is Oxide film 2 is recorded.
- the potential difference generated in the lateral direction is limited, however, by the fact that as the doping concentration in layer 7a increases, complete depletion will soon no longer occur and the electric field below zone 8 will rise rapidly.
- zone 7a must be manufactured before the component structure is produced (zones 5, 6, 7b, 8, 9 and 10), and therefore the permissible process temperatures have to be restricted. Otherwise, zone 7a diffuses to an impermissible depth.
- the invention can also be used for all other unipolar and bipolar components.
- the doping n and p of the examples can be interchanged.
- the components do not have to be designed symmetrically, a lateral isolation by trench can also be made.
- the arrangement shown in FIG. 3 consists of a semiconductor structure 1 formed by the connection of a silicon substrate 1 a and an n-doped substrate 1 b according to the direct connection technique with a dielectric layer 4 produced on the surface 3 of the Si substrate 1 a, for example an oxide layer, and the overlying n-layer 1 b.
- a dielectric layer 4 produced on the surface 3 of the Si substrate 1 a, for example an oxide layer, and the overlying n-layer 1 b.
- the dielectric layer 4 laterally homogeneously fixed positive charges are present in a layer 5, for example introduced by ion implantation before the direct connection process.
- the first semiconductor zone is a p + layer 6, so that a diode is formed.
- an n + -layer 7 is formed separately from the p + layer 6 as the second semiconductor zone for better contacting.
- the semiconductor surface is protected by an oxide layer 8.
- the p + layer 6 is contacted as the anode A, the n + layer 7 as the cathode.
- the full potential difference between the n + layer 7 and the surface 3 of the Si substrate 1a builds up when the substrate is grounded.
- the positive charges 5 cause a voltage drop verti cal in the dielectric layer 4, so that the electric field strength in the n-layer 1 b below the n + layer 7 is reduced.
- the arrangement shown in FIG. 4 differs from the arrangement according to FIG. 3 in that the p + layer 6 and the n + layer 7 extend to the dielectric layer 4.
- the voltage drop below the cathode is practically completely shifted into the dielectric layer 4.
- the positive charges 5 at the same time bring about a reduction in the electric field strength at the curvature of the n + layer 7, as a result of which a significant increase in the breakdown voltage is achieved.
- the arrangement shown in FIG. 5 differs from the arrangement according to FIG. 3 shows that the concentration of the positive charges 5 in the dielectric layer 4 is highest below the n + layer 7 and lowest below the p + layer 6. In this embodiment, it is achieved that a high voltage difference is recorded in the dielectric layer 4 below the n + layer 7 without the potential in the n layer 1 b below the p + layer 6 simultaneously increasing. In this way, a particularly advantageous potential distribution in the n-layer 1 b can be achieved.
- the arrangement shown in FIG. 6 differs from the arrangement according to FIG. 5 in that the p + layer 6 and the n + layer 7 extend to the dielectric layer 4. In this embodiment, the voltage drop below the cathode is practically completely shifted into the dielectric layer 4 in the blocking mode.
- the lateral distribution of the positive charges 5 allows the lateral field strength profile in the n-layer 1 b to be predetermined, so that almost ideal conditions for the breakdown voltage of the diode can be achieved.
- the existence of the fixed positive charges influences negative charge carriers in the n-layer 1 b, which at the same time leads to a desired reduction in the forward resistance.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7510606A JPH09503348A (ja) | 1993-10-01 | 1994-09-30 | 高い降伏電圧を有する半導体素子 |
DE59407460T DE59407460D1 (de) | 1993-10-01 | 1994-09-30 | Halbleiterbauelement mit hoher durchbruchsspannung |
EP94929506A EP0721665B1 (de) | 1993-10-01 | 1994-09-30 | Halbleiterbauelement mit hoher durchbruchsspannung |
US08/619,614 US5767548A (en) | 1993-10-01 | 1994-09-30 | Semiconductor component with embedded fixed charges to provide increased high breakdown voltage |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEP4333661.2 | 1993-10-01 | ||
DE4333661A DE4333661C1 (de) | 1993-10-01 | 1993-10-01 | Halbleiterbauelement mit hoher Durchbruchsspannung |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1995010122A1 true WO1995010122A1 (de) | 1995-04-13 |
Family
ID=6499282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1994/003266 WO1995010122A1 (de) | 1993-10-01 | 1994-09-30 | Halbleiterbauelement mit hoher durchbruchsspannung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5767548A (de) |
EP (1) | EP0721665B1 (de) |
JP (1) | JPH09503348A (de) |
DE (2) | DE4333661C1 (de) |
WO (1) | WO1995010122A1 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3460170B2 (ja) * | 1997-02-03 | 2003-10-27 | シャープ株式会社 | 薄膜トランジスタ及びその製造方法 |
DE10127952A1 (de) * | 2001-06-08 | 2002-12-19 | Infineon Technologies Ag | Laterale PIN-Diode und Verfahren zur Herstellung derselben |
FR2830123A1 (fr) * | 2001-09-26 | 2003-03-28 | St Microelectronics Sa | Peripherie haute tension |
US7494901B2 (en) * | 2002-04-05 | 2009-02-24 | Microng Technology, Inc. | Methods of forming semiconductor-on-insulator constructions |
JP2007273919A (ja) * | 2006-03-31 | 2007-10-18 | Nec Corp | 半導体装置及びその製造方法 |
US8564057B1 (en) | 2007-01-09 | 2013-10-22 | Maxpower Semiconductor, Inc. | Power devices, structures, components, and methods using lateral drift, fixed net charge, and shield |
JP5479915B2 (ja) | 2007-01-09 | 2014-04-23 | マックスパワー・セミコンダクター・インコーポレイテッド | 半導体装置 |
JP2010114409A (ja) * | 2008-10-10 | 2010-05-20 | Sony Corp | Soi基板とその製造方法、固体撮像装置とその製造方法、および撮像装置 |
US9119655B2 (en) | 2012-08-03 | 2015-09-01 | Stryker Corporation | Surgical manipulator capable of controlling a surgical instrument in multiple modes |
CN102194832A (zh) * | 2011-05-16 | 2011-09-21 | 重庆大学 | 具有界面横向变掺杂的soi耐压结构 |
CN102760753B (zh) * | 2012-07-26 | 2014-12-10 | 中国电子科技集团公司第二十四研究所 | 一种具有界面n+层的soi ldmos半导体器件 |
CN107198567B (zh) | 2012-08-03 | 2021-02-09 | 史赛克公司 | 用于机器人外科手术的系统和方法 |
US9226796B2 (en) | 2012-08-03 | 2016-01-05 | Stryker Corporation | Method for detecting a disturbance as an energy applicator of a surgical instrument traverses a cutting path |
US20140124893A1 (en) * | 2012-11-02 | 2014-05-08 | Infineon Technologies Ag | Varactor Diode, Electrical Device and Method for Manufacturing Same |
CN104505403A (zh) * | 2015-01-28 | 2015-04-08 | 桂林电子科技大学 | 一种具有介质层固定电荷的soi功率器件 |
EP3554414A1 (de) | 2016-12-16 | 2019-10-23 | MAKO Surgical Corp. | Techniken zur modifizierung der werkzeugbedienung in einem chirurgischen robotischen system auf basis des vergleichs von gegenwärtigen und befohlenen zuständen des werkzeugs in bezug auf eine operationsstelle |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4037243A (en) * | 1974-07-01 | 1977-07-19 | Motorola, Inc. | Semi conductor memory cell utilizing sensing of variations in PN junction current conrolled by stored data |
EP0213972A1 (de) * | 1985-08-30 | 1987-03-11 | SILICONIX Incorporated | Verfahren zum Ändern der Schwellspannung eines DMOS Transistors |
DE3806164A1 (de) * | 1987-02-26 | 1988-09-08 | Toshiba Kawasaki Kk | Halbleiterbauelement mit hoher durchbruchspannung |
EP0335741A2 (de) * | 1988-03-31 | 1989-10-04 | Kabushiki Kaisha Toshiba | Halbleitersubstrat mit dielektrischer Isolierung |
EP0452829A2 (de) * | 1990-04-16 | 1991-10-23 | Digital Equipment Corporation | Halbleiteranordnung mit verringten zeitabhängigen dielektrischen Fehlern |
-
1993
- 1993-10-01 DE DE4333661A patent/DE4333661C1/de not_active Expired - Fee Related
-
1994
- 1994-09-30 US US08/619,614 patent/US5767548A/en not_active Expired - Fee Related
- 1994-09-30 WO PCT/EP1994/003266 patent/WO1995010122A1/de active IP Right Grant
- 1994-09-30 DE DE59407460T patent/DE59407460D1/de not_active Expired - Fee Related
- 1994-09-30 JP JP7510606A patent/JPH09503348A/ja active Pending
- 1994-09-30 EP EP94929506A patent/EP0721665B1/de not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4037243A (en) * | 1974-07-01 | 1977-07-19 | Motorola, Inc. | Semi conductor memory cell utilizing sensing of variations in PN junction current conrolled by stored data |
EP0213972A1 (de) * | 1985-08-30 | 1987-03-11 | SILICONIX Incorporated | Verfahren zum Ändern der Schwellspannung eines DMOS Transistors |
DE3806164A1 (de) * | 1987-02-26 | 1988-09-08 | Toshiba Kawasaki Kk | Halbleiterbauelement mit hoher durchbruchspannung |
EP0335741A2 (de) * | 1988-03-31 | 1989-10-04 | Kabushiki Kaisha Toshiba | Halbleitersubstrat mit dielektrischer Isolierung |
EP0452829A2 (de) * | 1990-04-16 | 1991-10-23 | Digital Equipment Corporation | Halbleiteranordnung mit verringten zeitabhängigen dielektrischen Fehlern |
Non-Patent Citations (1)
Title |
---|
Y.S. HUANG ET AL.: "Extension of RESURF principle to dielectrically isolated power devices", PROCEEDINGS OF THE 3RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, April 1991 (1991-04-01), BALTIMORE, US, pages 27 - 30 * |
Also Published As
Publication number | Publication date |
---|---|
JPH09503348A (ja) | 1997-03-31 |
US5767548A (en) | 1998-06-16 |
DE4333661C1 (de) | 1995-02-16 |
EP0721665A1 (de) | 1996-07-17 |
DE59407460D1 (de) | 1999-01-21 |
EP0721665B1 (de) | 1998-12-09 |
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