WO1994029714A1 - Procede et appareil pour traiter les signaux d'un detecteur de defauts par ultrasons - Google Patents
Procede et appareil pour traiter les signaux d'un detecteur de defauts par ultrasons Download PDFInfo
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- WO1994029714A1 WO1994029714A1 PCT/JP1994/000916 JP9400916W WO9429714A1 WO 1994029714 A1 WO1994029714 A1 WO 1994029714A1 JP 9400916 W JP9400916 W JP 9400916W WO 9429714 A1 WO9429714 A1 WO 9429714A1
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- echo
- echo signal
- ultrasonic
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
- G01N29/449—Statistical methods not provided for in G01N29/4409, e.g. averaging, smoothing and interpolation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/36—Detecting the response signal, e.g. electronic circuits specially adapted therefor
- G01N29/38—Detecting the response signal, e.g. electronic circuits specially adapted therefor by time filtering, e.g. using time gates
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
- G01N29/46—Processing the detected response signal, e.g. electronic circuits specially adapted therefor by spectral analysis, e.g. Fourier analysis or wavelet analysis
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2291/00—Indexing codes associated with group G01N29/00
- G01N2291/04—Wave modes and trajectories
- G01N2291/044—Internal reflections (echoes), e.g. on walls or defects
Definitions
- the present invention relates to an ultrasonic detection and detection apparatus that transmits an ultrasonic pulse to an object and detects a defect existing in the object by analyzing an echo signal detected from the object.
- the present invention relates to a signal processing method and a signal processing device for once converting a high-frequency echo signal into a digital signal and then reducing the noise of the digital signal.
- the ultrasonic flaw detector is configured as shown in Fig. 25.
- Ultrasonic wave transmission and reception unit 1 sends a pulse signal to the probe 3 attached through a delay material such as direct or water into the subject 2 such as steel material in a constant period T Q.
- the probe 3 converts the received pulse signal into an ultrasonic pulse a and applies it to the subject 2 as shown in FIG.
- the ultrasonic pulse a applied to the subject 2 is reflected by the bottom surface 2 a of the subject 2 and is received again by the probe 3.
- the probe 3 converts the reflected wave into an electric signal and transmits the electric signal to the ultrasonic transmission / reception unit 1.
- the ultrasonic transmission / reception unit 1 amplifies the electric signal and sends it to the signal processing device 4 as an echo signal b.
- the echo signal b includes a bottom (B) echo 5 a corresponding to the reflected wave of the bottom 2 a and a defect (F) echo 5 b caused by the defect.
- the frequency f of the ultrasonic pulse a is embedded in the probe 3. It is determined by the thickness of the ultrasonic transducer being used.
- the frequency f of the ultrasonic pulse a used for flaw detection is several MHz to several tens of MHz, so the frequency range of the signal waveform of the bottom echo 5 a and the defect echo 5 b included in the echo signal b is 0 BZ to It is a wide range of more than a dozen MHZ.
- the signal processing device 4 performs various signal processing on the echo signal b received from the ultrasonic transmission / reception unit 1, and displays the signal processing result and the presence or absence of a defect on the display unit 6.
- the signal processing device 4 is supplied with the trigger signal c synchronized with the pulse signal from the ultrasonic transmission / reception unit 1 in order to perform signal processing on the echo signal and display the echo signal.
- the echo signal b output from the ultrasonic transmission / reception unit 1 includes many noises in addition to the bottom echo 5a and the defect echo 5b. If the noise contained in this echo signal a is large, the reliability of the flaw detection result will be greatly impaired. This noise is roughly divided into two types: electrical noise and material noise.
- Electrical noise is caused by external noise caused by electromagnetic waves entering the probe 3, the ultrasonic transmission / reception unit 1, the connection cable, and the like, and the internal noise generated by the amplifier incorporated in the ultrasonic transmission / reception unit 1. It is composed of noise, etc.
- ultrasonic waves propagating in the subject 2 are scattered at the crystal grain boundaries of the material.
- the scattered ultrasonic waves are received by the probe 3.
- the echo signal b output from the probe 3 includes the received scattered ultrasonic wave or scattered echo. This scattered echo is Material noise.
- an analog filter has been used to reduce noise components included in the echo signal b.
- BPF bandpass, filter
- LPF low-pass filter
- BPF bandpass filter
- LPF low-pass filter
- BPF low-pass filter
- the noise component included in the echo signal b can be reduced to a certain level or less.
- the frequency distribution of the defect echo changes depending on the ultrasonic attenuation characteristics of the subject 2. Therefore, when using BPF for material noise typified by scattered echo and the like, it is desirable to use a filter having optimal characteristics according to the subject 2.
- a digital signal processing method has been proposed to eliminate such inconveniences. That is, the echo signal b output from the ultrasonic transmission / reception unit 1 is subjected to AZD conversion. And digital signals The noise component is removed using a digital filter for the converted echo signal.
- the FIR (finite impulse response) digital filter can freely change the pass characteristics, so by setting the pass frequency characteristics according to the material of the subject 2, the optimal noise reduction processing for the echo signal b Can be applied.
- the echo signal a in order for the echo signal a to be subjected to digital signal processing in the above-mentioned high-frequency steps of several MHz to several tens of MBz, it is necessary to directly perform AZD conversion of this high-frequency echo signal b. Since the echo signal b has a wide frequency distribution of 0 H z ⁇ dozen MH z, at least from the sump-ring theorem must be A / D-converted 2 0 MH z or more sampling frequency f s is there. Furthermore, it is necessary to perform arithmetic processing for each sampling data sequentially created by the high-sampling frequency f s.
- the digital signal is input / output at the same timing as the sampling frequency of the arithmetic element, and the signal processing operation is performed continuously, so the operation time is longer than the repetition period of the ultrasonic pulse a. It will not be.
- the frequency of the forest echo is not significant difference between the frequency of the forest echo and the frequency of the defective echo, and if the frequency discrimination method including the digital filter described above cannot completely remove the forest echo There is.
- the frequency of the pseudo echo and the frequency of the defect echo are basically the same, so that the frequency echo cannot be removed as in the case of the forest echo. That is, there was no method for effectively removing the pseudo echo.
- a first object of the present invention is to provide a signal processing apparatus for an ultrasonic flaw detector capable of performing digital signal processing on an echo signal and reducing noise while keeping the repetition period of the ultrasonic pulse short. It is to provide a method and a signal processing device.
- a second object of the present invention is to provide, in addition to the above-mentioned objects, an ultrasonic wave capable of effectively removing a pseudo echo, minute noise and suddenly reducing a ringing tone, and further improving defect detection accuracy.
- An object of the present invention is to provide a signal processing device for a flaw detector.
- a high-frequency echo signal output from an ultrasonic transmitting / receiving unit that receives a reflected wave from a subject is converted into a digital signal at a predetermined sampling frequency. Then, a measurement period in the repetition period of the ultrasonic pulse is designated, and each sampling data in the measurement period of the echo signal converted into the digital signal is sequentially stored at a writing frequency equal to the sampling frequency. The stored sampling data are sequentially read out at a read frequency lower than the write frequency, and the sequentially read echo signals are subjected to frequency discrimination by a digital filter, and the presence or absence of a defect is determined based on the frequency discriminated echo signals. Is determined.
- the repetition period T Q of the ultrasonic pulse a is several ms or less.
- the measurement period T M required to actually determine the defect is the time from the transmission time of the ultrasonic pulse a to the time when the bottom echo is shot. And at most a number 10 / s, which is much shorter than the repetition period T D of the ultrasonic pulse a (T M ⁇ T Q ).
- the echo signal b within this measurement period T M Becomes a digital signal is AZD converted in-ring frequency f s.
- each sampling data that falls within the measurement period ⁇ ⁇ is, for example, FIF 0 using the same writing frequency f w as the sampling frequency f s.
- (First-in-first-out) Data is stored in the storage unit consisting of type registers. Each sampled data stored in the storage unit is less than the write frequency f w, ie the next digital filter are sequentially read out with a read frequency f R of sufficient data processing.
- the read digital echo signal is subjected to frequency discrimination processing in the next digital filter with a frequency characteristic that attenuates noise most effectively. Therefore, the noise component included in the digital echo signal passing through this digital filter is greatly reduced. Then, the presence or absence of a defect is determined based on the echo signal with the reduced noise component.
- T R T M (C ... digits) Then, if the read time T R and the measurement period time which is a sum of a tau Micromax is shorter than the repetition period T g of the said ultrasonic pulse, the next period T Q start At this point, the previous sampling data does not remain in the FIF 0 type register.
- digital full I Noreta can be provided by carrying out the process for the digital evening Lumpur data that are sequentially output at a slower read frequency f R than the previous supporttown ring frequency fs.
- the number of digital data N M that needs to be processed within the repetition period T Q of one ultrasonic pulse a is much larger than the number of digital data existing in the entire repetition period T n of the echo signal b. Therefore, sufficient processing can be performed within the repetition period Td . That is, it is not necessary to use a high-performance digital filter capable of executing particularly high-speed processing as the digital filter.
- a synchronous averaging filter is used in addition to the digital filter in the signal processing device having the above configuration.
- a synchronous averaging circuit is used instead of a digital filter.
- the echo signal can be averaged for each repetition period T Q of each ultrasonic pulse a, and the noise reduction efficiency can be further increased.
- averaging filter Similar to the digital filter ⁇ averaging filter is synchronization addition and averaging circuit used in place of the aforementioned, that have a function to average the digitized echo signals in each measurement period tau Micromax. Since the noise components included in each echo signal have random phases, each noise component is canceled out by adding and averaging a large number of echo signals, and the noise component as a whole is reduced. The S / N of the defective echo included in the echo signal increases. [Brief description of drawings]
- FIG. 1 is a block diagram showing a schematic configuration of an ultrasonic flaw detector in which a signal processing device according to one embodiment of the present invention is incorporated.
- FIG. 2 is a schematic diagram showing a schematic configuration of a digital filter incorporated in the apparatus of the embodiment.
- FIG. 3 is a time chart showing the operation of the apparatus of the embodiment.
- FIG. 4A is a waveform diagram of an echo signal input to the FIF0 type register of the apparatus of the embodiment.
- FIG. 4B is a waveform diagram of an echo signal output from the FIF0 type register of the device of the embodiment.
- FIG. 5 is a block diagram showing a schematic configuration of an ultrasonic testing device in which a signal processing device according to another embodiment of the present invention is incorporated.
- FIG. 6 is a block diagram showing a schematic configuration of an ultrasonic wave scoring device in which a signal processing device of still another embodiment is incorporated.
- FIG. 7 is a block diagram showing a schematic configuration of an ultrasonic flaw detector in which a signal processing device of still another embodiment is incorporated.
- FIG. 8 is a block diagram showing a schematic configuration of an ultrasonic inspection apparatus in which a signal processing apparatus according to still another embodiment is incorporated.
- FIG. 9 is a time chart showing the operation of the apparatus of the embodiment.
- FIG. 10 is a block diagram showing a schematic configuration of an ultrasonic flaw detector in which a signal processing device of still another embodiment is incorporated.
- FIG. 11 is a time chart showing the operation of the apparatus of the embodiment c .
- FIG. 12 is a block diagram showing a schematic configuration of an ultrasonic flaw detector in which a signal processing apparatus of another embodiment is incorporated.
- FIG. 13 is a time chart showing the operation of the embodiment.
- FIG. 14 is a block diagram showing a schematic configuration of an ultrasonic flaw detector in which a signal processing device of still another embodiment is incorporated.
- FIG. 15 is a block diagram showing a schematic configuration of a synchronous averaging circuit in the device of the embodiment.
- FIG. 16 is an echo signal waveform diagram showing the effect of the apparatus of the embodiment.
- FIG. 17 is a diagram showing the relationship between the average number of times Na and S showing the effect of the apparatus of the embodiment.
- FIG. 18 is a schematic diagram showing a main part of a signal processing device of an ultrasonic flaw detector according to still another embodiment.
- FIG. 19 is an echo signal waveform diagram including a general reflected echo, a defective echo, and a pseudo echo.
- FIG. 20 is an echo signal waveform diagram showing the operation of the apparatus of the embodiment.
- FIG. 21 is a waveform diagram of an echo signal in which the pseudo echo has been reduced in the apparatus of the embodiment.
- FIG. 22 is a block diagram showing a main part of a signal processing device according to still another embodiment.
- FIG. 23 is a block diagram showing a schematic configuration of an ultrasonic testing device in which a signal processing device of still another embodiment is incorporated.
- FIG. 24 is a time chart for explaining the effect of the apparatus of this embodiment.
- FIG. 25 is a schematic diagram showing a schematic configuration of a general ultrasonic flaw detector.
- Fig. 26 is a timing chart showing the operation of the ultrasonic flaw detector. is there.
- FIG. 1 is a block diagram showing the entire ultrasonic flaw detector in which the signal processing device of the embodiment is incorporated. The same parts as those of the ultrasonic flaw detector shown in FIG. Therefore, the detailed description of the overlapping part is omitted.
- the clock signal d output from the clock signal generation circuit 10 is applied to the ultrasonic transmission / reception unit 1.
- the clock signal d is also sent to the AZD converter 11, FIFO type register 12, delay circuit 13, write time counter 14, read time counter 15, and frequency divider 16. .
- a pulse signal every predetermined period T Q ultrasonic transceiver unit 1 divides the clock signal d inputted, the probe 3 attached through a delay material such as direct or water to the subject 2 Send out.
- the probe 3 converts the received pulse signal into an ultrasonic pulse a and applies it to the subject 2.
- the ultrasonic pulse a applied to the subject 2 is reflected by the bottom surface 2 a of the subject 2 and is received again by the probe 3.
- the probe 3 converts the reflected wave into an electric signal and sends it to the ultrasonic transmitting / receiving unit 1.
- the ultrasonic transmission / reception unit 1 amplifies the received electric signal and sends it to the AZD converter 11 as an echo signal b.
- a ZD converter 1 1 by using the frequency of the click lock signal d as sampled in g Frequency i s, converts the input echo signal b to the n bit Bok digital signal, for example. Convert to digital signal
- the echo signal b ⁇ is applied to the data input terminal D ⁇ of the next FIFO type register 12.
- the ultrasonic transmission / reception unit 1 transmits the trigger signal c to the delay circuit 13 in synchronization with the timing of transmitting the pulse signal to the probe 3.
- the delay circuit 13 is composed of a kind of power counter, and when the trigger signal c is input, starts clocking the preset delay time T D using the clock signal d, and counts the delay time T D When the processing is completed, the start signal e is sent to the writing time counter 14.
- the delay time T D is provided to delay the measurement start time of the echo signal b when water or other delay material is inserted between the probe 3 and the subject 2. I have. In the apparatus of the embodiment, the distance between the probe 3 and the subject 2 is 100 mm in water, so that the reflected wave from the subject 2 can be captured.
- the underwater velocity of the sound wave is 1480 mZ s.
- the write time counter 14 When the start signal e is input, the write time counter 14 sends a write enable signal g to the write control terminal of the FIFO type register 12 as shown in FIG. When the predetermined measurement period T M ends, the write time counter 14 releases the write enable signal g. The write enable signal g is also sent to the next read time counter 15.
- the read time counter 15 sends the read enable signal h to the read control terminal of the FIF 0 type register 12 in synchronization with the falling timing of the write enable signal g. And a predetermined reading When the ejection period T R is finished, releasing the read enable signal h.
- the read enable signal h is also sent to the synchronous averaging filter 17.
- the readout period T R is set to be 5 times the value of the measurement period tau Micromax.
- N M is in said measurement period T M
- the frequency divider 16 is the frequency f s of the input clock signal d.
- the FIFO type register 12 converts the n-bit sampling data input to the data input terminal D ⁇ during the H-level period (measurement period T M ) from the write enable signal g to the frequency of the clock signal d.
- the read enable signal h sequentially outputs each sampling data stored in the H level period (read period T R ) from the data output terminal D 2 at the read frequency f R equal to the frequency of the divided clock signal dj. I do.
- Digital echo signals which are sequentially read out with a read frequency f R is input to the next digital filter 1 8.
- this FIR digital finoleta has 128 multiplications. It consists of a delay unit 18a, 128 adders 18b, and 128 delay units 18c. Note that C i to C i ⁇ ⁇ are coefficients. In addition, each delay unit 18c performs a delay of 200 ns corresponding to the cycle of the divided clock signal di. Then, the FIR digital filter performs a product-sum operation represented by equation (2) on a total of 102 input data X (kT j) sequentially input, and outputs output data y (k) Get.
- Digital Fi with at filter 1 8 (2) digital echo signal b 3 to another processing operation frequency valve is performed as shown in formula is input to the next synchronous averaging filter 1 7.
- the synchronous averaging filter 17 repeats the ultrasonic pulse a for each of the 10 24 data items constituting the echo signal b 3 sequentially output from the digital filter 18 and represented by the equation (2). Calculate the average for each cycle TJJ. Specifically, the synchronous averaging filter 17 synchronizes with the rise of the read enable signal h from the read time counter 15 to output the same signal output from the digital filter 18 in the next cycle. Calculate the averaging of each data for the specified number of times in the past at the mining position and calculate the new averaging code. Have a single signal b 4 and sends it to the next defect determining section 1-9.
- averaged echo signal b 4 input is converted into an echo signal b 5 analog I even DZA converter 1 9 a.
- Echo signal b 5 are compared by the comparator 1 9 b.
- the analog echo signal bp is also sent to the display unit 20.
- the trigger signal c is output in synchronization with the transmission of the ultrasonic pulse a.
- the echo signal b is output from the ultrasonic transmission / reception unit 1.
- the echo signal b is converted into a digital echo signal by the AZD converter 11.
- the write enable signal g rises after the delay time T D due to the delay material such as water from the trigger signal c output, and the digital echo signal b 1 output from the A / D converter 11 1,024 sampling data are written to the FIF 0 register 12.
- the time required to write these 1,024 (-N ,,) sampling data that is, the measurement period T M, is written at the same frequency as the 25 MHz sampling frequency f s of the A / D converter 11. Therefore, it is 40 ns for one data, which is 40.96 s in total.
- the reading interval is 200 ns next sampling data
- the operation time is 204.8 us since the output interval of the data output from the digital filter 18 is 200 ns.
- defect determination section 19 is constituted by an analog circuit, the time required for the determination can be almost ignored.
- the digital signal processing for the echo signal b output in response to one ultrasonic pulse a is the repetition period T n of the ultrasonic pulse a required for online flaw detection processing. Can be implemented within ms. Therefore, it is not necessary to use a high-performance computer with a high arithmetic processing speed. The adoption of digital signal processing does not significantly increase the manufacturing cost of the entire ultrasonic flaw detector.
- digital filter processing and synchronous addition average filter processing can be easily performed on high-frequency echo signals b that contain a lot of electrical noise and material noise.
- the optimal filter conditions for noise By setting the optimal filter conditions for noise, the noise component contained in one echo signal can be effectively removed, and the defect detection accuracy of the ultrasonic flaw detector can be greatly improved.
- FIG. 5 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- the clock signal d divided by the divider 16 to 1Z5 is input to the clock terminal of the read time counter 15a.
- FIG. 6 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- the write enable signal g output from the write time counter 14 is only sent to the FIF 0 type register 12 and not input to the read time counter 15c. Then, the read time counter 15 c outputs the output from the ultrasonic transmitting / receiving section 1.
- the trigger signal c has been manually input.
- the readout time counter 1 5 c is collected by the trigger signal c is input, and starts the time count of the delay time T, the waiting time obtained by adding the measured period ⁇ ⁇ (T R + ⁇ ⁇ ) shown in FIG. 3, At the end of this waiting time (T R + ⁇ ⁇ ), the read enable signal h is set to H level. Then, when read out measurement of the time T R is finished, to release the read enable signal h of the H level to L level.
- the read time counter 1 5 c so measures between the read T R shown in FIG. 3, it is possible Rukoto obtain substantially the same effect as the embodiment of FIG.
- FIG. 7 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- the delay time between T D of the delay circuit 1 3 d is counting, the readout time T R the write time counter 14 d is the measurement period T M Contact and readout time counter 1 5 d is clocked to count
- the setting can be arbitrarily changed by the external time setting unit 21.
- the subject 2 to be inspected by the ultrasonic flaw detector Therefore, depending on the shape of the subject 2, it may be necessary to specify the area to be flaw-detected particularly as a portion shallow or deep from the surface. Further, the thickness of the subject 2 also changes greatly.
- the flaw detection range is changed or the flaw detection range is enlarged or reduced in this way, it is necessary to move the position of the measurement period T M in the echo signal b or to extend or shorten the measurement period ⁇ ⁇ .
- This Such a case as, by the time setting unit 21 sets the delay time T D, a measurement period tau Micromax and readout time T R to the optimum value. Therefore, the applicable range of the ultrasonic flaw detector incorporating the signal processing device can be greatly expanded.
- FIG. 8 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to still another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 7 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- the AZ converter 11, the first FIFO type register 12 a, the digital filter 18, and the second filter 18 are arranged along the signal path of the echo signal b output from the ultrasonic transmission / reception unit 1.
- a FIF 0 type register 12b, a DZA converter 22, and an external defect determination unit 23 are provided.
- Clock signal d having a sampling frequency f s that is output from the clock signal generating circuit 1 0, the first FIF 0 type register 1 2 a Shokomiku lock through the AND gate 14 e
- the signal is applied to the read clock terminal of the second FIFO register 12b via the AND gate 24a. Further, the clock signal d is applied to the clock terminal of the DZA converter 22.
- the activation signal e output from the delay circuit 13 d is applied to the write time counter 14 d and the processing time counter 15 a.
- the write time counter 14d applies the H-level write enable signal g for the measurement period (AZD conversion time) T M to the AND gate 14e.
- the first FIF type 0 register 12a stores the sampling frequency of each digital echo signal bi output from the A / D converter 11 for the measurement period (AZD conversion time) T M
- the data is sequentially captured at the same writing frequency as f s and stored.
- the processing time counter 1 5 a applies a timed readout time by setting unit 2 1 (signal processing time) T R by H-level read permission signal h to an AND gate 1 5 b.
- the first FIF 0 type register 1 2 a is reads each data stored by the read time (between time signal processing) T R in turn read frequency f R of 1 Z5 sampling frequency f s, Digital echo — sent to digital filter 18 as signal b 2 .
- Digital filter 18 may implement a frequency discrimination processing before mentioned in real time with respect to the echo signal b 2 sequentially input at a speed corresponding to the read frequency f n, E code signal from which a noise component has been removed Send b 2 to the second FIFO register 1 2 b.
- the read enable signal h for the first FIF 0 type register 12a output from the processing time counter 15a is the read time counter of the second FIFO type register 12b in addition to the AND gate 15b. Applied to 24.
- the read time counter 24 When the read enable signal h for the FIFO type register 1 a of the 2 a falls from the H level to the L level and falls to the H level for the read time (measurement time) T M set by the time setting unit 21 from the fall time Apply enable signal m to AND gate 24a.
- the second FIF type 0 register 12 b outputs the digital filter 18 in synchronization with the read start time of the echo signal b 2 of the first FIFO type register 12 a.
- each data of the echo signal b 3 being, stored in ipecac sequentially in equal write frequency to the read frequency f n of the first FIFO-type register 1 2 a.
- the second FIFO type register 1 2 b are, based on this stored respective data were It reads have at the sampling frequency f s 5 times the read frequency equal to, applied as an echo signal b 6 to the next D / a strange exchanger 22.
- D / A converter 22 crowded obtain respective data echo signals b, at sampling frequency f s and converted into an analog echo signal b 7, and sends to the outside of the defect determination unit 23.
- FIG. 9 is a time chart showing the operation of the embodiment apparatus shown in FIG.
- the delay circuit 13 d measures the delay time T D in synchronization with the trigger signal c, and then the write time (measurement period) ⁇ ⁇ and the signal processing time (read time) T R Timing starts.
- the signal processing time (reading time) T D ends, the reading time T M for the second OF IF 0 type register 1 2 b starts.
- the time axis of the echo signal is set to 2 during the period in which the digital filter 18 performs the frequency discrimination process on the input echo signal. It has expanded from 5 MHz to 5 times 5 MHz. Then, back to the original time axis the frequency discrimination process is completed in the digital filter 1 8, is converted into an echo signal b 7 analog.
- Defect determination process on an analog echo signal b 7 is defective events in E co first signal can be even 2 5 be a high frequency of approximately MH z sufficiently defect determination processable. Therefore, flaw detection for the subject 2 can be easily performed by applying the echo signal b ? Of the analog aperture to a general ultrasonic flaw detector.
- the noise component of the echo signal b 7 is because it is largely suppressed by the digital filter 1 8, can have contact to the general ultrasonic detector can accurately detect a defect.
- FIG. 10 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to still another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 8 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- the time setting unit 21a can calculate the data processing time required for the frequency discrimination processing in the digital filter 18a in addition to the delay time T D , the write time (measurement period) ⁇ ⁇ , and the read time TD. Set T p .
- the read permission signal h of the first FIFO type register 12a is applied to the AND gate 15b and also to the data processing time counter 26. As shown in the time chart of FIG. 11, the data processing time counter 26 synchronizes with the falling edge of the read enable signal h and sets the data processing time set by the time setting unit 21 a ⁇ ⁇ And outputs the H-level data processing time signal o.
- the second FIFO type register 1 2 b as shown in Taimuchiya one bets FIG. 1, the digital filter 18 at the time when you Keru data processing time T [rho has ended a, the digital full I filter 1 8 c and go written echo signal b output from a, each data at the frequency f R of 1 Z 5 Sa Prix ring frequency f s, at the time when the process of writing all of the data is completed, the original Data is sequentially read out at the fast sampling frequency f s and applied to the next DZA converter 22 as an echo signal b 6 .
- the signal processing device configured ultrasonic flaw detector, the echo signal b 3 which is frequency discrimination process in the digital Fi le evening 1 8 a second FIFO type register 1 2 b it Accordingly, since it is revert to the echo signal b 6 having the original time axis, it is possible to obtain substantially the same effect as the embodiment shown in FIG.
- FIG. 12 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to still another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 8 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- Digital filter 18, second FIFO type register 12 b, of DZA converter 22, first FIFO type register 12 a, first digital filter 18, second FIF 0 type register 1 For the signal storage processing circuit consisting of 2b, another signal storage processing circuit consisting of the third FIF 0 type register 12aa, the second digital filter 18b, and the fourth FIFO type register 12bb They are connected in parallel.
- the first and second FIFO type registers 12a and 12b of the upper signal storage circuit are paired.
- the delay time T D , write time (measurement time) ⁇ ⁇ , and read (processing time) T R , the first and second FIFO registers of the lower signal storage processing circuit 12 aa, 12 bb Delay time T dd , write time (measurement time) ⁇ ⁇ , and read (processing time) T RR can be set individually.
- the write time (measurement time) ⁇ ⁇ ⁇ is added to the delay time T dd of the lower signal storage processing circuit and the delay time T D of the upper signal storage processing circuit. by the amount of time (T D + T M) than the setting child, a plurality of defect E Coat 5 a at different time positions in the echo signal on the b, 5 b, respectively and individually extracted, each digital filter 1 8, 18 frequency discrimination process using the b is feasible c then, the digital signal processed each echo signal b 6, b 66 synthesized by the echo of the original one analog by the D / a converter 22 it can be obtained signal b 7.
- Each defect echo on the echo signal b 5 a, 5 b for measurement time (writing time) tau Micromax, scale defects tau Myumyu respectively, can be set to an optimum time width depending of the kind.
- FIG. 14 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to still another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 8 are denoted by the same reference numerals. According to Therefore, the detailed description of the overlapping part is omitted.
- the synchronous averaging circuit 27 converts the digital echo signal b 2 output from the first FIF type 0 register 12 a every time the output cycle T Q of the ultrasonic pulse a elapses into a plurality of cycles (N a times). It has the function of averaging over all. Then, averaged for N a number of echo signals b 2, a digital echo signal b 8 is input to the second FIFO type register 1 2 b below.
- Synchronization addition and averaging circuit 27 performs an averaging process of the echo signal b 2 by dividing click lock signal of a frequency f upsilon outputted from the frequency divider 1 6.
- FIG. 15 is a block diagram showing a schematic configuration of the synchronous averaging circuit 27.
- Each data of the write address constituting the echo signals b 2 for the first signal memory 28 is first write add- Specified by Rescue Counter 30a.
- read der Dress RA j of when reading an echo signal b 2 stored in the first signal memory 2 8 is specified by the first read A Doresukau printer 3 0 b.
- Each of the counters 30a and 30b is driven by the frequency-divided clock signal dj.
- the read address of the first read address counter 30b is the average number of times Na in the area 28a with respect to the write address WAi of the first write address counter 30a. Initially, the value is delayed (smaller).
- RA j WA j - N M ⁇ N a
- each input echo signal b are sequentially stored in each address specified by the write address WA i which increases in synchronization with the frequency-divided clock signal.
- WA i which increases in synchronization with the frequency-divided clock signal.
- N a of times before the data of the same waveform position of the stored echo signals b 2 to the first signal Note Li 2 8 read ud d Re in synchronism with the write operation * S) o
- Each data N a of times before the E co first signal b 2 read out from the first signal memory 2 8 is input to a subtracter 3 1 for next digital subtracting process.
- the second signal memory 32 stores the added echo signal b, that is, the added echo signal b 88.
- Has the N M ( 1 024) number of addresses, each te Isseki of 1 6 pit in each address can be stored.
- Each data of the added echo signal output from the subtractor 31 is sequentially written into the second signal memory 32. Further, the added echo signal b 88 read from the second signal memory 32 is added to the adder
- Shokomia drain scan WA 2 of each data of the addition echo signal from the subtracter 3 1 is designated by the second write address counter 33 a. Further, the read address RA 2 of each data of the addition the echo signal b 88 to be sent to the adder 29 is designated by the second read A Doresukau printer 33 b.
- Each of the counters 30a and 30b is driven by the frequency-divided clock signal. Further, in synchronization with the divided clock signal, each of the four address counters 30a, 30b,
- 33 and 33b are initially set to specify the same position on the waveform signal of the echo signal, that is, the same address in each area 28a and 1 to 1024 in the first signal memory 32. ing.
- the adder 29 is the data of the second and the data of the signal memory 32 is read from the sum E code signal b 88 constituting a 6-bit configuration, 8-bit structure constituting the echo signals b 2 input And are added, and an added echo signal composed of 16-bit data is sent to the subtractor 31.
- the subtractor 31 subtracts the 8-bit data of the echo signal read from the first signal memory 28 from the 16-bit data of the added echo signal input from the adder 29. Then, an addition echo signal composed of the subtracted 16-bit data is sent to the second signal memory 32 and also sent to the divider 34.
- Divider 34 is composed of, for example, in bit Bok shifter foremost, by dividing the sum echo signal by an average number N a, the second FIF 0 type register 14 as the echo signal d 8, averaged Send to 1 2 b.
- the first echo signal b 2 is input from the first FIF 0 type register 12 a
- the first echo signal b 2 is stored in the first area 28 a of the first signal memory 28.
- it is stored in the second signal memory 32.
- nothing is serial billion in each ⁇ address area 28 a the read address is specified by the second signal memory 32 and the first signal memory 28, echo signals b 2 input adder
- the signal passes through 29 and the subtractor 31 and is stored in the second signal memory 32.
- the adder 29 adds the current echo signal and the previous (first) echo signal to generate an added echo signal.
- the read address RA i of the first signal memory 28 is still Since nothing is stored in each address of the designated area 28 a, the added echo signal passes through the subtractor 31 and is stored in the second signal memory 32.
- the echo signals are sequentially added to the second signal memory 32 until the average number of Na echo signals b 2 are input.
- the average number N a more echo signals b 2 is Once entered, sent from the echo signal b 2 input to the new N a or to the subtracter 3 1 echo signal is read out previously entered.
- the addition echo signal b 8 stored in the second signal memory 32.
- the new echo signal b 2 is added, and the N a previous echo signal b 2 is subtracted. Therefore, the second signal memory 32 always adds the latest Na echo signals to the added echo signal b 88 3 ⁇ 4r ⁇ IB ".
- the noise is lower than the method of synchronously averaging the waveforms of the one-sided amplitude after envelope detection of the echo signal.
- the reduction effect can be increased.
- the average number of times Na may be set as appropriate in the relationship between the count values WA ⁇ and R Aj of the first write address counter 30a and the first read address counter 30b. Can be changed easily.
- the presence or absence of a defect is determined by comparing the signal level of the echo signal b and the threshold value for each ultrasonic pulse a . Therefore, even if it is sudden noise, it is determined that there is a defect.
- the level of sudden noise exceeding this threshold can be reduced to lZNa, and this sudden noise is erroneously determined as a defect. Can be prevented from occurring. Therefore, the reliability of the entire device can be further improved.
- Figure 16 shows the comparison between each echo signal waveform before input to the synchronous averaging circuit 27 and the echo signal waveform averaged by the synchronous averaging circuit 27 when the averaging count Na is set to 4. It can be understood that the SZN of the defect echo (F echo) in the averaged echo signal is greatly improved, as shown in the actual measurement diagram.
- the synchronous averaging circuit 27 having the excellent noise reduction function described above can be applied to the embodiment device shown in FIG.
- the noise component included in the echo signal output from the FIFO type register 12 can be significantly reduced.
- FIG. 18 is a schematic view showing a main part of a signal processing device of an ultrasonic flaw detector according to another embodiment of the present invention.
- the signal processing unit for the echo signal b after the ultrasonic transmission / reception unit 1 is the same as that in the embodiment shown in FIG.
- the subject 2a is conveyed at a speed V in a certain direction by, for example, an inspection line in a manufacturing factory by each conveying roller 35a, 35b, 36a, 36b. I have.
- the probe 3 is provided in a non-contact manner with the subject 2 a by a support mechanism 38 in which water 37 is sealed.
- the incident period T Q to the subject 2 a of the ultrasonic pulse a to adjust the moving velocity V of the object 2 a, with respect to the traveling direction of the subject 2 a for example
- Each ultrasonic pulse a is incident on a different position in one interval.
- Each echo signal b obtained by each ultrasonic pulse a. are averaged by a synchronous averaging circuit 27.
- each of the Na echo signals d 2 sequentially input to the synchronous averaging circuit 27 becomes an echo signal at a position different by 1 mm.
- each echo signal b contains many pseudo echoes due to the spread of reflection echo (S echo) and forest echo.
- Each of these pseudo echoes greatly changes, including the phase, when the incident position of the ultrasonic pulse a with respect to the subject 2a is minutely changed. Therefore, by averaging a large number of echo signals, pseudo echoes included in the echo signals can be reduced.
- FIG. 21 is a diagram showing an echo signal obtained by averaging each echo signal obtained by moving the incident position of the echo signal shown in FIG. 19 by a very small distance. As shown in the figure, it can be understood that the pseudo echoes near each of the surface echo (S echo) and the defect echo (F echo) are greatly reduced.
- FIG. 22 is a schematic view showing a main part of a signal processing device of an ultrasonic flaw detector according to another embodiment of the present invention.
- seven probes 3a are arranged in one direction. For example, they are arranged at minute intervals such as 1 mm intervals. In addition. A plurality of probes arranged in this state are generally called array probes.
- a pulse signal is applied to each probe 3 from a dedicated transmitting unit 39.
- Each of the echo signals output from each of the seven probes 3a is received by a dedicated receiving unit 40, and each of the transmitting units 39 and each of the receiving units 40 has four multiplexers 41, 42, respectively. Is connected.
- Each of the multiplexers 41 and 42 is switched by a multiplexer control unit 43 to which a trigger signal cj of, for example, an lms period is input from a trigger circuit 45. Also.
- the echo signals output from the multiplexers 42 are combined and amplified by the amplifier 46.
- the echo signal b amplified by the amplifier 46 is input to the AZD converter 11 in FIG.
- the signal processing unit for the echo signals after the AZD converter 11 is the same as the signal processing unit shown in FIG. 14.
- the c multiplexer control unit 43 controls the switching of each of the multiplexers 41 and 42 as follows. When the first trigger signal ci is output from the trigger circuit 45, the first multiplexer 41 selects the first transmitter 39, and the second multiplexer 41 selects the second transmitter 39. 3.
- the fourth multiplexer 41 selects the third and fourth transmitters 39, respectively. Further, the first to fourth multiplexers 42 select the first to fourth receivers 40, respectively.
- each of the first to fourth probes 3a is driven, and each echo signal is received from each of the first to fourth probes 3a and each of the first to fourth receivers 3a
- the signals are received by the first to fourth multiplexers 42 through the section 40.
- the four echo signals output from the first to fourth multiplexers 42 are combined and amplified by the amplifier 46 and sent to the AZD converter 11 as a new echo one signal b.
- the first to fourth multiplexers 41 select the second to fifth transmitters 39, respectively, and the first to fourth multiplexers 41 are selected.
- Each of the multiplexers 42 selects the second to fifth receiving units 40.
- the amplifier 46 outputs an echo signal b for each of the second to fifth probes 3a.
- the trigger circuits 45 to 3 When the third trigger signal ci is output, the first through fourth multiplexers 41 select the third through sixth transmitters 39, respectively, and the first through fourth multiplexers 42 each output the third multiplexer 34. -Select the sixth receiver 40. As a result, an echo signal b for each of the third to sixth probes 3a is output from the amplifier 46 in synchronization with the third trigger signal Cl.
- the echo signal b corresponding to each of the fourth to seventh probes 3a is output from the amplifier 46.
- the amplifier 46 When the fifth trigger signal c i is output from the trigger circuit 45, the amplifier 46 outputs the echo signal b for each of the first to fourth probes 3a.
- the combination of the probe 3a selected for each trigger signal c ⁇ is limited to the combination of [1-4] [2-5] [3-6] [4-7] described above. It is not something to be done. For example, when nine probes 3a are used, every other one may be selected, such as an odd number or an even number, as in [1 3 5 7] [2468] [3579].
- FIG. 23 is a block diagram showing a schematic configuration of a signal processing device of an ultrasonic flaw detector according to still another embodiment of the present invention.
- the same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals. Therefore, the detailed description of the overlapping part is omitted.
- the clock signal d output from the clock signal generation circuit 10 is frequency-divided by the frequency divider 47 to 1 Zn i.
- the divided clock signal is shaped into a trigger signal c with a short pulse width by a monostable circuit 48 (one-shot multivibrator MU).
- the trigger signal c is applied to the delay circuit 13 d and the ultrasonic transmission / reception unit 1.
- the clock signal generating circuit 10, the frequency divider 47, and the monostable circuit 48 constitute a trigger generating means.
- the frequency range of the ultrasonic pulse a incident on the subject 2 Since the range is very large, 10 MBz or more, the sampling frequency f s indicated by the frequency of the clock signal d is about 25 MHz in order to satisfy the sampling theorem in the A / D converter 1]. It is necessary. On the other hand, in order to reduce the manufacturing cost of the AZD converter 11, a slightly lower frequency is desirable.
- a clock signal generation circuit 10 sends a clock signal d for sampling from the clock signal generation circuit 10 to the AZD converter 11 and divides the same clock signal d to generate a trigger signal c. To the ultrasonic transmission / reception unit 1 and the delay circuit 13 d. The ultrasonic transceiver 1 synchronizes with the trigger signal c. To send a pulse signal to the probe 3.
- the sampling frequency f. Of the A / D converter 11 is low, the amount of jitter can be greatly suppressed, the noise component contained in the echo signal can be surely canceled, and the manufacturing cost is low. As a result, the SZN of the echo signal can be further improved.
- the present invention is not limited to the embodiments described above.
- the FIF0 type register was used as storage means for storing each sampling data of the AZD-converted echo signal.
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- Life Sciences & Earth Sciences (AREA)
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Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94917165A EP0654666B1 (en) | 1993-06-07 | 1994-06-07 | Signal processing method and signal processing device for ultrasonic inspection apparatus |
KR1019950700435A KR0160003B1 (ko) | 1993-06-07 | 1994-06-07 | 초음파 손상검출장치의 신호처리방법 및 신호처리장치 |
US08/374,777 US5671154A (en) | 1993-06-07 | 1994-06-07 | Signal processing method and signal processing device for ultrasonic inspection apparatus |
DE69428963T DE69428963T2 (de) | 1993-06-07 | 1994-06-07 | Verfahren und vorrichtung zur verarbeitung von signalen für einen ultraschallinspektionsapparat |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5135562A JP2985579B2 (ja) | 1992-06-09 | 1993-06-07 | 超音波探傷装置の信号処理装置 |
JP5/135562 | 1993-06-07 |
Publications (1)
Publication Number | Publication Date |
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WO1994029714A1 true WO1994029714A1 (fr) | 1994-12-22 |
Family
ID=15154719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1994/000916 WO1994029714A1 (fr) | 1993-06-07 | 1994-06-07 | Procede et appareil pour traiter les signaux d'un detecteur de defauts par ultrasons |
Country Status (6)
Country | Link |
---|---|
US (1) | US5671154A (ja) |
EP (1) | EP0654666B1 (ja) |
KR (1) | KR0160003B1 (ja) |
CN (1) | CN1035690C (ja) |
DE (1) | DE69428963T2 (ja) |
WO (1) | WO1994029714A1 (ja) |
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DE19941690C2 (de) * | 1999-09-01 | 2001-12-06 | Siemens Ag | Steuergerät und Lötverfahren |
US6728515B1 (en) | 2000-02-16 | 2004-04-27 | Massachusetts Institute Of Technology | Tuned wave phased array |
US6392327B1 (en) | 2000-03-29 | 2002-05-21 | James L. Sackrison | Sonic transducer and feedback control method thereof |
JP4552309B2 (ja) | 2000-11-02 | 2010-09-29 | 株式会社Ihi | 超音波探傷方法及び装置 |
US6833554B2 (en) * | 2000-11-21 | 2004-12-21 | Massachusetts Institute Of Technology | Laser-induced defect detection system and method |
WO2002086474A1 (en) * | 2001-04-20 | 2002-10-31 | Commonwealth Scientific And Industrial Research Organisation | Probe for non-destructive testing |
AUPR450801A0 (en) * | 2001-04-20 | 2001-05-24 | Commonwealth Scientific And Industrial Research Organisation | Method and apparatus for carrying out non-destructive testing of materials |
US20050111011A1 (en) * | 2001-04-20 | 2005-05-26 | Dickinson Laurence P. | Probe for non-destructive testing |
CN100520396C (zh) * | 2003-09-30 | 2009-07-29 | 北京时代之峰科技有限公司 | 数字式便携超声探伤仪的dac曲线制作方法 |
US7404671B2 (en) * | 2005-03-10 | 2008-07-29 | Luna Innovations Incorporated | Dynamic acoustic thermometer |
US7757557B2 (en) * | 2005-10-14 | 2010-07-20 | Olympus Ndt | Ultrasonic detection measurement system using a tunable digital filter with 4x interpolator |
US7461554B2 (en) * | 2005-10-14 | 2008-12-09 | Olympus Ndt | Digital time variable gain circuit for non-destructive test instrument |
US8001841B2 (en) * | 2005-10-14 | 2011-08-23 | Olympus Ndt | Ultrasonic fault detection system using a high dynamic range analog to digital conversion system |
CN101331395B (zh) * | 2005-10-14 | 2012-06-27 | 奥林巴斯Ndt公司 | 超声波探伤系统 |
KR100769627B1 (ko) * | 2006-04-19 | 2007-10-25 | 미승씨엔에스검사주식회사 | 비파괴 검사장치 |
CN101467035B (zh) * | 2006-06-13 | 2012-10-31 | 住友金属工业株式会社 | 超声波探伤方法、焊接钢管的制造方法及超声波探伤装置 |
EP2478353B1 (en) * | 2009-09-18 | 2016-11-02 | Conocophillips Company | High precision ultrasonic corrosion rate monitoring |
EP2372318B1 (de) * | 2010-03-26 | 2020-03-18 | VEGA Grieshaber KG | Störechospeicherung bei Behälterrauschen |
GB2482124B (en) * | 2010-07-19 | 2016-08-17 | Ultra Electronics Ltd | Acoustic structural integrity monitoring system and method |
US9638673B2 (en) * | 2012-10-18 | 2017-05-02 | Olympus Scientific Solutions Americas Inc. | Ultrasonic testing instrument with dithery pulsing |
CN103175900B (zh) * | 2013-03-19 | 2016-02-17 | 中国科学院声学研究所 | 一种相控阵无损探伤装置和系统 |
KR101738803B1 (ko) * | 2013-04-02 | 2017-05-22 | 제이에프이 스틸 가부시키가이샤 | 초음파 탐상 방법 및 초음파 탐상 장치 |
CA2967646A1 (en) * | 2014-11-14 | 2016-05-19 | Ursus Medical, Llc | Ultrasound beamforming system and method based on aram array |
BR112018003357B1 (pt) | 2015-08-28 | 2021-09-28 | Micro Motion, Inc. | Medidor e método de geração de um sinal |
CN107060739B (zh) * | 2017-06-29 | 2023-03-21 | 西安海联石化科技有限公司 | 一种存储式油井动液面监测系统及方法 |
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- 1994-06-07 EP EP94917165A patent/EP0654666B1/en not_active Expired - Lifetime
- 1994-06-07 KR KR1019950700435A patent/KR0160003B1/ko not_active IP Right Cessation
- 1994-06-07 CN CN94190492A patent/CN1035690C/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
CN1112374A (zh) | 1995-11-22 |
KR0160003B1 (ko) | 1999-03-30 |
CN1035690C (zh) | 1997-08-20 |
DE69428963D1 (de) | 2001-12-13 |
EP0654666A4 (en) | 1995-11-02 |
DE69428963T2 (de) | 2002-08-14 |
KR950703144A (ko) | 1995-08-23 |
EP0654666B1 (en) | 2001-11-07 |
EP0654666A1 (en) | 1995-05-24 |
US5671154A (en) | 1997-09-23 |
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