GB2114758A

GB2114758A - Ultrasonic flaw detector signal analyser

Info

Publication number: GB2114758A
Application number: GB08203382A
Authority: GB
Inventors: David Ian Crecraft; Paul Edwin Garner; Hugh Krikham Craig
Original assignee: Rolls Royce PLC
Current assignee: Rolls Royce PLC
Priority date: 1982-02-05
Filing date: 1982-02-05
Publication date: 1983-08-24
Also published as: DE3302548A1; JPS58151556A; GB2114758B; FR2521297B1; FR2521297A1

Abstract

A signal analyser for analysing the echo signals generated by an ultrasonic flaw detector, particularly in the region of geometry echoes comprises a number of signal processing channels (10), each arranged to receive a portion of the echo signal via a time gate (34) which is operated by a clock (14) or a clock (58) emitting gate pulses, and a shift register (12). Each signal processing channel (10) includes hold circuit (40) or (74) which holds the peak value of the signal in the respective time gate, an averaging filter (42) or (76) the output from which represents the average "grass" level, a first comparator (44) or (78) the output from which represents the difference between the outputs from the hold circuit and the averaging filter, and a second comparator (46) or (80) which receives the output of the first comparator and a threshold signal. The second comparator only has an output if the output of the first comparator is greater than the threshold signal, and thus represents a flaw and this output enables a tri-state buffer to pass the output of the first comparator to the output data bus. <IMAGE>

Description

SPECIFICATION Ultrasonic flaw detector signal analyser This invention relates to an analyser for processing and analysing the electrical signals generated by an ultrasonic flaw detector used for the non destructive testing of engineering components, in particular the turbine discs of gas turbine engines.

Internal flaws, which are essentially weaknesses in the material structure of such components, occur during the processing of the raw mateiral, the production of the component and during the service life of the component. The detection of these flaws is essential, particularly so in the case of highly stressed components like turbine discs. If the position and size of the flaw or flaws are known then the application of modern methods of fracture mechanics can determine with considerable accuracy, the life expectancy of the component.

A common method of non-destructively testing turbine discs for internal flaws is to immerse the disc in a water bath, rotate the disc and expose the disc to impulses of ultrasonic sound emitted from an ultrasonic probe, which is slowly moved over the disc. Each impulse is reflected by the component as a succession of echoes, comprising echoes from the front and rear surfaces of the component, an echo of varying magnitude called "grass", from the grain structure of the component material and if the impulse has been emitted over a flaw, there will be an echo corresponding to the flaw. The size of the flaw is related to the magnitude of the corresponding echo. If the impulse has been emitted in the region of a change in cross-section of the component, there will also be further echoes called "geometry echoes".

All these echoes are displayed on a screen, and the operator must recognise an echo which rises above the grass level momentarily, as the flaw passes under the probe, and disappears again.

The most critical case is when a flaw occurs in the region of a section change, and the flaw echo is masked by the geometry echo, e.g. the flaw echo signal may occur momentarily on the trailing edge of the relatively large geometry echo signal. The visual detection of such a flaw needs considerable concentration over long periods, experience, and pattern recognition skill. A momentary lapse of concentration could mean that a flaw passes undetected.

The present invention seeks to provide an apparatus which will process and analyse the signals produced by the echoes from a component subjected to ultrasonic nondestructive testing, so that flaw echo magnitude and position, particularly in the region of section changes, are indicated and recorded without the need for a continuous visual inspection of the echo signals.

According to the present invention there is provided a signal analyser comprising a plurality of signal processing channels, each channel of which is arranged to receive the signals to be analysed via a gating means, all the gating means being operable by a gating control to allow the signal to be analysed by each channel in sequence, each channel including a hold circuit arranged to receive and hold the peak value of the signal in the respective time gate, and averaging filter arranged to receive the output from the hold circuit, a first comparator arranged to receive the outputs from the hold circuit and the averaging filter, the output from the first comparator being passed to a second comparator which also receives a threshold level signal, the output from the second comparator being used to determine whether or not the signal from the first comparator is significant, and if so to record the output of the first comparator.

The output from the second comparator may pass to an analogue to digital (A-D) convertor which enables the output from the first comparator to be converted to digital form if the first comparator output is greater than the pre-set threshold level. The data converted may be passed to a data bus via a tri-state buffer, the data bus being connected to a first-in, first-out (FIFO) memory from which data can be passed to a visual display and a printer and/or a computer for data analysis.

The signal analyser may be particularly adapted to analysing the echo signals generated by an ultrasonic flaw detector in which regular impulses of ultrasonic energy are directed at an engineering component for testing purposes. The input signal to the analyser comprises the echo signals from the component, and these signals are preferably processed by a variable attenuator and a logarithmic amplifier before passing to the signal processing channels via the gating means.

The gating means may comprise a variable rate clock circuit to give gate pulses of chosen width, and a shift register, the clock circuit being activated by a pulse emitted by the flaw detector via a delay, or directly to the front wall echo signal from the component under test. The clock circuit may give uniform width gate pulses, the width of which can be varied by the operator, or the gate pulses may be obtained from a second clock circuit where the gate pulse width can be dependent upon the strength of the echo signal so that the geometry echoes can cause the gate pulse width to be narrowed enabling the geometry echoes to be closely examined.

The output from the first comparator represents the signal in decibels (dB) above the "grass" level and if this signal is above the threshold level, the second comparator recognises the signal as being a flaw signal and causes the A-D converter to convert the signal to digital form. The flaw size data together with the flaw depth in the form of numbers of pulses from the uniform clock circuit pass to the FIFO memory, the visual display and the printer and/or a computer. The visual display and the printer, and/or computer also receive data indicating the total number of flaws detected and the printer and/or computer receives data from a mechanical scanning system of the test rig indicating the position of the flaw.

Each signal processing channel may comprise analogue or digital devices, and in the analogue form, the first and second comparators comprise a differential amplifier and an analogue comparator, and the hold circuit comprises a capacitance circuit, which may include a capacitor and a buffer.

In the digital form, the comparators are both digital comparators, the hold circuit comprises a digital register and a single analogue to digital converter replaces the converters in the signal processing channels, and is arranged to convert the input signal from the flaw detector prior to being passed to each processing channel.

The present invention will now be more particularly described with reference to the accompanying drawings in which: Fig. 1 shows a typical echo plot of echo-signal amplitude versus time.

Fig. 2 shows on an enlarged scale, a part of the echo plot at a section change in the component, without the presence of a flaw signal.

Fig. 3 is similar to Fig. 2 but with the presence of a flaw signal, Fig. 4 is a block diagram of one form of signal analyser according to the present invention, Fig. 5 is a block diagram of one of the analogue signal processing channels of the analyser shown in Fig. 4, Fig. 6 shows the signal waveforms at various stages along the channel shown in Fig. 5, Fig. 7 is schematic layout showing the analyser of Fig. 4 coupled to a flaw detector and a nondestructive testing rig, and Fig. 8 is a block diagram of a digital form of the signal processing channel shown in Fig. 5.

Fig. 1 shows a plot of the type of echo received from a component having a section change. The signals A and B are the echo signals received from the front and back walls of the component, the signal C is the signal from the section change, known as a geometry echo, and there is a signal D which represents the background echoes from the grain structure of the component, known as "grass".

Fig. 2 shows to a larger scale, the trailing edge of the train of relatively large, damped oscillations of the geometry echo C. Existing methods of flaw location require the operator to recognise the flaw as an extra signal which suddenly appears on this train of oscillations as shown in Fig. 3. The present signal analyser proposes to examine the geometry echo signal through a series of gates of variable time width. Figs. 2 and 3 together show the effect of the use of different gate pulse widths.

In Fig. 2, the peak signal, in a broad gate pulse of duration t, is shown to be one of the oscillations of the geometry echo. In Fig. 3, with a gate of the same duration the peak signal is the same as in Fig. 2 because, although a flaw signal E has appeared in the gate duration, it is lower than the adjacent part of the geometry echo.

Fig. 2 also shows the operation with a narrow gate pulse of duration t2, and the peak signal within this gate is the next lower cycle of the geometry echo. In Fig. 3 the flaw echo E within the same narrow gate rises above the value of the narrow gate in Fig. 2 and providing the flaw echo exceeds a predetermined threshold level, which is some level above the 'grass' level, the flaw will be recognised and recorded.

As will be described later in detail, the analyser may use narrow gate pulses with a duration of about 100 ns in the region of the geometry echo and wider gate pulses elsewhere. The operator may choose to use one of two clock generators to control the gate pulse width, a uniform clock or an echo size controlled clock which generates pulses of a predetermined period unless a substantial echo, e.g. a geometry echo, is received. The instantaneous size of the received signal determines the instantaneous duration of the clock pulses, and hence the gate pulses, which are narrower when larger amplitude echoes occur.

Fig. 4 shows in block form, the principal components of the analyser and the recording and display peripherals with the analyser switched to the simplest operating mode. The main component of the analyser is a group of signal processing channels 10 which receive the echo signals from the component under test. The channels are controlled by a shift register 12 which generates the gate pulses and an adjustable pulse width uniform clock 14 which shifts a logical '1' through the register, the clock being triggered by the top surface echo signal from the component. The logical signal '1' opens the gate of each channel in turn.

The significant data from the channels 10 i.e.

data indicating the presence and size of a flaw are recognised by a data detect circuit 1 6 and cause the data to be passed to a First In First Out (FIFO) memory 18. A the same time the data detect circuit causes the output from a depth counter 20 indicating the depth of any flaw as a number of time slots from the output of the clock 14, to be put into the FIFO memory 18.

The data detect circuit 1 6 also loads scanning co-ordinates into an independent FIFO memory 22. The scanning co-ordinates are obtained from position transducers built into the component scanning system. These co-ordinates will normally be binary or binary coded decimal (BCD) numbers and in the case of the component being a turbine disc, will represent the instantaneous position of the ultrasonic probe in relation to the disc, as the distance from the centre (radius) and rotation from a datum mark (angle). The data detect circuit 1 6 in addition to loading the FIFO memories, also feeds a pulse to a flaw counter 26.

The data from FIFO memory 18 are carried via data buses 28 and 39 to a display 32 and the printer 24 and/or computer 34 which also receive data from the flaw counter 26 via a data bus 36.

The printer and/or computer also receive data from the FIFO memory 22 via a data bus 37. The complete set of data on each flaw comprises size in dB, depth as a number of time slots, radius in mm or inches and angle in degrees which together with the flaw count total, is printed by the printer 24 at the rate of about one line per second. If the display time is set to a different rate, the system allows the printer to work at its own speed, independently of the display.

The FIFO memory 18 is used as a temporary memory to match the possible rapid acquisition from a localised area of the disc to the relatively slow rate needed for display and recording. The capacity of the memory is matched to the likely number of flaws, and in the case of a turbine disc, since only one or two flaws are likely to arise in the worst case, the memory has a capacity to store data on 1 6 flaws. As soon as the flaw data are loaded into the FIFO memory they appear on the display 32 for a time determined by a display time control. At the end of this time, the next set of data in the FIFO memory is displayed and so on.If a group of defects gives rise to a rapid succession of flaw data from the signal processing channels 10, the groups of data are stored temporarily in the FIFO memory and read out to the display at a convenient rate determined by the operator. If the FIFO memory should fill temporarily, or if the operator should miss the flaws on the display 30, the total number of flaws detected can be checked by the flaw count reading on the display.

The display does not show scanning coordinates because there are usually displayed by the disc scanning system, but they are recorded on the printer 24 and/or computer 34.

Referring to Figs. 5, 6 and 7 each signal processing channel 10 comprises a gate circuit 38, a peak sample and hold circuit 40 which includes a capacitor and a unity gain amplifier, an averaging filter 42, a differential amplifier 44, a comparator 46, an analogue-to-digital (A-D) converter 48, and a tri-state buffer 50 the output from which is passed into a data bus connected to the data detect circuit 1 6 and the FIFO memory 18.

The signal processing channels 10 are arranged in parallel and receive in succession, processed echo signals from the component. The echo signals are first attenuated or amplified by a variable gain device 54 which adjusts the level of the signal to that most suitable for a logarithmic amplifier 56 whose output voltage represents the logarithm of its input voltage and, hence represents the input voltage in decibels. The gate circuits 38 of the channels are opened in succession of that each gate can inspect successive parts of the echo signal. The gate circuits are controlled by the shift register 12 which is in turn controlled by the variable uniform clock 14 or by an echo size controlled clock 58.

The clock circuits 14 and 58 have switches to enable either clock to operate the shift register 12. However, the clock 14 will continue to operate the depth counter 20 when the clock 58 is in use.

Both clocks may be triggered by the front wall echo via the interface trigger circuit 59.

Alternatively, both clocks may be triggered by the transmitter pulse after a delay set by delay 60.

The gate signal for a particular gate, from the shift register is also arranged to clear the A-D convertor of that gate and the gate signal from the previous gate is used to clear the peak sample and hold circuit 40 and enables the tri-state buffer 50. The analyser is arranged to receive signals from a flaw detector 62 which may also have an associated oscilloscope 64, and from position indicating devices (not shown) which indicate the position of a probe 66 relative to a component 68 which is immersed in water tank 70.

Each gate circuit 38 enables the associated signal processing channel 10 to examine the ultrasonic echo signal from a thin horizontal section of the disc under test. Fig. 5 shows the waveforms of the signal at various locations along the processing channel. Waveform (i) is the flaw detector's display of the ultrasonic signals, repeated a few times to show the result of changes in the received echoes as the disc spins.

The timebase is shown compressed for ease of presentation.

Waveform (ii) is the displayed gate-pulse waveform.

Waveform (iii) shows only one of the gate pulses, the one which opens the gate in the channel shown in Fig. 5.

Waveform (iv) shows the voltage on the capacitor in the peak sample and hold circuit 40 and is the output of the high input impedance uppity gain amplifier which acts as a buffer. When the gate 38 opens, the capacitor charges to the peak voltage of the ultrasonic signal which occurs during the gate interval. At a, the signal is the 'grass' level and is momentarily of a lower value. The capacitor holds this lower value until the gate opens again, in the next repetition period, at b. At b, the 'grass' level is higher, and this higher level is held until c. At c, a yet higher value is acquired until d. At d, the 'grass' level falls, and a lower value is held until e. At e, a flaw echo occurs, and causes a much higher value to be held until f.

Waveform (v) is the output of the averaging filter 42 which has a time constant of about 0.1 seconds and smooths out the trace to trace variations in signal level, providing an average value of the grass level.

The output of the differential amplifier 44 is the difference between the last signal level held by the peak sample and hold capacitor and the average 'grass' level. All the signal voltages represent the last signal level as dB above the 'grass' level, so the waveform (vi) represents the last signal level as dB above 'grass' level. The relatively small changes in the signal level on waveform (iv) cause the dB above 'grass' level to go slightly negative or positive. This has no effect on the comparator 46.

However, an echo signal sufficiently large to be interpreted as a flaw (e on a waveform (iv)) causes the 'dB above grass' signal to exceed the pre-determined threshold level at the input of the comparator 46 and the comparator then starts the A-D converter 48.

The A-D converter converts the 'dB above grass' level signal into the corresponding 6-bit binary number, and a maximum time of 80 us is taken to perform this operation. Waveform (vii) shows that the A-D converter output is connected to the data-bus via the tri-state buffer 50 for the duration of the gate pulse of the previous channel in the next repetition period. The A-D converter is then available to receive any input from the next cycle.

The ultrasonic probe only moves slowly across the disc face and cross-section changes are seen slowly by the ultrasonic scanning system. Thus even when the disc is positioned eccentrically, it takes a whole revolution to bring a new boundary under the probe, which at the highest testing speeds amounts to a time of the order of 1 second. If a geometry echo occurs in the range of the signal processing channel shown in Fig. 5, the geometry echo has an effect similar to the small changes in grass level shown on section a to d of waveform (iv) in Fig. 5. The echo signal strength only increases slowly and the low pass filter 42 with a time constant of 0.1 seconds, effectively follows the increasing signal strength. Thus the 'dB above grass' signal remains too small to exceed the threshold level, and the geometry echoes are ignored.

The analyser has two input signals, the ultrasonic signal to be processed (VIDEO IN), and a trigger signal (TRIG IN), and three output signals, two of which assist in setting up the operation of the analyser. These are the output of the logarithmic amplifier 56 (VIDEO OUT), and the gate pulses, shown as waveform (ii) on Fig. 6. The third output is the multi-way connection to the printer 24 and/or computer 34.

The signals to be processed are rectified and filtered ultrasonic signals, and are essentially the signals displayed on the oscilloscope screen of the flaw detector.

The TRIG IN input must be a trigger signal synchronous with, or at a small fixed time from, the flaw detector's transmitter output pulse. A trigger pulse occurring shortly before the transmitter pulse can be accommodated by adjustment of the delay control (Fig. 7). A later trigger pulse must occur before the disc topsurface echo, if the echo-triggered gate-pulse mode is to be used.

The VIDEO OUT output can be shown by the oscilloscope 64 together with the GATE PULSES output to check the correct triggering of the gate pulses in relation to the disc front wall echo. The gate pulse width can be set to ensure that the train of gate pulses includes all the ultrasonic signals of interest. The operator can also check that the gain settings on the flaw detector and on the analyser are such that disc flaws will give rise to VIDEO OUT signals with proper dynamic range. The gate pulse width can be set to ensure that the train of gate pulses includes all the ultrasonic signals of interest. The operator can also check that the gain settings on the flaw detector and on the analyser are such that disc flaws will give rise to VIDEO OUT signals with proper dynamic range.

The analyser can be operated in a number of different ways depending upon the objective and the manner of operation is determined by the analyser control settings (Fig. 7).

In the first mode of operation, which has so far been described, the mode control is set to normal, the gate pulse width is set to uniform and the gate pulse triggering is set to echo-triggered. The first gate pulse is triggered by the first echo pulse received at the VIDEO IN input after the trigger pulse at the TRIG IN input. The gate pulses are all of the same duration, the width of which can be set by the gate pulse width control between 100 ns and 1.O,us.

For convenience, the GATE PULSE output should be displayed, together with the ultrasonic signals, on the screen of the flaw detector 62 so that (a) it can be checked that the gate pulses start upon arrival of the top surface echo, and (b) the uniform width control can be adjusted so that the train of gate pulses encompasses all the ultrasonic echoes of interest, and that the gate width is of a value convenient for depth calibration.

Alternatively, the VIDEO OUT and GATE PULSE outputs can be displayed on an oscilloscope 64 so that procedures (a) and (b) can be carried out.

The input gain switch is used to bring the VIDEO OUT SIGNALS within the dynamic range of the analyser. The rotational speed of the component 68 is adjusted so that with the pulse repetition frequency of the flaw detector used, a flaw will be seen at least three times as it passes under the probe.

Flaw echo size will be indicated as dB above the average grass level, provided that this value exceeds the setting of the threshold switch. Each time a flaw is detected, the corresponding flaw depth will be displayed and in this uniform mode, the depth is measured in terms of time slots corresponding to the gate pulses. The flaw will also be added to the flaw count.

In the normal mode the gate pulse triggering can be delayed so that the first gate pulse is triggered after a delay following the TRIG IN trigger pulse. The length of the delay is set by the delay control and the start of the gate pulses can be checked against the ultrasonic signals as before.

Also, in the normal mode, the gate pulse width can be controlled by the echo size, using the echo-size controlled clock 58. Whichever way the first gate pulse is triggered, the gate pulse width is then set by the echo-size controlled width control between the limits of 100 ns and 1.0 ,us.

The width is also affected by the amplitude of the ultrasonic signals, large signals causing the width to decrease, the minimum possible width still being 100 ns.

The sensitivity control and the associated width control are used to adjust the train of clock pulses to encompass all the ultrasonic signals of interest and, at the same time, ensure that narrow gate pulses are generated whenever the relatively large geometry echoes occur. The depth of flaws is still measured in terms of numbers of pulses from the uniform clock.

The analyser can be used to examine the ultrasonic signals in a selected gate or time slot and this is achieved by setting the mode switch to echo signals and selecting the desired time slot or gate number. The analyser will now display only flaws occurring in the selected gate or time slot. If the gate pulse width is uniform, the time slots are identical to the gate numbers, so either can be selected.

If the gate pulse width is echo size contolled, the gate number can be used to select the gate number of the flaw to be displayed. With a flaw at a given depth, its gate number will depend on the size of the echo-size controlled width and sensitivity controls. If a flaw should occur in this gate, its depth will still be displayed in terms of time slots from the uniform clock.

In the embodiment shown in Fig. 8, each channel 10 incorporates digital devices instead of analogue devices and the A-D converter 48 in each channel is removed. The input signals from the flaw detector, after being processed by the input gain 54 pass to an analogue to digital converter 72, prior to passing to each channel 10, so that the signals to the channels are now in digital form.

The components of the channels 10 now comprise a digital register 74 which forms the peak sample and hold circuit, a digital averaging filter 76, a first digital comparator 78, and a second digital comparator 80.

The first digital comparator corresponds to the differential amplifier 44 and receives signals from the register 74 and the averaging filter 76. The output of the first comparator represents the 'dB above grass' level which passes to the second comparator 80 corresponding to the comparator 46, the comparator 80 also receiving the threshold signal from device 45. The 'dB above grass' signal also passes to the tristate buffer 50 which is only enabled by the output of an AND gate 82, the inputs to which are the output from the shift register to the preceding gate circuit and the output from the second comparator 80. Thus, the AND gate will only enable the tri-state buffer to receive the 'dB above grass' signal if there is an output from the second comparator 80, this latter output only occurring if the 'dB above grass' signal exceeds the threshold level. In all other respects, the signal analyser is constructed and operates as shown with reference to Figs. 1 to 7, and previously described.

Although the signal analyser has been particularly described with reference to a turbine disc of a gas turbine engine, it can be applied to other engineering components in which there is a change in section.

Claims

1. A signal analyser comprising a plurality of signal processing channels, each channel of which is arranged to receive the signals to be analysed via a gating means, all the gating means being operable by a gating control to allow the signal to be analysed by each channel to pass to the signal processing channels in sequence, each channel including a hold circuit arranged to receive and hold the peak value of the signal in the respective time gate, an averaging filter arranged to receive the output from the hold circuit, a first comparator arranged to receive the outputs from the hold circuit and the averaging filter, the output from the first comparator being passed to a second comparator which also receives a threshold level signal, the output from the second comparator being used to determine whether or not the signal from the first comparator is significant, and if so to record the output of the first comparator.

2. A signal analyser as claimed in claim 1 arranged to analyse the signals generated by an ultrasonic flaw detector in the testing of an engineering component in which in each of the signal processing channels, the output of the averaging filter represents the average 'grass' level in the respective processing channel, the output of the first comparator represents the difference between the last signal level held by the hold circuit and the average 'grass' level, and the output of the second comparator represents whether or not the output from the first comparator has exceeded the threshold level.

3. An analyser as claimed in claim tor claim 2 in which the gating control comprises at least one clock circuit actuated by a trigger pulse, the clock circuit emitting gate pulses to a shift register which opens the gate of each processing channel in sequence, the time for which each gate is held open being determined by the width of the gate pulses generated by the clock circuit.

4. An analyser as claimed in claim 2 having at least two clock circuits, the gate pulse width generated by one of the clock circuits is uniform for all of the channel gating means, and can be pre-set between limits depending upon the number of channels available, the thickness of the component being examined, and the smallest width of the signal which needs to be examined.

5. An analyser as claimed in claim 3 in which the gate pulse width generated by the other one of said clocks is echo-size controlled and varies depending upon the size of the echo signal from the component so that in the region of geometry echo the gate pulse width narrows enabling each processing channel to examine a shorter duration of the echo signal in the region of a sharp change of thickness in the component, the uniform clock still being used to measure the depth of the flaw via a counter circuit.

6. An anlayser as claimed in claim 4 or claim 5 having switching means enabling both clocks to receive trigger pulses from the transmitted signals of the flaw detector via a delay, or from the echo signals from the flaw detector, and the input to the shift register to be selected from the outputs of the two clocks.

7. An analyser as claimed in any one of the preceding claims in which the signal from the gating control to one signal processing channel is arranged to clear the signal held in the hold circuit of the next succeeding signal processing channel.

8. An analyser as claimed in any one of the preceding claims in which the digital data generated by each channel is passed via a tristate buffer, to a visual display and/or a printer and/or a computer via one or more data buses.

9. An analyser as claimed in claim 18 in which the signal from the gating means is arranged to enable the tri-state buffer of the next succeeding processing channel.

10. An analyser as claimed in any one of the preceding clams in which the hold circuit comprises a capacitance circuit, the first comparator comprises a differential amplifier, and the second comparator comprises an analogue comparator.

11. An analyser as claimed in claim 9 in which the capacitance circuit includes a capacitor and a buffer.

12. An analyser as claimed in claim 10 or claim 11 in which the signal from the gating means to one processing channel is arranged to clear the A D converter of the same processing channel.

13. An analyser as claimed in any one of the preceding claims 10 to 12 in which the signals to be analysed are processed by a variable attenuator-amplifier and a logarithmic amplifier prior to being examined by each of the signal processing channels.

14. An analyser as claimed in any one of the preceding claims 1 to 9, in which the hold circuit comprises a digital register and the first and second comparators are each digital comparators.

1 5. An analyser as claimed in claim 12 in which the output from the second comparator passes to a logic switching device, the output from which enables a tri-state buffer to receive the output from the first comparator, if the first comparator output exceeds the threshold level.

16. An analyser as claimed in claim 1 5 in which the logic switching device comprises an AND gate having an input signal from the gating control of the preceding signal processing channel.

17. An analyser as claimed in claim 14 in which the signals to be analysed are processed by a variable attenuator-amplifier and an analogue to digital converter prior to being examined by each of the signal processing channels.

17. An analyser as claimed in any one of the preceding claims 12 to 14 in which the signals to be analysed are processed by a variable attenuator-amplifier and an analogue to digital converter prior to being examined by each of the signal processing channels.

1 8. A signal analyser constructed and arranged for use and operation substantially as herein described, and with reference to Figs. 1 to 7, and Fig. 8 of the accompanying drawings.

New claims or amendments to claims filed on 13 January 1983.

Superseded claims 1-17.

New or amended claims:

3. An analyser as claimed in claim 1 in which the gating control comprises at least one clock circuit actuated by a trigger pulse, the clock circuit emitting gate pulses to a shift register which opens the gate of each processing channel in sequence, the time for which each gate is held open being determined by the width of the gate pulses generated by the clock circuit.

5. An analyser as claimed in claim 4 in which the gate pulse width generated by the other one of said clocks is echo-size controlled and varies depending upon the size of the echo signal from the component so that in the region of a geometry echo the gate pulse width narrows enabling each processing channel to examine a shorter duration of the echo signal in the region of a sharp change of thickness in the component, the uniform clock still being used to measure the depth of the flaw via a counter circuit.

6. An analyser as claimed in claim 4 having switching means enabling both clocks to receive trigger pulses from the transmitted signals of the flaw detector via a delay, or from the echo signals from the flaw detector, qnd the input to the shift register to be selected from the outputs of the two clocks.

7. An analyser as claimed in claim 1 in which the signal from the gating control to one signal processing channel is arranged to clear the signal held in the hold circuit of the next succeeding channel.

8. An analyser as claimed in claim 1 in which the digital data generated by each channel is passed via a tri-state buffer, to a visual display and/or a printer and/or a computer via one or more data buses.

9. An analyser as claimed in claim 8 in which the signal from the gating means is arranged to enable the tri-state buffer of the next succeeding processing channel.

10. An analyser as claimed in claim 1 in which the hold circuit comprises a capacitance circuit, the first comparator comprises a differential amplifier, and the second comparator comprises an analogue comparators

11. An analyser as claimed in claim 10 in which the capacitance circuit includes a capacitor and a buffer.

12. An analyser as claimed in claim 1 in which each signal processing channel includes an analogue to digital converter arranged to receive the output from the first comparator when the converter is enabled by the output from the second comparator, the signal from the gating means to one processing channel being arranged to clear the analogue to digital converter of the same processing channel.

13. An analyser as claimed in claim 1 in which the signals to be analysed are processed by a variable attenuator-amplifier and a logarithmic amplifier prior to being examined by each of the signal processing channels.

14. An analyser as claimed in claim 1 in which the hold circuit comprises a digital register and the first and second comparators are each digital comparators.

1 5. An analyser as cliamed in claim 14 in which the output from the second comparator passes to a logic switching device, the output from which enables a tri-state buffer to receive the output from the first comparator, if the first comparator output exceeds the threshold level.

1 6. An analyser as claimed in claim 1 5 in which the logic switching device comprises an AND gate having an input signal from the gating control of the preceding signal processing channel.