JPS58151556A - Analyzer for signal from ultrasonic defect detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the processing and analysis of electrical signals generated by ultrasonic defect detection devices used for non-destructive testing of technical components, in particular turbine discs of gas turbine engines. Regarding analysis equipment for

Internal defects, which are substantial weaknesses in the material structure of such components, occur during processing of the green material, during manufacture of the component, and during the service life of the construction requirements. Detection of such defects is important, especially in highly stressed components such as turbine disks. If the location and size of such defects are known, then modern methods of fracture engineering can be used to determine predictions of component service life with considerable accuracy.

A common method for non-destructively testing turbine disks for internal defects is to immerse the disk in a water bath, rotate the disk, and use ultrasonic waves emitted from an ultrasonic probe that moves slowly over the disk. It's about giving a shock.

Each impact is reflected by the component as a series of echoes consisting of echoes from the front and rear of the component, i.e. echoes of different intensities from the grain structure of the component, called grass echoes. However, if this impact were to be fired at a defect, there would be an echo corresponding to this defect. The size of the defect is related to the size of the corresponding echo. If the impact is fired within the region of a change in the cross-section of the component, further echoes, also referred to as "regular echoes", will occur in this case.

All these echoes are displayed on the screen.

The operator must be aware that when this defective point is passed through the probe, the echo is momentarily higher than the level of the forest echo and disappears again. The most important case is when a defect occurs in a region of change where the defect echo is masked by the regular echoes. For example, the defect echo signal is at the trailing edge of a relatively large regular echo signal. It can occur instantaneously. Visual detection of such defects requires prolonged attention span,
Requires experience and familiarity with pattern recognition methods. Even a momentary loss of focus can mean a defect passes undetected.

In particular, the present invention provides a method for detecting defects from components subjected to non-destructive testing with ultrasound, in which the magnitude and location of defect echoes in regions of cross-sectional variation are displayed and recorded without the need for continuous visual inspection of the echo signals. The present invention aims to provide a device that processes and analyzes signals generated by echoes.

According to the invention, there is provided a signal analysis device comprising a plurality of signal processing channels, each channel of which is arranged to receive the signal to be analyzed via a gating device, all of said gating devices being connected to a series of Each channel is operable by a gate control to allow analysis of multiple signals;
Each channel includes a holding circuit configured to receive and hold the peak value of the signal at each time gate, an averaging filter configured to receive an output from the holding circuit, and the holding circuit and the averaging filter. a first comparator configured to receive an output from the first comparator;
The output of this first comparator is sent to a second halator which also receives the threshold level signal and the output from the second comparator determines whether the first comparator's signal is significant. and, if so, to record the output of the first comparator.

The output from the second comparator is an analog/digital (A/D) signal that allows converting this output into digital form if the output of the first comparator is higher than a preset threshold level. It can be sent to the converter. The converted data is sent via a three-state buffer to a data bus that is connected to a first-in-first-out (FIFO) memory from which data can be sent to a visual display and printer and/or data bus. can be sent to a computer for analysis.

The signal analyzer is in particular a device for analyzing the echo signals generated by an ultrasonic defect detection device in which regular jolts of ultrasonic energy are directed against a technical component for inspection purposes. It is something.

The input signals to the analysis device include echo signals from the components, and these signals are preferably processed by a variable attenuator and a logarithmic multiplier before being sent to a signal processing channel via a gating device.

The gating device consists of a variable clock circuit and a shift register that provides a gate pulse of a selected width, the clock circuit being clocked by a pulse produced by a defect detection device via a delay circuit, or alternatively directly by the component under test. It is energized by the front wall echo signal from the front wall. This clock circuit.

The gate pulse may be of uniform width, the width of which can be varied by the operator, or the width of the gate pulse may be narrowed so that the regular echoes can be closely examined. The pulses can also be obtained from a second clock circuit whose width can depend on the echo signal.

The output from the first comparator is the “forest echo” mentioned above.
represents a signal in decibels (dB) above the level of
If the signal is above the threshold level, the second comparator recognizes the signal as a defective signal and causes the A/D converter to convert the signal to digital form. This defect size data together with the depth of the defect in the form of pulse numbers from the uniform clock circuit.

FIFO memory, visual display and sent to printer and/or computer. This visual display and printer.

and/or sent to a computer.

visual display and printer, and/or
The computer also receives data representing the total number of defects formed, and the printer and/or combinator receives data from the test equipment's mechanical scanning system representing the location of the defects.

Each signal processing channel consists of analog or digital elements, in the case of analog form it includes first and second comparator differential amplifiers and an analog comparator, and the holding circuit includes a capacitive circuit rich in capacitors and buffers. There is.

In the digital form, the comparators are both digital comparators, the holding circuit includes digital registers, and a single A/D converter replaces the converter in the signal processing channel, and for each processing channel. The input signal from the defect detection device is configured to be transformed before being sent.

The invention will now be described in more detail with reference to one drawing.

FIG. 1 shows a graph of the types of echoes received from a component with a cross-sectional change. Signals A and B are echo signals received from the front and rear walls of the component, and signal C
There are signals from areas of cross-sectional change known as regular echoes, and signals representing background echoes from the particle structure of the constituent elements known as "forest echoes".

FIG. 2 shows on a magnified scale the trailing edge of a relatively large damped oscillation train of four regular echoes C. Current defect location methods require the observer to identify this defect, t, as an extra signal that suddenly appears in this vibration train, as shown in FIG. Today's signal analysis devices offer to examine regular echo signals passing through a series of gates of various time durations. FIGS. 2 and 3 together illustrate the effect of using different gate-pulse widths.

In FIG. 2, a wide gate-pulse of duration tl is shown as one of the regular echo oscillations.

In FIG. 3, for gates of the same duration, the peak signal is the same as in FIG. This is because it is low.

FIG. 2 also shows an example of operation with a narrow gate pulse of duration t, in which the peak signal in the gate is the next relatively low cycle of regular echoes. In FIG. 6, when the defect echo E rises above the value at the narrow gate in FIG. If exceeded, defects will be recognized and recorded.

As explained in detail below, one analyzer uses narrow gate pulses with a duration of about 100 ns in the region of regular echoes and other gate Φ pulses of wider width. If no substantial echoes, e.g. regular echoes, are received, the operator can control the clock to control the width of the gate pulse, the amplitude of the echoes to produce pulses of uniform lock or predetermined duration. You can choose to use one of two clock generators. The instantaneous magnitude of the received signal determines the instantaneous duration of the clock pulse, and hence the narrow gate pulse, at which the large amplitude knee Z- occurs.

FIG. 4 shows, in block diagram form, the main components of one analyzer and the recording and display peripherals that switch the analyzer to its simplest mode of operation. The main component of the analyzer is a group of signal processing channels 10 which receive echo signals from the component under examination. This channel is a shift register 12 that generates two gate pulses.
and a variable pulse width uniform clock 14 that converts a logical ``1'' through this register, which clock is D) triggered by the highest surface echo signal from the component. A logic "1" opens the gates of each channel alternately.

Important data from channel 10, such as data indicating the presence and size of a defect, is recognized by data detection circuit 16 and sent to a first-in-first-out (FIFO) memory 18. At the same time, this data detection circuit causes the FIFO memory 18 to receive the output from the depth counter 20 which indicates the depth of any defect as a number of time slots from the output of the clock 14.

The data detection circuit 16 also includes: Scan coordinates independent FIF
Load into O memory 22. The scan coordinates are obtained from a transducer located within the component's scanning system. These coordinates are usually binary or binary coded decimal (BCD) numbers, and if the component is a turbine disk, the distance from the center (radius) and the rotation (angle) from the data mark. ) will represent the instantaneous position of the ultrasound probe with respect to the disk. In addition to loading the FIFO memory described above, the data detection circuit 16 sends pulses to the defect counter 26.

Data from FIFO memory 18 is transferred to data bus 2.
8. Display 32 and printer 24 via 59
．． and/or sent to computer 64;
These also receive data from defect counter 26 via data bus 66. Also printers and/or computers. Data is received from FIFO memory 22 via data bus 67. The complete set of data for each defect is size in dB, depth in number of time slots, radius in 1111 units or inches.

and angles in units, which are printed by the printer 24 at a rate of one line per second, along with the total defect count. If the display time is set to a different speed, the screw stem allows the printer to operate at its own speed independent of the display.

FIFO memory 18 is used as a temporary memory to match the speed of different limits from a limited area of the disk with the relatively slow speed required for display and recording. The capacity of this memory is matched to the approximate number of defects, and in the case of turbine disks, even just one or two defects can lead to catastrophe.
This memo 11- has a capacity to store data regarding 16 defects. Once defective data is loaded into this FIEO memory, it will appear on display 62 for a period of time determined by the display time controller. At the end of this time, the next set of data in the FIFO memory is displayed, and so on. If a group of defects results in a fast sequence of defective data from the signal processing channel 10, this group of data is temporarily stored in a FIFO memory and read out to the display at a convenient rate defined by the operator. If the FIEI memory is temporarily full or the operator overlooks defects on the display 32, the total number of defects detected can be verified by reading the defect count on the display.

The display does not show the scan coordinates since they are normally displayed by the disk scanning system.

The coordinates are recorded at printer 24 and/or computer 54.

5, 6 and 7, each signal processing channel 10 includes a gate circuit 38, a capacitor, a direct-coupled gain amplifier, an averaging filter 42, a differential amplifier 44, a comparator 46, and an analog/digital (A /D )・Converter 48 and its output are connected to data detection circuit 16 and FIF
3 sent to the data bus connected to O memory 18
It includes a peak sample and hold circuit 40 including a state buffer 50.

Signal processing channels 10 are arranged in parallel and sequentially receive processed echo signals from the components.

The echo signal is first passed through a variable gain element 5 which adjusts the level of the signal to the most suitable level for the logarithmic amplifier 56.
However, it is attenuated or amplified by 4.

the output voltage of the amplifier represents the logarithm of its input voltage;
It therefore represents the input voltage in dB. The gate circuits 38 of the channels are opened sequentially so that each gate can examine successive portions of the echo signal. This gating circuit is controlled by a shift register 12 which is further controlled by a variable equalization clock 14 or by a clock 58 which controls the magnitude of the echo. Clock circuits 14 and 58 have switches that allow any clock to operate shift register 12. However, equalization clock 14 will continue to run depth counter 20 while clock 58 is in use.

Both clocks are connected to the interface trigger circuit 5
9 can be triggered by the front wall echo. Alternatively, both clocks can be input to the delay circuit 60.
It can also be triggered by the transmitter after a set delay.

The gate signal for a particular gate from the shift register is also configured to clear the A/D controller of this gate, and the gate signal from the previous gate clears the peak sample and hold circuit 40. is used to enable the three-state buffer 50. The analyzer also receives the probe 66 from the defect detection device 62, which also has an associated oscillation fi 64, and to a component 68 immersed in the water tank 70. It is configured to receive signals from a position indicating element (not shown) that indicates position.

Each gating circuit 38 allows an associated signal processing channel 10 to examine ultrasound echo signals from a horizontal thin section of the disk under examination. FIG. 6 shows the waveforms of the signals at various locations along the processing channel. Waveform (1) is a defect detector image of the ultrasound signal repeated several times to show the result of changes in the echoes received as the disk rotates. Time references are shown condensed for ease of display.

Waveform (11) is the waveform of the displayed gate pulse.

Waveform (iii) shows the only gate pulse that opens the gauge in the channel shown in FIG.

The waveform (which shows the voltage across the capacitor in the peak-to-peak sample and hold circuit 40) is the output of a direct-coupled gain amplifier with a large input impedance that acts as a buffer.

When gate 38 opens, the capacitor charges to the peak voltage of the ultrasound signal occurring in the gate interval. At point a, the signal is at a "forest echo" level and momentarily drops to an even lower value. The capacitor holds this relatively low value until the gate is opened again during the first repetition period. At point C, the "forest echo" level is relatively high, and this relatively high level is maintained up to point C. At point C, an even higher value is reached by point d. At point d, the "forest echo" level decreases and is maintained at a relatively low value until point 6 e. A defective echo occurs at point e.

A much higher value is maintained up to point f.

The waveform (V) has a time constant of approximately 0.1 seconds and is passed through an averaging filter 42 that smooths the trajectory to track fluctuations in signal level, resulting in an average value of the "forest echo" level.
This is the output of

The output of differential amplifier 44 is the difference between the last signal level and the average "forest echo" level held by the peak sample and hold capacitor. All signal voltages represent the last signal level in dB years above the "forest echo" level, and thus the waveform (vDi [forest echo] represents the last signal level in dB years above the level. Waveform ( 1
Relatively small changes in signal level at ψ cause the dB above the "forest echo" level to become slightly negative or positive. Therefore, no effect occurs on the comparator 46.

However, the echo signal (
The waveform (e in step 1) is “dB higher than the forest echo”.
The comparator then triggers the A/D converter 48, causing the dB e above the j signal to exceed a predetermined threshold level at the input of the converter 46.

The A/D converter converts the dBJ level signal higher than the forest echo into a corresponding 6-bit binary number.

It takes a maximum of 80 microseconds to perform this operation. The waveform (vl) shows that the output of the A/D converter is connected to the data node through the six-state buffer 50 during the gate pulse of the previous channel in the next repetition period. The A/D controller is now available to receive any input from the next cycle.

The ultrasound probe is moved slowly across the surface of the disk, and changes in the cross section are slowly indicated by the ultrasound scanning system. Even when the disk is electrically positioned in this way, it takes one complete revolution, at the fastest speed, on the order of one second to establish a new boundary below the probe. If the regular echoes occur within the signal processing channel shown in Figure 5, the regular echoes will be at the "forest echo" level shown in cross sections a to d of waveform (1v) in Figure 5. Produces an effect similar to a small change. The strength of this echo signal increases only gradually and the low pass filter 42, which has a time constant of 0.1 seconds, effectively tracks the increasing signal strength. Thus, dBJ signals higher than forest echoes remain just too small to exceed the threshold level, and regular echoes are ignored.

The analyzer has two input signals: the ultrasound signal to be processed (VIDEOIN) (!:) and the trigger signal (TRIGI).
N) and six output signals, two of which help configure the operation of the analyzer. These are the output of the logarithmic amplifier 56 (VI
DEO0UT) and gate pulse. The third output is the printer 24 and [or] combination, - 34
This is a multipath connection for

The signal to be processed is a rectified and filtered ultrasonic signal, substantially the signal displayed on the screen of the oscilloscope of the defect detection device.

The input signal TRIP IN must be a trigger signal synchronized with the output pulse of the transmitter of the defect detection device, or a trigger signal after some short fixed time. A trigger pulse occurring slightly before the transmitter NO pulse is enabled by adjustment of the delay control (FIG. 7).

A relatively large trigger pulse must occur before the echo of the top surface of the disk if an echo-triggered gated pulse mode is used. In addition, in FIG. 7, each symbol has the following meaning.

D: Delay ES: Echo signal ESC: Controlled echo signal ET Nidorigaed Echo GNo, Nige-)No.

N: Normal S: Reactivity T: Test signal TS: Time slot U: Uniform W: Width VIDEOOUT output is 0. Oscillator 6 with the output GATE PULSES is used to check the proper triggering of the gate pulses associated with the front wall echo of the disk.
4 can be shown. The width of this gating pulse can be set to ensure that the gating pulse train contains all the ultrasound signals of interest. Operator also.

This gate pulse width allows the gain settings in the defect detection and analysis equipment to be such that a disc defect produces a signal VIDEOOUT within the correct dynamic range. It can be set to ensure that the ultrasound signal of interest is included. Operator also.

Are the gain settings in the defect detection and analysis equipment such that a defect in the disk produces a signal VIDEOOUT in the correct dynamic range? It can also be inspected.

The analyzer can be operated in many different ways depending on the purpose, and the manner of operation is determined by the settings of the analyzer (FIG. 7).

In the first mode of operation described so far.

The mode control is set to normal, the width of the gate pulse is set to equal, and the triggering of the gate pulse is set to trigger by echo. The first gate pulse is the trigger signal at the TRIG IN input.
Triggered by the first echo pulse received at input VIDEOIN after the pulse. The gate pulses are all of the same duration and have a width of 100
It can be set within the range of ns to 1.0 μsec by controlling the gate pulse width.

For convenience, (a) to be able to check that the gate pulse starts simultaneously with the arrival of the top echo;

(b) so that the gating pulse train can be adjusted to cover all ultrasound echoes of interest.

The GATE PULSE must also be displayed on the screen of the defect detection device 62 along with the ultrasonic signal so that the width of the gate is a convenient value for depth calibration. Alternatively, the output VIDEOOUT and GA
TE PULSE can be displayed on the oncilloscope 64 so that steps (a) and (b) above can be performed.

Place the signal VIDEOOUT within the screen dynamic range of one analyzer using the input gain switch. The rotational speed of component 68 is adjusted such that, at the pulse repetition frequency of the defect detection device used, the defect is presented at least three times as it passes under the probe.

Defect echoes exceed the average "forest echo" level, assuming this value exceeds the threshold switch setting.
It will be displayed as B.

Each time a defect is detected, the depth of the corresponding defect is displayed, and in this uniform mode, this depth is
Measured in time slots corresponding to pulses. Defects will also be added to the defect count.

In the normal mode, the triggering of the gate pulse can be delayed such that the first gate pulse is triggered after a certain amount of delay following the trigger pulse TRIG IN K. The length of this delay is set by a delay controller.

The onset of the gate pulse can be checked against the ultrasound signal as described above.

Also, in normal mode, the width of the gate pulse is
The echo size can be controlled using an echo size control clock 58.

Regardless of how the first gate pulse is triggered, the width of the 7 gate pulses ranges from 100 ns to 1.0 ns.
The width is set at this time by the width controller, which is controlled by the magnitude of the echo in microseconds. Is this width also affected by the amplitude of the ultrasound signal? Larger signals reduce this width, and the shortest width is still 100 ns.

A sensitivity control and an associated width control are used to adjust the clock pulse train to cover all the ultrasound signals of interest, while at the same time applying a narrow gate pulse each time a relatively large regular echo occurs. Ensure that it is generated. The depth of the defect is still measured relative to the number of pulses from the lock.

The analyzer can be used to examine the ultrasound signal at a selected gate or time slot, and this can be done by setting the mode switch to the echo signal and at the desired time slot or gate. This is accomplished by selecting a number. The analyzer will now only display defects that occur in the selected gate or time slot. If the gate
If the pulse widths are equal, this time slot must be the same as the gate number, so any of them can be selected.

If the gate pulse width is controlled by the size of the echo, the gate number switch can be used to select the gate number of the defect to be displayed.

For a given depth defect, the gate number will depend on the width size, which is controlled by the echo size, and will depend on the sensitivity control. If some defect occurs in this gate.

The depth will still be displayed evenly in terms of time slots from the lock.

In the embodiment shown in FIG.
incorporates digital elements instead of analog elements, and the A/D converter 48 in each channel is eliminated. The input signal from the defect detection device is processed by the input gain device 54 and then sent to each channel 10.
/D converter 72, so that the signal for the channel is now in digital form.

In this case, the components of channel 10 are a digital register 74 forming a peak sample and hold circuit, and a digital averaging filter 76.

It consists of a first digital comparator 78 and a second digital e-comparator 80.

A first digital comparator corresponds to a different amplifier 44 and receives signals from a register 74 and an averaging filter 76. The output of the first comparator is sent to a second comparator 80 corresponding to comparator 46.
Digital comparator 80 also receives a threshold signal from element 45, representing a higher dB j level signal than the forest echo.

The higher dBJ signal than the forest echo is also enabled only by the AND gate 82, which is a three-state buffer 5.
0, and the input to this gate is the shift
Output from the register to the previous gate circuit and the second
This is the output from the comparator 80. Thus, if only this AND gate and the output from I-digital comparator 80 are present, then the six-state buffer is
This makes it possible to receive a dBj signal higher than the forest echo, and the output of this comparator will only occur if a dBJ signal higher than the forest echo exceeds the threshold level. In all other respects.

The signal analysis apparatus is constructed and operative as shown and previously described with respect to FIGS. 1-7.

This signal analyzer has been specifically described with respect to the turbine disk of a gas turbine engine.
The analysis device can also be applied to other technical components where variations in cross section are present.

[Brief explanation of drawings]

Fig. 1 is a typical echo graph showing the relationship between the amplitude of the echo signal and time; Fig. 2 is an enlarged echo φ graph showing a state in which a cross-sectional change of the constituent capacitance occurs in the absence of a defective signal;
FIG. 6 is a graph similar to FIG. 2 in the presence of a defective signal, FIG. 4 is a block diagram showing an embodiment of the signal analysis device according to the present invention, and FIG. 5 is an analysis shown in FIG. 4. A block diagram showing one of the analog signal processing channels of the device, FIG. 6 is a graph showing signal waveforms at each stage in the channel shown in 5, and FIG. FIG. 4 is a configuration diagram showing the analyzer, and FIG. 8 is a block diagram showing the digital form of the signal processing channel shown in FIG. DESCRIPTION OF SYMBOLS 10... Signal processing channel, 12... Shift register, 14... Equal clock, 16... Data detection circuit, 18... FIFO memory, 20... Depth counter, 22... FIFO memory, 24... printer. 26...Defect counter, 28...Data bus, 5
0...Depth counter, 62...Display, 34
...computer, 66...data bus, 67.
...Data bus, 68...Gate circuit, 39...
data bus. 40...Peak sample and hold circuit, 42...Averaging filter, 44...Differential amplifier, 46...Comparator, 48...Analog/digital (A/D)
・Converter, 50... 3-state buffer, 54...
Variable gain element, 56... Logarithmic amplifier, 58... Clock. 59...Interface/trigger circuit, 60...
- Delay circuit, 62... Defect detection device, 64... Oscillator. 66...brouf, 68...constituent element, 70...
Water tank, 72... A/D converter, 74... Digital register, 76... Digital averaging filter. 78...Digital comparator, 80...Digital comparator. Patent applicant Robus Royce Limited [4 others]

Claims (1)

Claims: (11) providing a plurality of signal analysis channels each configured to receive a signal to be analyzed via a gating device; Each channel has a holding circuit configured to receive and hold the peak value of the signal at each time gate, and the holding circuit. an averaging filter configured to receive an output from the holding circuit and a first comparator configured to receive an output from the holding circuit and the averaging filter;
an output from the first comparator is sent to a second comparator that also receives a threshold level signal;
The output from the second comparator is used to determine whether the signal from the first comparator is significant and, if so, is used to record the output of the first comparator. signal analyzer. (2) configured to analyze the indicated signal generated by the ultrasonic defect detection device during the inspection of technical components, and in each of said signal processing channels the output of the averaging filter is determined by the average the output of the first comparator represents the difference between the last signal level held by the holding circuit and the average "forest echo" level, and the output of the second comparator 2. The signal analysis device according to claim 1, wherein the signal analysis device indicates whether the output from the first comparator exceeds the threshold level. (3) The gate circuit includes at least one clock circuit activated by a trigger pulse. The clock circuit issues a gate Φ pulse to the shift register which sequentially opens the gate if of each processing channel;
2. The signal analysis device of claim 1, wherein the period during which each gate is held open is determined by the width of a gate pulse generated by said clock circuit. (4) having at least two clock circuits, the width of the gate pulse generated by one of said clock circuits is equal for all channel gate devices, and the width of the gate pulse generated by one of said clock circuits is equal to the number of available channels; 3. Signal analysis device according to claim 2, characterized in that it can be preset within limits depending on the thickness of the component and the smallest width of the signal that needs to be examined. (5) In regions of regular echoes, the width of the gate pulse is narrowed to allow each processing channel to examine relatively short periods of echo signals in regions of large thickness variations in the component. so that the width of the program generated by another one of said clocks is controlled by the echo size and varies according to the size of the echo signal from said component, and the equal lock still controls the counter circuit. 5. The signal analysis device according to claim 4, wherein the signal analysis device is used to measure the depth of a defect through a sensor. (6) enabling both clocks to receive trigger pulses from the transmitted signal of the defect detection device through a delay circuit or from an echo signal from the defect detection device;
5. Signal analysis device according to claim 4, further comprising a switching device which allows the input to the shift register to be selected from the outputs of the two clocks. (7) The signal according to claim 1, wherein the signal from the gate control device for one signal processing channel is configured to clear the signal held in the holding circuit of the next channel. Analysis equipment. (8) Digital data generated by each channel is sent via a six-state buffer to a visual display and/or printer and/or computer over one or more data buses. A signal analysis device according to claim 1, characterized in that: (9) the signal from the gate device is configured to enable a three-state buffer of a subsequent processing channel; The signal analysis device according to claim 8, wherein the OQ holding circuit comprises a capacitor circuit, the first comparator comprises a differential amplifier, and the second comparator comprises an analog comparator. The signal analysis device according to claim 1, wherein αυ The signal analysis device according to claim 10, characterized in that the capacitor circuit includes a capacitor and a buffer. a channel configured to receive an output from the first comparator when it is enabled by a signal from the second comparator;
2. Signal analysis device according to claim 1, characterized in that the signal for one processing channel from the gating device is arranged to clear the analog-to-digital converter of the same processing channel. 03) Before being examined by each signal processing channel. Claim 1, characterized in that the signal to be analyzed is processed by a variable attenuation amplifier and a logarithmic amplifier.
The signal analysis device described in Section 1. (14) The signal analysis device according to claim 1, wherein the holding circuit includes one digital register, and the first and second comparators are each digital comparators. 05) The output from said second comparator is sent to a logic switching element whose output is equal to the output of said first comparator color if the output of said first comparator exceeds said threshold level. 15. The signal analysis device according to claim 14, wherein the signal analysis device allows a five-state buffer to receive a signal. 16. The signal analysis device according to claim 15, wherein the logical switching element includes an AND gate having an input signal from a gate control of a preceding signal processing channel. 15. Signal analysis device according to claim 14, characterized in that the signal to be analyzed is processed by a variable attenuation amplifier and an analog/digital converter before examination by each signal processing channel.