GB2148638A - A/D converters - Google Patents

Abstract

Analog signals, particularly those obtained from ultrasonic testing equipment, are converted into digital form by converters 800-804, and subsequently into logarithmic form by a coder 840, this arrangement being cheaper and having certain advantages compared with logarithmically- graduated converters. Converters 800-804, which are each of the simultaneous comparison type, are supplied by amplifiers 810-814 with signals within respective ranges that overlap. The upper ten stages of one 64-stage converter may for example be overlapped by the lower ten stages of the next converter. <IMAGE>

Description

SPECIFICATION Processing analog signals It is often necessary to convert analog signals into digital form, or into digital logarithmic form. One example is in the field of nondestructive ultrasonic testing in which an analog signal obtained from a test probe is so converted for evaluation and/or display.

A known approach to the problem of analog-digital conversion has been to supply an analog signal to a number of analog/digital (A/D) converters arranged in parallel, the converters being preceded by amplifiers which modulate the individual converters substantially uniformly, see for example Federal German OS 29 39 617. By using a number of A/D converters, analog signals can be digitalised over a practically unlimited dynamic range (i.e. the ratio of the largest to the smallest signal to be digitalised). In order to convert an analog signal into digital logarithmic form, the stages of the individual A/D converters are graduated in a logarithmic rather than linear manner.

The main disadvantage of these known circuits for digital analog conversion is the relatively high cost of the A/D converters which produce a logarithmic output directly. In contrast to linearly graduated A/D converters, logarithmic A/D converters operating at a high conversion rate (e.g. with scanning frequencies in the 100 MHz range) are not commercially obtainable and must be specially manufactured for each application.

Also, the circuit arrangements used in ultrasonic devices for non-destructive testing of materials have a maximum conversion rate of the same order as the signal frequency, namely a few MHz. In order to operate at this rate, which is too low for satisfactory operation, the scanning of the analog signals has to be timed so that the peak value of each signal is dependent on the shape of the signal and frequently inadequate.

The present proposal, therefore, is for a simple and inexpensive circuit arrangement for converting analog signals to logarithmic digital form, the dynamic range and resolution corresponding to that of known (and much more expensive) circuit arrangements. Another aspect of the present proposal is the conversion of analog signals into a form in which conversion to logarithmic form may be readily carried out. Briefly stated, the present proposal is that the signals to be digitalized be supplied to a number of analog-digital converters (A/D converters) preceded by amplifiers, the gain of the individual amplifiers being so chosen that the dynamic ranges of each A/D converter overlaps that of at least one other. A coder connected downstream of the A/D converters may then be used for converting to logarithmic form the digital signals obtained from the A/D converter.It will be appreciated that the final conversion may be made into some other digital, non-linear form instead of into logarithmic form.

Accordingly, commercially available linearlygraduated A/D converters may be used to digitalize the analog signals, after which the digital signals are converted to logarithmic form using the coder. The resolution of this circuit arrangement is made equal to that of existing logarithmically graduated A/D converters by choosing the gain of the individual amplifiers so that the dynamic ranges of the A/D converters are adjacent one another and overlap.

The circuit can be used for A/D conversion of high-frequency signals over a dynamic range of at least 80 dB and with a conversion rate in the 100 MHz region. This avoids the expense of timing for scanning the analog signals in conventional circuits.

The circuit may with particular advantage be used in or in association with ultrasonic devices, the large dynamic range avoiding the need for manual adjustment of the input signal level. This fulfills an important precondition for complete automation of data acquisition and data evaluating units, as is particularly necessary in ultrasonic devices.

Because commercially available linear A/D converters in the form of monolithically integrated circuits can be used, the construction of the overall functional unit becomes so compact that it can be incorporated on a double European board. The circuit is much easier to adjust, since the monolithic converters are already individually adjusted and constructed to exact specifications.

The resulting accuracy and linearity is much greater than obtainable with analog logarithmic amplifiers or conventionally constructed logarithmically graduated A/D converters, since full use may be made of the advantages of monolithic technology in which all circuit elements are produced on a crystal in a common manufacturing process, e.g. uniform temperature variation and other tolerances in the same direction.

Another advantage of using linear A/D converters is that the linear digitalized signal obtained as a preliminary step to obtaining a logarithmic signal can be processed directly in a linear form to produce graphic images on a VDU or for other purposes. In the case of direct logarithmic converters, it is necessary to carry out a computerized reconversion of logarithmic into linear values in order to provide a suitable signal for visual display. The obtainable resolution on the linear scale is very coarse, since it is limited by the logarithmic jump between stages.

As appears from the foregoing, the proposed circuit has particular advantages in the field of ultrasonic testing, in which context it will now be described with reference to the drawings, in which: Figure 1 is a block circuit diagram of an ultrasonic non-destructive testing device using the proposed circuit; Figure 2 is a block circuit diagram of one form of proposed circuit; Figure 3 is a block circuit diagram of a known A/D converter; Figures 4 and 5 are diagrams illustrating the operation of the proposed circuit shown in Fig. 2; and Figure 6 is a block circuit diagram of a second form of proposed circuit.

Referring to Fig. 1, an apparatus for testing for flaws ultrasonically comprises a pulse generator 1 connected by a line 2 to a test head 3 applied to a testpiece 4 having a flaw 5.

The test head 3 is also connected to a receiving amplifier 6, the output of which is connected by a line 7 to a circuit 8 in accordance with the present proposal for digitalizing and converting to logarithmic form the received echo signals. The output of circuit 8 is connected by a line 9 to an evaluating unit 10.

The operation of the apparatus is known and will therefore be described only briefly.

Electric pulses periodically generated by generator 1 energize test head 3, which generates a corresponding ultrasonic pulse. The ultrasonic pulse enters testpiece 4, is reflected by the flaw 5, the echo returning to test heat 3 and being converted into a corresponding electric pulse. The electric pulse is amplified in the receiving amplifier 6 and then digitalized and converted to logarithmic form in circuit 8. The values are retained temporarily in intermediate stores in the circuit 8 and supplied to unit 10 for further evaluation. As soon as the stored values have been transferred to unit 10, a strobe signal is applied by way of line 11 to circuit 8 and causes the intermediate stores in circuit 8 to be erased.

Fig. 2 shows one form of circuit 8 including conventional commercially available A/D converters 800 to 804. Siemens A/D converters Type SDA 5010 have been found particularly advantageous for use as the converters 800 to 804.

The A/D converters 800 to 804 are preceded by amplifiers 810 and 814 respectively, whose inputs are connected to line 7.

The output of the converters are in the form of linear digitalized values which are supplied to a coder 840 by way of a priority logic unit 820 and, if required, via a circuit arrangement 830 for recognition of maximum values.

Coder 840 converts the linear digitalized values into corresponding logarithmic values.

The linearly digitalized values can also be read off by way of lines 833 and further processed by evaluating unit 10 or supplied for graphic representation in a VDU (not shown).

When each conversion has been completed, release signals are supplied along lines 822, 832 and 834 to inform the respective downstream circuit units that signals are available on lines 821, 831 and 833.

Fig. 3 is a block circuit diagram of a known A/D converter suitable for use in the circuit of Fig. 2. The converter comprises a number of comparators 900, 901 and so on. The first input of each comparator is connected to line 70 on which is supplied the analog signal to be digitalized. The second input of each comparator is at a comparison voltage derived from a reference voltage U,,,, provided by a voltage source 920. The line from the source 920 include resistors 910, 911 and so on. all having the same resistance, the second inputs being connected to this line between the resistors as shown, in order to ensure that the comparison voltage at the comparators 900, 901 and so on decreases in linear manner.

The outputs of comparators 900, 901 and so on are connected to D flip-flops 930, 931.

The D flip-flops are used as intermediate stores and their outputs are connected to a priority coder 940, which translates the comparator states into a corresponding binary code. Line 941 then transmits the corresponding binary number to the priority logic unit 820 of circuit 8 (Fig. 2). A pulse (a logic 1) appears on line 942, which is likewise connected to unit 820, whenever the voltage on line 70 is large enough to exceed the comparison voltage at comparator 900 thereby providing an "overflow" bit.

The operation of the circuit shown in Fig. 2 will now be described in detail with reference to Figs. 4. 5 and 6: The gain of amplifiers 810 to 814 (Fig. 2) is chosen so that the dynamic ranges of the individual A/D converters overlap. Each of the converters includes 64 stages, each in the form of a comparator responsive to a predetermined voltage. Referring to Fig. 4, the vertical line 1 2 shows the entire voltage range (dynamic range) to be digitalized expressed as percentages. The vertical lines 1 3 to 1 7 show the respective voltage ranges in which the individual A/D converters 800 to 804 are to operate in conjunction with the amplifiers 810 to 814, the operating ranges of the converters overlapping by 10 stages. Assuming that the voltage on line 7 is within the range of the (lowest) converter 804, one or more of its stages generates a digital output value. If the input voltage exceeds the comparison voltage of stage 55 of A/D converter 804, converter 803 begins to operate simultaneously, for the comparison voltage of the first stage of converter 803 is likewise exceeded. However, the output of circuit 8 is not affected by the generation of digital signals by converter 803 so long as stge 64 of converter 604 does not respond. If the voltage on line 7 exceeds the comparison value of comparator 64, A/D converter 804 delivers an overflow signal on line 950 to unit 820, with the result that line 821 delivers a digital value indicating the states at that time of the stages of converter 803.

Accordingly, line 821 first supplies binary values corresponding to the states of stages 1 to 64 of converter 804, followed by binary values corresponding to the states of stages 10 to 64 of converter 803, and so on.

The overlapping working ranges of converters 800 to 804 are selected to give adequately high resolution over a large dynamic range. The lower converter stages, i.e. more particularly the states of stages 1 to 10, substantially determine the resolution of the entire circuit 8. This will be explained with reference to Fig. 5: The vertical line 1 20 represents the entire voltage range to be digitalized (dynamic range) in decibels. The vertical lines 1 30 to 1 70 represent the working ranges (dynamic ranges) of the linear A/D converters 800 to 804. The voltages corresponding to the individual stages are plotted in decibels (i.e. on logarithmic scales). As the drawing shows, the first ten stages of each A/D covnerter cover a dynamic range of 20 dB.

The remaining 54 stages are available for a dynamic range of 1 6 dB, so that the gradation, i.e. te spacing between individual stages in the logarithmic scale, is much finer in this case than the gradation between the first ten comparators. The spacing between individual stages decreases as the stage number increases. For example, a jump from the first to the second stage corresponds to a voltage change of 6 dB, a jump from the second to the third stage correponds to a voltage change of 3.5 dB, etc. If the voltage change (resolution) of circuit 8 has to be smaller than e.g.

0.8 dB per stage, digitalization must occur only after the 12th stage, since the jump from the tilth to the 12th stage is the first to produce a voltage change less than 0.8 dB.

In practice the resolution of circuit 8 for very small voltages (noise signals) can be worse than 6 dB, and therefore it is sufficient if only converters 800 to 803 satisfy the condition that digitalization occurs only after the 12th stage. In that case, converter 804 can efficiently digitalize from the first stage.

Fig. 6 shows a further circuit 80. The main difference between the two circuits is that Fig.

2 shows amplifiers 810 to 814 having varying gain whereas all the amplifiers 810 to 818 in Fig. 6 have th same gain. To this end the amplifiers, in contrast to Fig. 2, are not interconnected at the input side but are connected in series. Converters 800 to 804, and units 820, 830 and 840 are the same subassemblies as shown in Fig. 2.

Amplifiers 810 and 815-818, each having a gain of 1 6 dB, are used to make the individual dynamic ranges overlap so as to give a resolution of c0.8 dB.

The digital maximum value detector 830 comprises known circuit arrangements, which do not need to be described in detail here.

Basically, the only function of detector 830 is to compress data and it can be omitted in many cases.

The previously-described circuit arrangements were successfully used for A/D conversion of high frequency signals over a dynamic range of 80 dB and with a conversion rate in the 100 MHz region.

Claims (5)

1. A circuit arrangement for digitalizing and converting analog signals to logarithmic form, in which the signals to be processed are supplied to a number of analog-digital converters (A/D converters) preceded by amplifiers, the gain of the individual amplifiers being so chosen that the dynamic ranges of each A/D converter overlaps that of at least one other, the converters have linearly graded quantization stages; and a coder connected downstream of the A/D converters is used for converting to logarithmic form the digital signal obtained from the A/D converter.

2. A circuit arrangement according to claim 1, wherein each pair of A/D converters having adjacent ranges is connected via an amplifier and all the amplifiers have the same gain.

3. A circuit arrangement according to claim 1, wherein A/D converters in the form of monolithic integrated circuits are used.

4. The circuit arrangement according to claims 1, 2 or 3 when used in ultrasonic installations for non-destructive testing of materials.

5. A method in which an analog signal is supplied to a plurality of A/D converters each having a plurality of stages with sequential comparison voltages, the comparison voltages of some stages of one converter being the same as the comparison voltages of some stages of another converter, an output being generated indicative of the number of stages of the first comparator whose state has changed and, in the event that all of its stages have changed state, of the number of stages of the second converter which have changed state.