GB2034140A - Analog/digital conversion - Google Patents

Abstract

The invention provides an autoranging ultrasonic attenuation meter which includes a multistage amplifier for producing amplified signals from an input signal from an ultrasonic receiver transducer, amplitude reader means for determining the peak amplitude of the input signal and the signals, from each amplifier stage, comparator means for comparing the peak voltage of the signals with a reference voltage and to produce a binary output corresponding to each of said signals as a first quantisation of attenuation level, selection means for selecting from the peak amplitude signals the one having of voltage in a predetermined range, and comparison means for comparing the voltage of the selected signal with a ramp voltage as a second quantisation of attenuation level.

Description

SPECIFICATION Improvements in or relating to auto-ranging ultrasonic attenuation meters The present invention relates to auto-ranging ultrasonic attenuation meters such as may be used for detecting voids, inclusions, cracks or other flaws in, for example, solid propellent rocket motors.

One method which has been employed to measure the attenuation of an ultrasonic signal involves the measurement of the amplitude of the attenuated signal waveform on a cathode ray tube (CRT) display. A test specimen is placed between an ultrasonic transmitter and receiver, and the transmitter energised by electrical pulses of 1 ,us duration. The receiver output is fed via an emitter follower, attenuator and tuned amplifiers to an input of an ultrasonic test which has a CRT display. By adjustment of the attenuator and X and Y axis controls of the CRT, the amplitude of the waveform of the input can be measured and compared with the amplitude of the transmitter output signal. One disadvantage of such a method is that the dynamic measurement range is low.In one particular system the dynamic range was 14 decibels (dB) and was only obtained by a continuous manipulation of the system controls.

In a second known method a similar arrangement of emitter follower, attenuator and tuned amplifiers is used but the results are presented as an array of dots produced by a printer instead of a waveform on a CRT display. The number of dots printed is proportional to the amplitude of the received signal. The printing speed of dot printer, which is typically 120 dots per second, imposes a limit on the pulse repetition frequency (prf) of the ultrasonic signal which may be used.

The present invention provides an ultrasonic attenuation meter having a large dynamic range and capable of operation at high prf levels.

According to the present invention an autoranging ultrasonic attenuation meter includes a amplifier for producing amplified signals from an input signal from an ultrasonic receiver transducer, amplitude reader means for determining the peak amplitude of the input signal and the amplified signals, comparator means for comparing the peak voltage of the signals with a reference voltage and to produce a binary output corresponding to each of said signals as a first quantisation of attenuation level, selection means for selecting from said ouputs an output corresponding to the one of said signals having a peak voltage in a predetermined range, and comparison means for comparing the voltage of the selected output with a ramp voltage as a second quantisation of attenuation level.

The first and and second quantisations may be summed while in digital form, decoded and displayed as a digital readout.

According to another aspect of the present invention an autoranging ultrasonic attenuation meter includes amplifier for producing amplified signals from an input signal from an ultrasonic receiver transducer, amplitude reader means for determining the peak amplitude of the input signal and the amplified signals, comparator means for comparing the peak voltage of the signals with a reference voltage and to produce a binary output corresponding to each of said signals as a first quantisation of attenuation level, selection means for selecting from said outputs an output corresponding to the one of said signals having a peak voltage in a predetermined range, and conversion means for producing the binary equivalent of the selected output as a second quantisation of the attenuation level.

The first and second quantisations may be decoded while in digital form to produce a binary output equal to the attenuation level and displayed as a digital readout Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings of which: Figure 1 shows a block diagram of the circuit of an autoranging ultrasonic attenuation meter in accordance with the invention, Figure 2 shows a circuit diagram of an amplifier which forms part of the circuit of Figure 1, Figure 3 shows a circuit diagram of a set of four peak readers which forms part of the circuit of Figure 1, Figure 4 shows a circuit diagram of a comparator which forms part of the circuit of Figure 1, Figure 5 shows a circuit diagram of a trigger pulse generator which forms part of the circuit of.

Figure 1, Figure 6 shows a circuit diagram of a timing and logic control circuit which forms part of the circuit of Figure 1, Figure 7 shows a circuit diagram of a digital to analogue converter, which forms part of the circuit of Figure 1, Figure 8 shows a circuit diagram of a + dB log converter which forms part of the circuit of Figure 1, Figure 9 shows a circuit diagram of a counter-display circuit which also forms part of the circuit of Figure 1.

Figure 10 is a graph showing the frequency response curves of the amplifier of Figure 2; Figure 11 is a diagram showing input and output states of the trigger pulse generator of Figure 5, Figure 12 is a diagram showing timing sequences of the timing and logic control circuit of Figure 6, Figure 13 is a block circuit diagram of part of a second auto-ranging ultrasonic attenuation meter in accordance with the invention, and Figure 14 is a diagram showing the form of a comparator reference ramp voltage, Figure 1 5 is a block circuit diagram of a third autoranging ultrasonic attenuation meter in accordance with the invention, Figure 16 is a circuit diagram of an amplifier, peak reader and gating forming part of the circuit of Figure 15, Figure 1 7 is a block circuit diagram showing devices comprising linear to log converter of the circuit of Figure 15, Figure 1 8 is a circuit diagram giving details of a static level adjuster which receives signals from the converter of Figure 17, Figure 1 9 is a circuit diagram of a binary to BCD converter and display with associated latches and drivers which form the final stage of the circuit of Figure 1 5, Figure 20 is a circuit diagram of a trigger generator forming part of the circuit of Figure 1 5, Figure 21 is a timing diagram which illustrates the operation of the circuit of Figure 1 5.

As an ultrasonic signal traverses a medium, energy is extracted from it, reducing its intensity. The change of intensity Al as expressed in decibels (dB) is given by: Al = 10 log10 (ldl,) dB (see for example 'Fundamentals of Ultrasonics' by Blitz, J, pubiished by Butterworth 1967) where Ii and 12 represent (1) the initial and final intensities, respectively, of the ultrasonic pulse. It can also be shown that: laA2 (2) where A is the amplitude of a beam of intensity I.If A1 and A2 are the amplitudes corresponding to intensities Ii and 12 respectively, the change in amplitude AA is given by: AA = 20 log10 (A2/A) dB (3) The attenuation meter in accordance with the invention measures the amplitude level A2. A1 is chosen to be + 10 V. As attenuation measurements are made relative to a selected level and the system is calibrated, A1 may be chosen arbitrarily. The input amplitude to a transmitting probe (not shown) must remain constant (within +2%).

From equation (3) it can be shown that if the ratio A2/A, is 1, 1/10, 1/100 ... .. 1/1 0" the corresponding amplitude level change in dB is 0, --20 dB, --40 dB ... -20 n dB wherein n = 0, 1,2, 3 .... etc.

In accordance with an embodiment of the invention an input signal is amplified through successive stages in a cascade of amplifiers stages each having a gain of for example 20 dB. The amplifier stage, the output of which is in the range +1 to +10 V peak, is located and selected for processing. its position in the cascade immediately indicates the "coarse" range in which the input signal lies, ie 0-20, 200, 40--60 or 60--80 dB below the selected reference level. The "fine" range is obtained by processing that output logarithmicaliy between + 1 and + 10 V peak, this being a cbnvenient range for the circuit components. The result is a reading within a span of 0--20 dB to a resolution of 0.5 dB.Summation of the "coarse" and "fine" readings gives the total attenuation level, in dB, of the input signal.

Referring to Figures 1 and 2 a signal from an ultrasonic receiver transducer (not shown) is amplified through a three stage amplifier 1, which is shown in detail in Figure 2. The stages of the amplifier 2, 3 and 4 are each of 20 dB gain and provide outputs on lines 6, 7 and 8 at 20, 40 and 60 dB, respectively, above the input level of O dB which is supplied on a line 5. The output signals are detected and stored by a set of peak readers 9, which is shown in detail in Figure 3 in which input lines 10, 11, 12 and 13 connected to lines 5, 6, 7, 8 respectively, feed peak readers 1 4, 15, 1 6 and 1 7 and sampled levels compared in a set of comparators 1 8, which is shown in detail in Figure 4 in which four comparators 19,20,21 and 22 receive signals from the peak readers.A comparator reference rampvoltage signal, of the form shown in Figure 14, is generated by a digital-to-analogue converter (DAC) 23, which is shown in detail in Figure 7, and the sampled levels are compared with the ramp voltage.

During a ramp holding period, ie when the ramp level is steady at +10 V, "coarse" attenuation levels are read. For a peak level of + 10 V, or more, at input the comparator gives a logical '1' (high) output and 0 dB is added to a counter-display 24 shown in Figure 9. For an input of less than +10 V the comparators 1 8 gives a logical '0' output (low). A 20 dB step is added to the display 24 for each '0' level output. Data is clocked to, and held at, the display stage.

A timing and logic control circuit 25 selects the first comparator in the chain, the output of which is at 'O'. A high frequency clock drive 26, 100 kHz to 1 MHz, which forms part of the timing and logic control circuit 25, is fed simultaneously to the DAC 23 and to an eight-bit binary counter 28a-28h, which forms part of a z dB log converter 29, the input to which is gated by the comparator output. The ramp.voltage is driven down by the clock, and when this level becomes equal to the comparator input level, the comparator output changes stage and-inhibits the clock drive to the counter 28. The complements of the binary data produced by the counter are directly proportional to the input voltage.

The eight-bit data generated by the counter 28 are processed in the 2 dB logarithmic converter.

The output of the converter 29 is a six-bit word which is the binary logarithm of the eight-bit data over a range of 20 dB to a resolution of 2 dB. This gives the "fine" attenuation reading.

The "coarse" and "fine" readings are summed while in digital form and decoded to give a sevensegment numerical display, shown in detail in Figure 9. The total attenuation is then displayed directly ir dB.

Referring to Figure 2, the amplifier uses standard, integrated circuit operational amplifiers, selected for their high slew rate, large output voltage swing, wide full-power bandwidth, low noise and low voltage drift characteristics. The three cascaded stages 2, 3 and 4 are operated in the non-inverting mode for high input impedance, and are a.c. coupled to minimise d.c. offsets. Each stage is required to give a gain of 20 dB (x 10) so that overall gains of 0, 20, 40 and 60 dB (+0.5 dB) can be obtained over a frequency range of 60 kHz to 500 kHz. To provide extra lift in the response at high frequencies, giving a flat characteristic with no roll-off to 500 kHz, gain compensation is employed.

The closed-loop voltage gain AVCL of an operational amplifier, in the non-inverting mode, is given by

for large values of open-loop gain, where Rf is a feedback resistor 32 in amplifier 3 connecting the output to the inverting input, and Rj is a resistor 31 connecting the inverting input to ground.

If Rj is reduced at high frequencies, AVCL increases and counteracts the output roll-off of the amplifier. To achieve this effect a small compensation capacitor Cc, 30, of about 100 pF, is connected across Rj so that the parallel impedance of Rj with Cc decreases with increasing frequency, thereby increasing Avc. The values of the capacitors can be calculated to a reasonable degree of accuracy.

Tests have shown that the amplifier has a frequency response from 5 kHz to 1 MHz (see Fig. 10), within the required gain limits, when driven from a 75 ohm source.

The input impedance of the amplifier is about 3 k ohms at 100 kHz, falling to 750 ohms at 1 MHz.

A 220 pf capacitor, 33, is connected across the input to reduce unwanted high frequency signals.

Meesurements have shown the input noise to be about 70 zlV rms over the operating frequency range.

Referring to Figure 3, each of the peak readers 14, 15, 16 and 17 uses three integrated circuit operational amplifiers 34, 35 and 36. Input signals to each peak reader are processed through both inverting and non-inverting unity gain followers and the outputs of each are driven through type 1S120 diodes 37, 38 to a storage capacitor 39. This method effectively doubles the charging current to the storage capacitor 39 since it is being positively charged from both halves of the input waveform. The storage capacitor 39 can be charged to within vd of the peak input signal, where vd is the forward voltage drop across one diode. The diodes 37, 38 prevent charge leaking back through the outputs of the input stages.The third operational amplifier 36 has very high input impedance, of the order of 10" ohms in parallel with 3 pf, to buffer the storage capacitor 39, permitting long storage times.

A transmitter 40, connected across the capacitor 39 to perform the 'reset' function, is turned 'on' by a delay pulse, dissipating the stored charge and zeroing a buffer input. This function is performed within 2 ys.

The output stage features a variable 25 k ohms resistor 41, termed 'offset control'. This is used to set the peak reader output to +1 Vfora +1 V peak input, enabling the operation to be carried out within the required accuracy limits (*0.5dB of the input level) for input voltages in the range +1 to +10 V peak.

Tests have shown that each peak reader has a dynamic range of 24 dB (+600 mV to +10 V peak at input) from DC to 1 MHz within the required limits of accuracy. The output droop rate of the readers has been measured as 30 mV in 5 ms, which is within acceptable limits.

The comparator circuit 18, shown in Figure 4, incorporates four high speed comparators 1 8, 20, 21 and 22 and a buffer 42 for the DAC output, as this is limited to a 2 mA fuli scale, having high differential input impedance, fast response, large input slew rate and high open loop voltage gain (AVOI) and the power supplies are +15 V.

Buffered reference ramp voltage is supplied via a line to all comparator inverting inputs. The sampled input levels are connected to the non-inverting inputs of the comparators. For input signals greater than the reference level, the comparator assumes a high output state, while for the input signals less than the reference level, it assumes a low output state.

To increase the speed of the low-to-high transition in the comparator output, and to ensure oneshot operation of the comparators, positive feedback is applied. Each comparator output is connected through a high value resistor 44, to the non-inverting input, and the input voltage to the non-inverting input is driven via a resistor 45, to give the comparator a hysteretic output characteristic. The hysteresis width, a voltage, VH, of each comparator, is given by:

where Rf is the resistance of resistors 44 and Rj is the resistance of resistors 45.

Each comparator output is clamped by a 4.7 Zener diode to ground so that the output levels generated are TTL-compatible.

A trigger pulse generator 47, shown in Figure 5, is designed to accept negative-going transmission pulses, in the range -50 V to -1000 V, and to generate a TTL-compatible output pulse of 500 s duration, the positive-going edge of which coincides with the first negative-going transmission level, as shown in Fig. 11.

The generator has an input circuit which consists of a potential divider 48 driving the inverting input of an operational amplifier 49 having a value of Avo of the order of 105, and acts as a zero-crossing detector. The output of-the detector swings positive for negative-going input levels and negative for positive-going transitions. A 3.9 V Zener diode 5Q provides a TTL-compatible output drive to a set-reset latch 51 which is reset by a monostable 52 after 500,us.

The prime function of the timing and logic control circuit 25 shown in Figure 6 is to generate a timing sequence as shown in Fig. 1 2. The timing circuit operates as follows:- The positive edge of a trigger pulse from the generator 47 trips an 'overrun reset' which ensures that the '0' output of a bistable 53 is set to a logical '0'. This prevents the output from locking into a high state if successive processing periods overlap.

A bistable clear pulse sets all counter and flip-flop outputs to '0' but presets the 'Q' output of bistable 53 to a '1'.

A delay pulse is generated to set the peak-readers 14, 1 5, 1 6 1 7 in the 'reset' mode, inhibiting the system and disregarding any transmission breakthrough into the amplifier. The pulse length of the delay pulse is variable over two ranges; from 1.3 us to 76 ,os and from 136,us to 7.6 ms.

A window pulse is generated which opens a peak-reading period. The window pulse length is variable from 132 Ms to 6.4 ms and is set so that it just encompasses the input pulse.

A bistable clock pulse 54 generates and locks the initial comparator output states, ie those set during the 'ramp-holding' period, into four delay bistables 54, 55, 56 and 57, for decoding and is retained until the next trigger period is initiated.

A ramp down period is initiated by the trailing edge of the bistable clock pulse, driving a high frequency pulse train to the DAC 23, generating a falling ramp voltage. The pulses are also driven to the T dB logarithmic converter 29 so that both reference voltage and the logarithmic conversion function are generated to synchronism. The pulse drive to the 2 dB logarithmic converter 29 is inhibited when the reference voltage has fallen to a level equal to the input level of whichever comparator has an input in the range +1 to +10 V peak.

The pulse drive to the DAC 23 is maintained until the output level has fallen to around 900 mV. A display clock 58 pulse clocks all decoded data to display stages on the counter display 24. The data is held until it is reset by the complement of delay pulse (delay-display clear) or bistable clear pulse.

A ramp clear pulse from a monostable 59 sets the DAC output to OV, completing the operating cycle. The cycle is repeated when the next trigger pulse is initiated.

A logic control function is performed by the four delay bistables 54, 55, 56 and 57 and associated 'AND','NOR' and 'OR' gates. The circuit 25 automatically selects, for fine processing, the input level to the first comparator in the chain whose input is at logical '0', ie the comparator, the input voltage of which is in the range +1 to +10 V peak.

The circuit 25 is designed to allow high frequency pulses through to the 2 dB logarithmic converter 29, until the reference voltage has fallen to the level of the input signal being processed, producing a change of output state in the corresponding comparator.

The DAC circuit 23 shown in Figure 7 uses a 16-pin dual-in-line monolithic integrated DAC, 59, to perform a digital-to-analogue conversion and requires parallel input data and the serial data, from the ramp drive output, are converted to this form by an eight-bit up/down counter. Voltage output of circuit 2 is generated by an operational amplifier 6q incorporating both full scale and offset adjustments.

The circuit 23 is designed to operate in the 'backward' mode, the first pulse driving the output to full scale, ensuing pulses causing the 'ramp down' function to be generated.

The+dBlogarithmic converter 29 shown in Figure 8 is a decoder designed to produce one output pulse for each of a set of 40 words from 256 generated by the eight-bit counters 28. Pulse drive to the counters is provided by the timing and logic control circuit 25 and gated by the selected comparator output. The complement of the eight-bit word generated is directly proportional to the input voltage, a change of 1 least significant bit corresponding to a 40 mV step in the output, over a 20 dB range from +1 to +10 V peak. A logic network selects the word required to produce an output pulse. The output is in a logarithmic sequence so that, when driving a six-bit counter, it generates a binary word which is the logarithm of the eight-bit word. The converter covers a range of 20 dB with a resolution of 2 dB. The sequence generated by the converter 29 is shown in Table 1.

TABLE 1 Sequence generated by V2 dB log converter The V2 dB log converter generates an output pulse for each of the following binary input configurations. The attenuation corresponding to each input word is given.

Input Atrenuation Input Attenuation MSB LSB (dB) MSB LSB (dx o 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 10.0 O 0 0 0 1 1 1 0 0.5 1 0 1 1 0 0 1 1 10.5 O 0 0 1 1 1 0 0 1.0 1 0 1 1 0 1 1 1 11.0 0 0 1 0 1 0 0 1 1.5 1 0 1 1 1 0 1 1 11.5 0 0 1 1 0 1 0 1 2,0 1 0 1 1 1 1 1 1 12.0 0 1 0 0 0 0 0 0 2.5 1 1 0 0 0 0 1 0 12.5 0 1 0 0 1 0 1 0 3.0 1 1 0 0 0 1 1 0 13.0 0 1 0 1 0 1 0 1 3.5 1 1 0 0 1 0 0 1 13.5 0 1 0 1 1 1 1 0 4.0 1 1 0 0 1 1 0 0 14.0 0 1 1 0 0 1 1 1 4.5 1 1 0 0 1 1 1 1 14.5 0 1 1 1 0 0 0 0 5.0 1 1 0 1 0 0 1 0 15.0 0 1 1 1 1 0 0 0 5.5 1 1 0 1 0 1 0 0 15.5 0 1 1 1 1 1 1 1 6.0 1 1 0 1 0 1 1 1 16.0 1 0 0 0 0 1 1 0 6.5 1 1 0 1 1 0 0 1 16.5 1 0 0 0 1 1 0 1 7.0 1 1 0 1 1 0 1 1 17.0 1 0 0 1 0 0 1 1 7.5 1 1 0 1 1 1 0 1 17.5 1 0 0 1 1 0 1 0 8.0 1 1 0 1 1 1 1 1 18.0 1 0 0 1 1 1 1 1 8.5 1 1 1 0 0 0 0 1 18.5 1 0 1 0 0 1 0 0 9.0 1 1 1 0 0 0 1 0 19.0 1 0 1 0 1 0 1 0 9.5 1 1 1 0 0 1 0 0 19.5 1 1 1 0 0 1 1 0 20.0 3.8 The display card The counter-display shown in Figure 9, using logic devices coupled with 741 88A, 32 x 8 bit programmable read-oniy memories 61, and decodes both 'coarse' and 'fine' data from the converter 29 to drive a 3 x 7 segment numerical display 62 which produces a read-out directly in dB. The 741 88A programmes are shown in Tables 2 and 3 below.

TABLE 2 Programme for 74188A PROM: Chip 10 display card Input output E D C B A Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 0 0 1 0 O 0 1 0 0 0 1 1 0 0 1 1 0 O 0 1 0 1 1 0 1 1 0 1 1 0 O 0 1 1 0 0 0 1 1 1 1 1 0 O 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 -1 0 1 0 0 1 1 1 1 1 1 0 0 TABLE 3 Programme for 74188A PROM: Chip 22 display card Input output E D C B A yl Y2 y3 Y4 Y5 Y6 Y7 Y8 O O O O O 1 1 1 1 1 1 0 0 O O O O 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 0 0 At normal pulse repetition rates the display would be updated at every pulse but this is too fast for an operator to read. A delay circuit 64 is incorporated so that an operator can select using a binary switch 63, the required delay, which is dependent on the prf.

Delay settings are available from 10 to 90 in steps of 10, and from 100 to -900 in steps of 100.

The delay circuit is designed so that the display generates a read-out for 1 pulse, ignoring the next (n-1) pulses, where n is the delay setting.

An undecoded output is available, carrying the information generated by every input pulse for more detailed processing if required.

A test/operate switch 65 is provided which overrides the delay circuitry permitting static testing of the memories and displays.

Part of a second embodiment of the invention is shown in Figure 13. This embodiment employs the same amplifiers, peak readers and comparators as the first embodiment described above but has the following modifications: A single 256 x 8 bit prom 29, is used as a 2 dB logarithmic converter.

Data, giving 'coarse' and 'fine' attenuation levels is decoded by a second prom, 1 00, to generate a pure binary output to simplify interfacing with external equipment.

An external switch is provided to permit the addition of discrete binary levels to the output data and display. This allows the output reading range of the meter to be shifted from 0--80 dB to 40-1 20 dB in steps of 10 dB, and effects a change of reference point against which the attenuation measurements are made, and enables the operator to obtain readings which are the actual attenuation loss between the probes. Also a second DAC 101 may be added to generate an analogue output voltage which is directly proportional to the attenuation. The analogue level is updated at the same rate as the display.

A third embodiment of the invention is shown in Figure 1 This embodiment comprises a meter having a single stage amplifier 100 having dynamic range of 40 dB. The amplifier is connected to receive a signal on a line 99 from an ultrasonic receiver (not shown) as in previous embodiments. The amplifier 100 has an output which is detected and stored in a peak reader circuit 101 shown in detail in Figure 16. The circuit 101 is shown in detail in Figure 16, and employs a pair of 'OEI' type 5030A peaksample-hold devices 108, 109, having a dynamic range of 40 dB up to frequencies of 5 MHz. Output from the p-s-h device 108 is fed via an offset 116 on line 11 5 to an input of a dual input comparator 110 having its other input at +10 V reference level.A line 111 carries the output from the comparator 110, and the output controls an analogue switch 114 to select the appropriate level for fine level processing, the switch 114 having its output of 100 mV to 10 V peeak on a line 113. The comparator 110 output is also carried on a line 112 as either a O or 40 dB step to be added to the fine level.

A selected input level from the reader 101 is converted to digital data by a 12-bit analogue to digital converter, 102, and the data held is a latch 103. This data is then processed by a linear-to-log converter 104 comprising a pair of programmable read-only memories (PROM's) 11 7, 11 8 (see Figure 1 7). PROM 11 7 generates the logarithm of the input signals in accordance with stored programs. The following Table 4 list part of the program in PROM 117.

TABLE 4 PROGRAM FOR PROM, 117 (TEXAS TMS 2532) db i/p Level Dec Change Point Log Binary 40 100 mV 40 39 01010000 39.5 106mV 42 41 01001111 20.5 944 mV 378 367 00101001 20.5 944 mV 378 367 00101001 20 1.0V 400 389 00101000 . . .

0.5 9.44 V 3776 3670 00000001 0.5 9.44 V 3776 3670 00000001 0 data from PROM 117 are 10.00 V 4000 1 18 while generate 3888 'fine' and 00000000 The data from PROM 117 are input to PROM118 which generates from dB 'fine' and 'coarse' data an 8-bit output which covers a 0-80 dB range in steps adjuster of which includes 2 a 12-bit dB.

Data from the PROM 11 8 are adder'A' input to a static level adjuster 130 which includes by a 12-bit adder, 120, (see Figure 18), via the adder 'A' input, 'B' input to the adder 120 is generated by a 1K x 8-bit PROM, 121 (type 8282708) having a program in accordance with the following.

a. When the calibration is set in a (+) mode, the program generates BCD-to-binary conversion, using BCD thumbwheel switches (not shown).

b. In When the calibration issetin a may mode,the program generates BCD-to-binary complement +1, LSB. In this way a true calibration point maybe obtained through A + B or A - B. The summed data are input to a PROM, 1 22 (type 74S472, -3) having a program in accordance with the following.

a. For calibration set in (+) mode, data out = data in; b. For calibration set in (-) mode, and A > B, dataout=complementdata in +1 LSB, thus allowing positive attenuation to be measured with respect to to the reference position.

Calibration points, 123 at positive or negative values, aresettable from 0 to 99.5 dB, in steps of 0.5 dB. An over-range circuit, 123 is included to ensure that input levels less than, or greater than, the input range of the meter will be indicated by an LED,124.8-bit binary data are latched to line drivers 127 to provide a binary output on lines 125 and 126 for indicating whether the signal is below or above range.

Referring to Figures 1 5 and 19, the 9-bit output data is input to a binary-to-BCD converter 128 to generate display codes for display on display units, 131, 132, and 1 33 which digital ro include latches and drivers. 8-bit binary data on lines 134, 135 are latched to a 10-bit digital to analogue converter 136 by either a latch on the delayed display latch pulse on lines 137 and 1 38 respectively, to generate an analogue output of the attenuation level. BCD data 141 on lines 139 and 140 to which a carry outputs from the converter 128 are latched by a pulse from latch 141 to line drivers, 142, to provide a BCD output of the attenuation level.

A trigger generator 143 shown in Figure 1 5 and shown in detail in Figure 20, has an input on a line 145 at a level of 5 V to 1 000 V peak. The generator includes a comparator 144 protected at one input by Schottky doides after the signal has been reduced by a factor of 20 to 1 by a potential divider.

A variable DC level of approximately +1.5 V provides a reference input on a line 146 to the comparator 144 after being buffered by an operational amplifier 147. By varying dc levels triggering from either positive or negative-going signal edges can be used to de-sensitise input levels where spurious spikes on input lines may cause false triggering. A TTL compatible pulse is generated by damping the comparator 144 output with a 4.7 V Zener diode, 148. The clamped output is fed to a dual monostable (type 74221), 149, via a Schmitt trigger which when triggered trip a latch 1 50 which generates a trigger output on line 151. The latch 1 50 is reset at the end of a 'read' cycle.

Figure 20 shows a timing diagram for the meter. Referring to trace 1, a trigger pulse A is generated to initiate a timing sequence. A variable delay, pulse B on trace 3 from 1 to 1000 Hs duration is triggered from the rising edge of the trigger pulse A. The trailing edge of B trailers a window pulse C on trace 4 from 1 to 1000 flls duration to act as a measurement gate. A 50 ElS fixed delay pulse D on trace 6 is triggered by the window trailing edge and spans Analogue to Digital conversion period. The negative going edge of pulse D triggers an ADC conversion command pulse E on trace 7 which is in the range 100 ns to 2 StS. ADC clocking and end of ADC conversion are indicated on traces 8 to 9 respectively.

When conversion is complete a 1 ElS latch pulse, on trace 10, latches all data with the meter circuits.

A circuit for generating delayed display-latch puises, which is the same as that described for the first embodiment herein, is not shown.

Claims (5)

1. An autoranging ultrasonic attenuation meter including a multistage amplifier for producing amplified signals from an input signal from an ultrasonic receiver transducer, amplitude reader means for determining the peak amplitude of the input signal and the amplified signals, comparator means for comparing the peak voltage of the signals with a reference voltage and to produce a binary output corresponding to each of said signals as a first quantisation of attenuation level, selection means for selecting from said outputs an output corresponding to the one of said signals having a peak voltage in a predetermined range, and comparison means for comparing the voltage ofthe selected output with a ramp voltage as a second quantisation of attenuation level.

2. A meter as claimed in claim 1 wherein the first and second quantisations are summed while in digital form and displayed as a digital readout.

3. An autoranging ultrasonic attenuation meter including an amplifier for producing amplified signals from an input signal from an ultrasonic receiver transducer, amplitude reader means for determining the peak amplitude of the input signal and the amplified signals, comparator means for comparing the peak voltage of the signals with a reference voltage and to produce a binary output corresponding to each of said signals as a first quantisation of attenuation level, selection means for selecting from said outputs an output corresponding to the one of said signals having a peak voltage in a predetermined range, and conversion means for producing the binary equivalent of the selected output as a second quantisation of the attenuation level.

4. A meter as claimed in claim 3 wherein the first and second quantisations may be decoded while in digital form to produce a binary output equal to the attenuation level and displayed as a digital readout.

5. An autoranging ultrasonic attenuation meter substantially as described herein with reference to the drawings.