WO1990016123A1 - Modem capable de detecter des conditions de synchronisme hors bloc - Google Patents
Modem capable de detecter des conditions de synchronisme hors bloc Download PDFInfo
- Publication number
- WO1990016123A1 WO1990016123A1 PCT/JP1990/000769 JP9000769W WO9016123A1 WO 1990016123 A1 WO1990016123 A1 WO 1990016123A1 JP 9000769 W JP9000769 W JP 9000769W WO 9016123 A1 WO9016123 A1 WO 9016123A1
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- signal
- frame
- point
- error
- transmission
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
Definitions
- the present invention relates to a modulation apparatus for a phase modulation / demodulation method, a quadrature amplitude modulation / demodulation method, or the like.
- the present invention relates to a device capable of detecting out-of-frame synchronization in synchronous transmission in a modem.
- the device according to the present invention is used, for example, for a modem device in a data communication terminal.
- a frame is included in a rasing signal for automatic pull-in of an automatic equalizer on the receiving side performed prior to data transmission.
- Frame synchronization between transmission and reception is achieved by including a synchronization signal.
- operation is performed with the synchronized frame phase when receiving the training signal. If frame synchronization is lost due to characteristics fluctuations on the line during data transmission and frame synchronization is lost, data transmission cannot be performed normally, but this frame synchronization loss can be determined only from abnormalities in received data. Therefore, it would be desirable to have a method to detect frame synchronization quickly and accurately.
- the data transmission speed of a transmission device that uses an analog surface line with a transmission speed of 2400 bps to 19200 bps is generally It is an integral multiple of 2400 bps.
- the modulation rate which is the time interval for transmitting and receiving data while starting, is different from 2400 bps, and the number of transmission bits that can be modulated and demodulated at one time is an integer
- an integer multiple of the reference 2400 bps is used.
- the synchronization of the frame phase between transmission and reception is performed by matching the frame phase of the reception frame with the frame phase of the transmission frame by inserting the frame start signal in the training signal performed prior to data transmission.
- operation is performed according to the synchronized frame phase when the training signal is received.
- a modulation synchronization signal is demodulated for each modulation, and frame phase information is generated by counting the number of the demodulation synchronization signals.
- the clear timing is determined by the frame synchronization signal at the time of receiving the training signal, so that the transmission and reception frame phases can be synchronized without receiving the frame synchronization signal during data transmission. .
- a main object of the present invention is to perform coordinate image transformation on signal point coordinates on a complex plane, in which a bit sequence from an error control coding unit on a transmitting side is converted, based on frame phase information, and on a receiving side.
- the received coordinate of the receiving point is subjected to the coordinate rotation opposite to the coordinate rotation based on the frame phase information, and the most likely signal point is determined using the redundancy added by the error control coding means on the transmitting side.
- Judgment the presence or absence of frame synchronization loss is determined based on the distance between the determined judgment point and the demodulation reception point, thereby quickly detecting that frame synchronization has been lost, and operating the modem.
- the purpose is to improve the reliability of the system.
- Bit processing means for outputting a bit string of transmission data at predetermined time intervals
- Frame phase generating means for generating frame phase information in which an interval of an integer N times the time of the bit string is defined as one frame; redundancy according to a predetermined procedure for a transmission bit string from the bit processing means Error control coding means for coding by adding a degree;
- a data string-to-coordinate conversion means for converting the bit string from the error control coding means into signal point coordinates on a complex plane
- Coordinate image conversion means for rotating the converted signal point coordinates based on frame phase information from the frame phase generation means
- Demodulation means for demodulating reception point coordinates on a complex plane from a reception signal of a communication plane line
- Frame phase detection means for detecting a frame synchronization signal from the training signal sent from the transmission side and matching the frame phase from the frame phase generation means with the reception frame phase; the frame phase of the frame phase generation means Coordinate rotation means for applying a rotation to the receiving point coordinates in the opposite direction to the coordinate image conversion means on the transmitting side based on the information;-Judgment of the most probable signal point using the redundancy added by the error control coding means on the transmitting side Signal point determining means for correcting an error in the coordinates of the receiving point by performing
- Frame out-of-synchronization determining means for determining the presence / absence of frame out-of-synchronization based on the distance on the complex plane between the decision point and the demodulation reception point by the maximum likelihood signal point determining means.
- a receiving device connected to an image on which transmitted data is most likely encoded and phase-modulated and transmitted is provided.
- Proximity signal point judging means for judging and outputting one of the ideal signal points to be transmitted with respect to the compensated signal output from the compensating means, out of a plurality of ideal signal points.
- a maximum likelihood signal point determining unit that decodes the maximum likelihood encoded data using the compensated signal output from the compensating unit and determines and outputs the maximum likelihood signal point;
- Equipment is provided.
- Error control encoding means for encoding a transmission signal according to a predetermined transition rule for restricting transition of a signal point on a complex plane
- Modulating means for modulating the coded signal coded by the error control coding means and transmitting the coded signal to a communication line;
- First transmission signal selection means for transmitting an uncoded signal not coded by the error control coding means for a predetermined time at the start of transmission of transmission data
- the error control coding means Second transmission signal selecting means for transmitting an encoded predetermined encoded signal for a predetermined time and switching to transmission of transmission data when transmission of the encoded signal is completed;
- Demodulating means for demodulating a signal point on a complex plane from the received signal of the communication object
- An evaluation value is set for each of a plurality of transition sequences of the received signal based on the transition rule on the transmitting side, and the evaluation value is updated each time a signal is received, and the maximum value is determined based on the updated evaluation value.
- Error control signal decoding means for correcting an error of a demodulated signal point by selecting a transition sequence of the received signal;
- Evaluation numerical value setting means for setting, to the error control signal decoding means, an initial value of an evaluation numerical value updated by the first received coded signal when switching from the uncoded signal to the transmission of the coded signal;
- a modulation / demodulation device for performing error correction of data transmission,
- FIG. 1 is a diagram showing a modulation / demodulation device as one embodiment of the present invention
- FIG. 2 is a waveform diagram showing signal waveforms for explaining the operation of the FIG. 1 device
- FIG. 3 is a diagram showing a signal point arrangement for trellis coded modulation used for error control coding.
- FIG. 4 is a diagram showing a modem according to another embodiment of the present invention.
- FIG. 5 is a waveform diagram showing signal waveforms for explaining the operation of the FIG. 4 apparatus.
- FIG. 1 An apparatus according to one embodiment of the present invention is shown in FIG. 1
- FIG. 2 The operation of the FIG. 1 apparatus is illustrated in FIG. 2 and FIG.
- the transmitting side images the transmitted signal on the complex plane according to the frame phase, and the receiving side rotates the received signal points on the complex plane in the opposite direction to the transmitting side. It is returned to the original state, and it is further determined that frame synchronization has been lost based on the difference between the hard decision distance and the soft decision distance.
- the hard decision signal point and the soft decision signal point are usually the same point, in which case the difference between the two errors becomes zero, and When this occurs, the loss of synchronization is measured and detected by using the fact that the difference between the two becomes large.
- the difference can be obtained, for example, when it is lost, and this value is subjected to integration processing or the like, and when the value exceeds a predetermined value, it can be determined that the synchronization is lost.
- a transmitting side 1 includes a bit processing circuit 10 for outputting a bit sequence of transmission data at a predetermined time interval, and an interval N times an integer of the time interval of the bit sequence.
- a frame phase generation circuit 12 that generates frame phase information and a training signal that generates a frame synchronization signal prior to data transmission
- a trellis coding circuit as an error control coding circuit for coding the transmission bit string from the bit processing circuit 10 by adding redundancy according to a predetermined procedure.
- a data string-to-coordinate conversion circuit 18 for converting the bit string from the error control encoding circuit 16 into a signal point coordinate on a complex plane, and a signal point converted by the data string-to-coordinate conversion circuit 18
- a coordinate rotation circuit 20 that applies a predetermined coordinate plane rotation to the coordinates based on the frame phase information from the frame phase generation circuit 12, and outputs the output of the coordinate rotation circuit 20 to the communication plane line 6 after phase modulation or quadrature amplitude modulation. Modulation means 24 are provided.
- the receiving side 2 has a demodulation circuit 26 that demodulates the coordinates of the receiving point on the complex plane from the signal received on the communication line 6 and a frame synchronization signal from the training signal sent from the transmitting side.
- a frame phase detection circuit 32 that adjusts the delay amount ⁇ of the variable delay circuit 30 so that the frame phase from the frame phase generation circuit 28 matches the reception frame phase from the variable delay circuit 30;
- a coordinate image conversion circuit 34 for performing rotation of the receiving point coordinates in a direction opposite to the coordinate rotation of the transmitting side based on the frame phase information of the area 28, and the received point coordinates output from the coordinate rotating area 34 are transmitted.
- the first determination path 36 that determines which signal point is the closest among the signal points on the complex plane as a hard decision, and the redundancy added by the error control coding means 16 on the transmission side Utilize the most (most likely )
- a second decision circuit 38 that decides the signal point as a soft decision and corrects the error of the coordinates of the reception point, and a decision point and a demodulation reception point on the complex plane by the first and second decision circuits 36 and 38 Frame loss determination circuit that determines the presence or absence of frame loss based on the distance 5 Is provided.
- the out-of-frame determination circuit 5 determines the frame based on the difference between the distance between the determination point by the first determination circuit 36 and the demodulation reception point and the distance between the determination point of the second determination circuit and the demodulation determination point. Determine that synchronization has been lost.
- the distance between the decision point of the first decision circuit 36 and the demodulation reception point is calculated as a first decision error E 1 as a hard decision error
- the distance between the decision point of the second decision circuit 38 and the demodulation reception point is calculated.
- the average value of the difference “E 1 — E 2” between the first and second decision errors E 1 and E 2 is equal to or greater than a predetermined value.
- each of the frame phase generation circuits 12 and 32 provided on the transmission and reception sides divides one frame into two parts, a first half frame and a second half frame.
- the coordinate image transfer circuit 20 on the transmitting side performs predetermined coordinate rotation on the signal point coordinates set in the first half frame, and makes the signal point coordinates included in the second half frame non-image.
- the coordinate rotation circuit 30 on the receiving side performs predetermined coordinate rotation opposite to that of the transmitting unit to return the coordinates of the receiving point set in the first half frame to the original position, and the receiving point coordinates included in the second half frame are non-rotated.
- the relationship between the coordinate rotation and the non-image rotation in the first half frame and the second half frame is not limited to this, and conversely, the first half frame can be non-image rotation and the second half frame can be rotation.
- the generating circuits 12 and 32 generate the same frame information independently of each other and asynchronously.
- Fig. 1 shows an example of data transmission at a transmission speed of 14400 bps.
- reference numeral 10 denotes a bit processing area
- transmission data is given from an appropriate terminal, and the bit processing area 10 separates a bit string of the transmission data for each modulation bit.
- Outputs after processing such as scrambling. Since the transmission speed of the device shown in FIG. 1 is 14400 bps, 6 bits are obtained by dividing 14400 bps by 2400 bps. Q3n Q2n Ql n 'is output.
- the 6-bit bit string from the bit processing circuit 10 is supplied to a trellis coding circuit 16 as an error control coding circuit, and the trellis coding circuit 16 adds one redundant bit according to a predetermined rule. It outputs a 7-bit bit string.
- the trellis encoding circuit 16 inputs the lower two bits “& 2n Qln” of the bit string from the bit string processing circuit 10 to an encoding circuit composed of a differential encoder and a convolutional encoder, and outputs a 3-bit signal. Create a subset "Y2n Y in YOn". The 3-bit subset of the total of 7 bits to the high-order 4 bits-bit string "Q6n Q5n Q4n & 3n Y2n Y in YOrT c to generate a
- the output of the trellis coding circuit 16 is supplied to a data column-to-coordinate conversion circuit 18 via a switch circuit 42.
- Switch surface 42 Switches the output of the release code circuit 16 and the training signal generation circuit 14. That is, prior to data transmission, the switch circuit 42 selects the training signal from the training signal generation circuit 14 and receives the training signal from the training signal generation circuit 14 to select the training signal.
- the frame synchronization signal is included in the training signal generated by the training signal generation circuit 14.
- the receiving side 2 detects a frame synchronization signal from the training signals and performs frame synchronization control during training.
- the switch circuit 42 selects the output of the trellis code circuit 16 during data transmission.
- the data string-to-coordinate conversion circuit 18 converts the 7-bit bit string obtained from the trellis coding circuit 16 into coordinates indicating signal points on a complex plane.
- the data string-to-coordinate conversion circuit 18 is a signal represented by a black point on a complex plane represented by a binary number of a bit string from the 7-bit trellis coding circuit 16 in accordance with the signal point arrangement shown in FIG.
- the coordinate data of the point that is, the coordinate data consisting of the amplitude value of the real axis (Re) and the amplitude value of the imaginary axis (I m) is output.
- A, B, C, and D are signal points for the first half of the training signal for low speed.
- a coordinate plane conversion circuit 20 is provided following the data string-to-coordinate conversion circuit 18, and the coordinate rotation path 20 is based on the frame phase information from the frame phase generation circuit 12 and is output from the data string-to-coordinate conversion circuit 18.
- a predetermined rotation on the complex plane is performed on the signal point coordinates.
- the frame phase generation image path 12 starts when the power is turned on. It operates independently, and as shown in the transmission-side frame phase information (Fig. 2 (2)), the frame phase information obtained by dividing one frame, which is 8 modulation, into the first half frame and the second half frame appear.
- the coordinate rotation circuit 20 rotates on a complex plane the coordinate of the signal point from the data sequence to the coordinate conversion circuit 18 included in the first half frame A, for example, 0 Is + 90 °, for example, 90 ° clockwise on the complex plane in Fig. 3, and the lower signal coordinates in the next second half frame are not rotated without coordinate rotation. Is repeated every frame.
- the output of the coordinate rotation circuit 20 is provided to a modulation circuit 24, modulated by phase modulation, quadrature amplitude modulation or the like, and output to a communication line 22. That is, in the modulation image 24, the amplitude value of the real axis (Re) of the signal point coordinates output from the coordinate plane conversion circuit 20 is modulated by sino) t, and the amplitude value of the imaginary axis ( ⁇ ) is advanced by 90 °. The signal is modulated by sinw t, and both are combined and output to communication line 6.
- a demodulation circuit 26 demodulates signal point coordinates, that is, reception point coordinates, from a reception signal of the communication object 6. Chi words, taken out the amplitude value of the real axis (Re) the received signal and synchronous detection with c 0S 6) t, also taken out the amplitude values of the imaginary axis (1 «) by synchronous detection with sin w t.
- the demodulation circuit 26 includes a circuit for removing a line deterioration factor, such as an automatic equalizer or CAPC.
- a frame phase generation circuit 28 detects a frame synchronization signal included in a training signal from the transmission side 1 performed prior to data transmission, and detects a frame phase from the frame phase generation circuit 28 on the reception side 2.
- the delay amount ⁇ of the variable delay circuit 30 is adjusted so that the information matches the phase of the transmission side frame phase information of the frame phase generation circuit 12 provided on the transmission side 1.
- each of the frame phase generation circuit 12 provided on the transmission side 1 and the frame phase generation picture 28 provided on the reception side 2 operate independently when the power is turned on, and the one frame is divided into the first half frame and the second half. Frame phase information divided into frames is generated, and the transmitting and receiving side frame phases do not match. Therefore, the frame phase detection circuit 32 knows the transmission-side frame phase based on the frame synchronization signal detected from the training signal, and determines the error of the reception-side frame phase with respect to the transmission-side frame phase. The delay amount is obtained, and the delay amount of the variable delay circuit 30 is adjusted. By the signal delay by the variable delay amount circuit 30, the frame phases of the transmission-side and reception-side frame phase generation circuits 12 and 28 in the independent operation state are matched.
- the coordinate rotation circuit 34 following the variable delay circuit 30 transmits the reception point coordinates obtained through the variable delay circuit 30 based on the frame phase information from the frame phase generation circuit 28 on a complex plane. A coordinate rotation opposite to the side is performed.
- the first half frame is subjected to, for example, a face rotation, for example, a rotation of + 90 ° as 0, in the coordinate rotation circuit 20 on the transmission side, and the second half frame is Non-movement Therefore, based on the frame phase information from the frame phase generation circuit 28, the coordinates of the receiving point set in the first half frame are the reverse face rotation 6 from the transmitting side, that is, 1-90 ° coordinate plane rotation as 0. However, the latter half frame is non-rotating.
- the signal point coordinates that have undergone the coordinate rotation on the transmitting side 100 by the coordinate rotating circuit 34 return to the original signal point coordinates before the coordinate image conversion on the receiving side if the frame synchronization is normally performed.
- the coordinates of the receiving point from the coordinate rotation circuit 34 are given to a first determination circuit 36 as hard decision means and a second determination circuit 38 as soft decision means.
- the first determination circuit 36 determines which of the signal points on the complex plane that are likely to be transmitted is the signal point on the complex plane that is closest to the received signal point at that time. The closest coordinate point is output as the judgment point.
- the second determination circuit 38 uses the redundant bits by the trellis code performed by the trellis code circuit 16 on the transmission side to determine a predetermined signal point on the maximum likelihood complex plane as a reception point. Then, the error at the received signal point is corrected. For example, a numerical value for evaluation is set for each of a plurality of transition sequences of a received signal based on a transition rule according to trellis coding on the transmitting side, and the evaluation value is updated and updated each time a signal is received. The error of the demodulated received signal point is corrected by selecting the most likely transition sequence of the received signal based on the evaluation value. This is called Viterbi decoding determination.
- the signal points determined by the second determination circuit 38 are supplied to a coordinate-to-data sequence conversion circuit 44, and the coordinate-to-data sequence conversion circuit 44 performs mapping with a binary number of 6-bit data at each signal point arrangement.
- the matching circuit converts the decision coordinate points into 6-bit data and outputs the data to the bit processing circuit 46.
- the bit processing circuit 46 performs descrambling processing, etc., and outputs received data to the terminal by connecting data of 6 bits each. ⁇ Furthermore, in the apparatus shown in FIG. Is provided.
- the frame out-of-synchronization determination circuit 5 is provided with a demodulation reception point from the coordinate rotation circuit 34, a hard decision point from the first determination circuit 36, and a soft decision point from the second determination circuit 38.
- the out-of-frame determining circuit 5 includes error calculating circuits 50 and 52, a difference calculating circuit 54, an averaging circuit 56, and a determining circuit 58.
- the error calculation circuit 50 calculates the distance on the complex plane between the demodulated reception point and the determination point of the first determination circuit 36 as a hard decision error E 1.
- the error calculation circuit 52 calculates the distance on the complex plane between the demodulated reception point and the soft decision point of the second decision circuit 38 as a soft decision error E 2.
- the hard decision error ⁇ ⁇ 1 and the soft decision error ⁇ 2 calculated by the error measuring circuits 50 and 52 are given to a difference operation circuit 54, and the difference “ ⁇ 2 — ⁇ 1” of the two is given by a difference operation circuit 54. Minode is done.
- Output of difference calculation circuit 54 Power is applied to the averaging path 56.
- the averaging circuit 56 for example, an average of the difference values for several frames is obtained.
- the judgment circuit 58 finally compares the average with a predetermined ⁇ value, and when the average value becomes equal to or more than the Y value, generates a judgment output indicating that the frame is out of synchronization.
- the switch circuit 42 Prior to data transmission, the switch circuit 42 is switched to the training signal generation circuit 14 side, and a training signal is transmitted from the training signal generation circuit 14 to the reception side 2. Is done.
- the receiving side 2 receives the training signal from the transmitting side 1 and performs line compensation processing such as pull-in of an automatic equalizer provided in the demodulation circuit 26, and also performs training by the frame phase detection circuit 32.
- a frame synchronization signal contained in the transmission signal is detected, and the timing of the frame phase of the frame phase generation circuit 12 provided on the transmission side 1 is detected. For this reason, the frame phase detection circuit 32 detects the phase difference between the transmission-side frame phase information and the reception-side frame phase information, that is, the amount of delay, and the frame phase detection circuit 32 The delay amount is adjusted to the detected delay amount ⁇ .
- the frame phases on the transmitting and receiving sides match.
- the frame of the received signal obtained through the signal delay of the variable delay circuit 30 by setting the delay amount ⁇ of the variable delay circuit 30 based on the frame synchronization signal is the frame phase information of the frame phase generation path 28. Will be matched.
- the transmitting side 1 starts data transmission of transmission data from the terminal.
- a 6-bit bit sequence is extracted from the transmission data in synchronization with the modulation synchronization signal for each modulation, and the length is reduced by encoding the lower 2 bits in the trellis encoding circuit 16.
- the data is converted into a 7-bit string with one bit added, and output to the data string-to-coordinate conversion circuit 18 via the switch circuit 42.
- FIG. 4 shows an example of a signal point arrangement of trellis coded modulation.
- the data string-to-coordinate conversion circuit 18 converts the data into signal point coordinates by a mapping path having a signal point arrangement corresponding to the input 7-bit binary number at this time, and outputs the signal point coordinates to the coordinate rotation circuit 20. .
- the frame rotation information is given to the coordinate rotation circuit 20 from the frame phase generation circuit 12, and the coordinates of the four signal points in the first half of the frame phase information are defined on the complex plane.
- a coordinate rotation of 0, for example, + 90 ° is performed as 0, and the coordinates of the four signal points included in the second half frame are output to the modulation circuit 24 as non-rotated.
- the signal point coordinates sequentially output through the coordinate rotation circuit 20 are converted by the modulation circuit 24 into a real axis.
- the coordinate value of (Re) is modulated by cos wt, while the coordinate of the imaginary axis (I m) is modulated by sinwt advanced by 90 °, and the combined signal of both is output to the communication object 6.
- the demodulation circuit 26 demodulates the signal point coordinates from the received signal of the communication line 6, and the variable delay circuit 30 delays the signal by the amount of delay r set at the time of receiving the training signal.
- the synchronization is given to the coordinate rotation circuit 34 by synchronizing the system phases.
- the coordinate rotation circuit 34 is based on the phase information from the frame phase generation circuit 28, that is, based on the frame phase information (FIG.
- the coordinates of the reception point subjected to the coordinate rotation by the coordinate rotation circuit 34 are given to the second determination circuit 38, and most likely by Viterbi decoding processing.
- the coordinate-to-data sequence conversion circuit 44 converts the error-corrected received signal point to 6-bit data using a mapping circuit, and performs a process such as descrambling in a bit processing circuit 46. Then, it connects the 6-bit data received for each modulation and sends the received data to the appropriate terminal.
- the frame out-of-synchronization determination circuit 5 uses the determination points from the first determination circuit 36 and the second determination screen 38, which are obtained each time a modulation signal of one modulation is received, and the actual reception points.
- the hard decision error E 1 and the soft decision error E 2 are calculated in each of the error calculation paths 50 and 52, the difference between them is obtained by the difference circuit 54, and the averaging circuit 56 averages a predetermined number of frames. And the result is sent to the decision circuit 58.
- both the hard decision error E1 and the soft decision error E2 greatly change due to the characteristics on the line, and if the line characteristics are stable, only the increase in the soft decision error due to the loss of frame synchronization is detected. Loss of frame synchronization can be determined.
- the characteristics of the line fluctuate greatly. Therefore, by taking the average of the difference between the two decision errors, the error amount caused by the line characteristics is eliminated, and the frame synchronization is accurately lost based on the average value of the change in the soft decision error caused by the frame synchronization loss. Can be determined.
- the frame phase information is generated by dividing the inside of one frame into the first half and the second half.
- the invention is not limited to this. It may be the selected frame phase information.
- the apparatus shown in Fig. 1 is an example in which the rotation of the signal point coordinates is performed 90 'on the complex plane.However, the present invention is not limited to this. The amount of rotation may be used.
- FIG. 4 An apparatus according to another embodiment of the present invention is shown in FIG. 1. The operation of the FIG. 4 apparatus is illustrated in FIG.
- the Fig. 4 device is technically closely related to the above Fig. 1 device. 19 Compare with the specified bridge value.
- the demodulation synchronization signal (Fig. 2 (8)) becomes 7 or less at one frame interval, and the receiving-side frame phase shifts.
- the modulated signal contained in the rotating frame on the transmitting side corresponds to the non-planar frame without timing on the reverse rotating frame on the receiving side.
- the modulated signal contained in the non-picture frame on the transmission side corresponds to the reverse rotation frame on the reception side.
- the frame out-of-synchronization determination circuit 5 since the frame out-of-synchronization is determined based on the average value of the hard decision error E1 and the soft decision error E2, the error amount due to the surface line characteristics is determined. And it is possible to accurately determine out-of-frame synchronization. Switch to output selection of these transmission data.
- the trellis ⁇ circuit 110 as an error control coding means performs coding for error control according to a transition rule that restricts a transition of a signal point to be transmitted on a complex plane according to a predetermined procedure for a transmission signal. Perform
- a 6-bit bit string “Q6n Q5n Q4n fi3n Q2n Qln” is given to the trellis coding circuit 110 from the bit processing circuit 300 via the selection switching circuit 180 for each modulation.
- Can be The low-order 2 bits of this bit string "Q2n QlrT” are encoded using a differential encoder and a convolutional encoder to generate a subset "Y2n Yin Yn” with one redundant bit added
- the encoded signal is output.
- the output of the trellis coding circuit 110 is supplied to a bit sequence-to-coordinate conversion circuit 340, which converts the signal point coordinates on the phase plane as a complex plane corresponding to the transmission bit sequence. Is output.
- the signal point coordinates on the complex plane with respect to the input ⁇ bit string, which is converted by the bit string to coordinate conversion circuit 340 from the trellis coding circuit 110, are as shown in FIG. 3, for example.
- the output of the bit string-to-coordinate conversion circuit 340 is supplied to a modulation circuit 140 via a selection switch circuit 160 as first transmission signal selection means.
- the selection switch circuit 160 is a bit sequence to coordinate transformation west. Therefore, in practical use, it is preferable to use the technology of the Fig. 1 device and the technology of the Fig. 4 device together.
- the transmission side 1 and the reception side 2 are connected via a communication line 6 such as a telephone line, and after encoding user data as transmission data to the transmission side 1 for error control,
- the signal is modulated by phase modulation or quadrature width modulation and transmitted to the communication plane 6, while the receiving side 2 demodulates the signal received from the communication plane 6 and performs error correction by the maximum likelihood decoding method.
- Play transmitted data user data
- the transmission side 1 is provided with a bit processing circuit 300, and transmission data is provided to the bit processing circuit 300 from a user terminal as a transmission terminal, and the transmission data is scrambled. After performing bit processing such as the above, it is divided into the number of bits to be transmitted for each modulation and output.
- the bit processing unit 300 outputs a bit string “E16n Q5n Q4n Q3 n 02n airT divided into 6 bits per modulation.
- n is an integer indicating the number of modulations.
- Reference numeral 180 denotes a selection switch as second transmission signal selection means, and the selection switch 180 outputs an error control code to the output of the bit processing circuit 300 and the output of the high-speed signal generation circuit 280 as an encoded signal generation circuit.
- Switching to the conversion circuit (trellis code path) 110 That is, the selected switch image path 180 transmits the high-speed signal from the high-speed signal generation circuit 280 for a predetermined time from the time when encoding and decoding are started in a start-up stage prior to transmission of transmission data.
- Output to trellis coding circuit 110, and then to bit processing circuit 300 The output of the path 340 and the output of the low-speed signal generation circuit 260 as an uncoded signal generation circuit are switched to the modulation circuit 140.
- the selection switch circuit 160 Selects the output of the low-speed signal generation circuit 260 and sends the low-speed signal to the communication line 6 via the modulation circuit 140 for a fixed period of time, and when the transmission of the low-speed signal ends, the bit string to coordinate conversion
- the output of the circuit 340 that is, the signal output encoded by the trellis encoding circuit 110 is selected.
- the modulation circuit 140 generates a modulation signal corresponding to the coordinate input of the transmission signal point on the complex plane. Specifically, the amplitude value of the real axis (Re) at the signal point input coordinate on the complex plane is represented by the amplitude cos wt. Then, the amplitude value of the imaginary axis (I m) is amplitude-modulated by sinwt advanced in phase by 90 °, and these are combined and output to the communication line 6.
- a demodulation circuit 200 demodulates the modulated signal received from the communication line 6 and outputs the coordinates of the received signal point on the complex plane. That is, the received modulated signal is
- Cos ⁇ t and sin w t are used for synchronous detection to reproduce the amplitude component of the real number (Be) and the amplitude component of the imaginary number axis (), and detect the coordinate data of the received signal point.
- the demodulated output of the demodulation circuit 200 that is, the coordinate data of the received signal point is supplied to an error control signal decoding circuit 220 as an error control decoding means, and the transition rule of the signal point restricted on the transmission side is used to determine the final value.
- the transition rule of the signal point restricted on the transmission side is used to determine the final value.
- the error control signal demodulation circuit 220 has an evaluation value for each of a plurality of reception sequences determined by the transition rules of signal points restricted on the transmission side, and updates the evaluation value each time a signal is received.
- the signal sequence of the most likely received signal is selected based on the updated evaluation values, and the error at the received signal point is corrected.
- the coordinate data of the reception point which has been subjected to the error correction by the maximum likelihood decoding circuit 220, is provided to a coordinate-to-bit string conversion circuit 360.
- the coordinate-to-bit string conversion circuit 360 outputs a bit string corresponding to the input coordinates of the receiving point on the complex plane. Since the device shown in Fig. 4 is an example of the case of transmitting a bit string of 6 bits per modulation, the bit string "Q6n Q5n Q4n Q3 n Q2n Q liT power is output from the coordinate-to-bit string conversion circuit 360.
- the bit string output from the coordinate-to-bit string conversion area 360 is supplied to a bit processing circuit 380, and the bit strings divided for each modulation are joined together, and the bits such as descrambling are added together. Performs the processing and outputs the received data to the terminal device on the receiving side.
- the numerical value setting circuit 240 for evaluation is applied to the error control signal decoding image 220 provided on the receiving side 2. It is provided.
- the evaluation value setting circuit 240 is updated by the first received high-speed signal when the transmission signal from the transmitting side 1 is switched from an uncoded low-speed signal to an encoded high-speed signal. The new evaluation value is set to the error control signal decoding circuit 220.
- the evaluation numerical value set by the evaluation numerical value setting means 240 is a predetermined number or more of the high-speed signal decoded from the transmitting side 1. In the case of reception, an evaluation numerical value representing a transition sequence of a received signal which can be taken by the error control signal decoding circuit 220 is used.
- the selection switch circuit 160 switches to the low-speed signal generation circuit 260 side, and the low-speed signal generation circuit 260
- the signal is supplied to the modulation circuit 140 via the selection switch circuit 160, and the low-speed signal modulated by the modulation circuit 140 is transmitted to the communication line 6.
- the received signal from the communication line 6 is demodulated by the demodulation circuit 200 to reproduce the low-speed signal, the error control signal decoding circuit 220 provided on the receiving side 2, the coordinate-to-bit string conversion circuit 360, and bit processing
- the start operation of the circuit 380 and other necessary circuit parts is performed. At the time of starting by receiving the low-speed signal, the decoding operation by the error control signal decoding circuit 220 is not performed.
- the selection switch circuit When transmission of the low-speed signal over a certain period of time from time t1, that is, continuous data of a predetermined number of bits is completed, the selection switch circuit
- the reference numeral 160 disconnects the output of the low-speed signal generation circuit 260 and connects the output of the bit string to coordinate conversion circuit 340 to the modulation circuit 140.
- the selection switch circuit 180 selects the output of the high-speed signal generation circuit 280 that is activated at the same time, and sets a bit predetermined in this transmission system.
- the high-speed signal having the pattern is supplied to the error control coding circuit 110.
- the high-speed signal generation circuit 280 outputs a 6-bit bit string having a fixed bit pattern, and outputs the bit pattern.
- One is the repetition of the same pattern or the repetition and output of multiple types of bit patterns that change according to a predetermined procedure.
- the high-speed signal obtained through the selection switch circuit 180 is converted into a 7-bit string to which one redundant bit is added by an encoding process for error control by an entertainment control encoding circuit 110.
- the bit-to-coordinate conversion circuit 340 converts the data into the coordinate data of the signal point on the complex plane corresponding to the 7-bit string, and modulates the data by the modulation circuit 140 via the selection switch circuit 160. Output to communication object 6.
- the time of the low-speed signal is not shown on the receiving side. It is measured by a timer, and when a certain time has elapsed, the timing of supply of the signal point coordinate data is known.
- the error control signal decoding circuit 220 updates the evaluation value set in advance by the evaluation value setting means 240 based on the received and demodulated signal point coordinates. Based on the numerical values, the error of the demodulated signal point coordinates is corrected so that the signal point coordinates follow the transition sequence of the received signal.
- the error control signal decoding circuit 220 when the first encoded high-speed signal is received, the error control signal decoding circuit 220 also needs to update the evaluation value to be updated because the previously encoded high-speed signal has not been decoded. It does not exist. However, in the apparatus shown in FIG. 4, the evaluation numerical value setting means 240 apparently exceeds the predetermined number. The same situation is created as when the high speed signal was received and the error control signal was decoded. Therefore, in the apparatus shown in FIG. 4, the evaluation value on the receiving side has coherence in view of the transition rule of the transmission signal, and the error control signal decoding circuit is provided even immediately after the transmission switching of the decoded high-speed signal. At 220, correct error correction can be performed.
- the coordinate of the received signal point whose error has been corrected by the error control signal decoding circuit 220 is converted into a 6-bit bit string by a coordinate-to-bit string conversion circuit 360, and then divided by a bit processing circuit 380 for each modulation. It is converted to the received data that combines the bit strings.
- the selected switch surface 180 of the transmission side 1 disconnects the output of the high-speed signal generation circuit 280 and bit
- the output of the signal processing circuit 300 is connected to the error control coding circuit 110, and the transmission data is subjected to bit processing such as scrambling, and then divided into 6-bit strings for each modulation, and error control coding is performed.
- the signal is output to the circuit 110 and, like the high-speed signal, is coded for error control and sent to the receiver 2.
- the receiver 2 always corrects the received data by error correction by the error control signal decoding circuit 220. Obtainable.
- the device shown in Fig. 4 is an example in which data is transmitted after being divided into 6-bit bit strings per modulation.However, the invention is not limited to this, and the number of bits per modulation depends on the transmission speed. Can be appropriately selected according to the conditions.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP90909375A EP0429674B1 (en) | 1989-06-13 | 1990-06-13 | Modem capable of detecting out-of-frame synchronism condition |
US07/635,520 US5319650A (en) | 1989-06-13 | 1990-06-13 | Modulator-demodulator device capable of detecting an unsynchronized frame state |
DE69030053T DE69030053T2 (de) | 1989-06-13 | 1990-06-13 | Modem fähig zur detektierung von synchronzuständen ausserhalb eines rahmens |
US08/053,804 US5572537A (en) | 1989-06-13 | 1993-04-29 | Modulator-demodulator device capable of detecting an unsynchronized frame state based on hard and soft error values |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1151272A JPH088562B2 (ja) | 1989-06-13 | 1989-06-13 | フレーム同期外れ検出方式 |
JP1/151272 | 1989-06-13 | ||
JP1164624A JP2610999B2 (ja) | 1989-06-27 | 1989-06-27 | データ伝送装置の誤り制御方式 |
JP1/164624 | 1989-06-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1990016123A1 true WO1990016123A1 (fr) | 1990-12-27 |
Family
ID=26480573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1990/000769 WO1990016123A1 (fr) | 1989-06-13 | 1990-06-13 | Modem capable de detecter des conditions de synchronisme hors bloc |
Country Status (6)
Country | Link |
---|---|
US (3) | US5319650A (ja) |
EP (2) | EP0721265B1 (ja) |
CA (1) | CA2034007C (ja) |
DE (2) | DE69033637T2 (ja) |
ES (1) | ES2098268T3 (ja) |
WO (1) | WO1990016123A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2817785B2 (ja) * | 1996-06-20 | 1998-10-30 | 日本電気株式会社 | 自動識別点制御識別器およびその制御方法 |
US6031873A (en) * | 1996-06-24 | 2000-02-29 | 3Com Corporation | Nested shell mapping |
US6101216A (en) * | 1997-10-03 | 2000-08-08 | Rockwell International Corporation | Splitterless digital subscriber line communication system |
US6735724B1 (en) * | 1999-04-08 | 2004-05-11 | Texas Instruments Incorporated | Detection error estimation and method |
JP3545726B2 (ja) * | 2001-02-27 | 2004-07-21 | 松下電器産業株式会社 | 受信側装置 |
EP3624412B1 (en) * | 2017-06-27 | 2022-06-08 | Mitsubishi Electric Corporation | Likelihood generation device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS61118049A (ja) * | 1984-11-14 | 1986-06-05 | Fujitsu Ltd | デ−タ伝送方式 |
JPS61137447A (ja) * | 1984-12-07 | 1986-06-25 | Mitsubishi Electric Corp | 多相psk信号の復号装置 |
JPS6310837A (ja) * | 1986-03-24 | 1988-01-18 | Nec Corp | フレ−ム同期はずれ検出方式 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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US4146841A (en) * | 1977-09-28 | 1979-03-27 | Harris Corporation | Technique for combatting jitter in multiple phase transmission system |
CH656760A5 (de) * | 1981-11-11 | 1986-07-15 | Landis & Gyr Ag | Verfahren und anordnung zur sicherstellung der start-synchronisation eines aus bit-impulsfolgen bestehenden telegramms innerhalb eines empfaengers. |
US4546322A (en) * | 1983-08-24 | 1985-10-08 | Reliance Electric Company | Adaptable demodulator for arbitrary amplitude and phase keyed modulation signals |
US4756007A (en) * | 1984-03-08 | 1988-07-05 | Codex Corporation | Adaptive communication rate modem |
JPS60213150A (ja) * | 1984-04-06 | 1985-10-25 | Nec Corp | 符号方式 |
JPS60214150A (ja) * | 1984-04-09 | 1985-10-26 | Fujitsu Ltd | デ−タアクセスユニツトの試験方法 |
JPS6333028A (ja) * | 1986-07-26 | 1988-02-12 | Nec Corp | 信号検出方式 |
US5001729A (en) * | 1987-05-26 | 1991-03-19 | Hayes Microcomputer Products, Inc. | High speed half duplex modem with fast turnaround protocol |
US4891806A (en) * | 1987-09-18 | 1990-01-02 | Racal Data Communications Inc. | Constellation multiplexed inband secondary channel for voiceband modem |
US4873766A (en) * | 1988-04-25 | 1989-10-17 | Johnston Robert H | Power saw |
JPH06310837A (ja) * | 1993-04-23 | 1994-11-04 | Nec Toyama Ltd | 印刷配線板及びその製造方法 |
-
1990
- 1990-06-13 EP EP96104775A patent/EP0721265B1/en not_active Expired - Lifetime
- 1990-06-13 DE DE69033637T patent/DE69033637T2/de not_active Expired - Fee Related
- 1990-06-13 CA CA002034007A patent/CA2034007C/en not_active Expired - Fee Related
- 1990-06-13 ES ES90909375T patent/ES2098268T3/es not_active Expired - Lifetime
- 1990-06-13 EP EP90909375A patent/EP0429674B1/en not_active Expired - Lifetime
- 1990-06-13 WO PCT/JP1990/000769 patent/WO1990016123A1/ja active IP Right Grant
- 1990-06-13 DE DE69030053T patent/DE69030053T2/de not_active Expired - Fee Related
- 1990-06-13 US US07/635,520 patent/US5319650A/en not_active Expired - Fee Related
-
1993
- 1993-04-29 US US08/053,803 patent/US5574737A/en not_active Expired - Lifetime
- 1993-04-29 US US08/053,804 patent/US5572537A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61118049A (ja) * | 1984-11-14 | 1986-06-05 | Fujitsu Ltd | デ−タ伝送方式 |
JPS61137447A (ja) * | 1984-12-07 | 1986-06-25 | Mitsubishi Electric Corp | 多相psk信号の復号装置 |
JPS6310837A (ja) * | 1986-03-24 | 1988-01-18 | Nec Corp | フレ−ム同期はずれ検出方式 |
Non-Patent Citations (1)
Title |
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See also references of EP0429674A4 * |
Also Published As
Publication number | Publication date |
---|---|
ES2098268T3 (es) | 1997-05-01 |
US5319650A (en) | 1994-06-07 |
EP0429674A4 (en) | 1993-05-12 |
DE69030053D1 (de) | 1997-04-10 |
EP0721265B1 (en) | 2000-09-27 |
DE69033637D1 (de) | 2000-11-02 |
EP0721265A2 (en) | 1996-07-10 |
EP0429674A1 (en) | 1991-06-05 |
US5574737A (en) | 1996-11-12 |
DE69030053T2 (de) | 1997-06-12 |
US5572537A (en) | 1996-11-05 |
CA2034007C (en) | 1997-09-09 |
CA2034007A1 (en) | 1990-12-14 |
DE69033637T2 (de) | 2001-02-08 |
EP0429674B1 (en) | 1997-03-05 |
EP0721265A3 (en) | 1996-11-27 |
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