WO1987000938A1 - Procede de fabrication de cartes a circuits imprimes - Google Patents

Procede de fabrication de cartes a circuits imprimes Download PDF

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Publication number
WO1987000938A1
WO1987000938A1 PCT/US1986/001270 US8601270W WO8700938A1 WO 1987000938 A1 WO1987000938 A1 WO 1987000938A1 US 8601270 W US8601270 W US 8601270W WO 8700938 A1 WO8700938 A1 WO 8700938A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper
traces
holes
areas
tin
Prior art date
Application number
PCT/US1986/001270
Other languages
English (en)
Inventor
Gary B. Larson
Stanley J. Ruszczyk
Steven A. Castaldi
Original Assignee
Macdermid, Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macdermid, Incorporated filed Critical Macdermid, Incorporated
Publication of WO1987000938A1 publication Critical patent/WO1987000938A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present invention relates to printed circuit boards of the type having a solder mask over non-reflow- able metal, such as bare copper traces etched on a suit ⁇ able substrate, and, more particularly to a method of manufacture of such circuit boards and to the unique printed circuit boards resulting therefrom.
  • the manufacture of double-sided printed circuit boards requires the provision of conductive through-holes for interconnecting components on opposite sides of the board.
  • the non-conductive surfaces exposed when through-holes are drilled in a non-conductive substrate having metal cladding on both sides must, therefore, be provided with a conductive coating, and this generally is accomplished by a first electroless deposition of copper onto the suitably conditioned through-hole surfaces, followed by electroplating of copper to build up additional thickness.
  • plating resists so as to prevent all but particular areas of the board (through-holes and/or traces and/or pads and/or other areas) from receiving applied metal platings such as the copper electroplate used in through-hole plating or the commonly-employed tin-lead coating applied as an etch-resist preliminary to the step of etching away undesired metal down to the non-conductive substrate surface so as to form the appropriate conductive circuit pattern.
  • tin-lead is a preferred, overplating for otherwise exposed copper areas on the circuit board so as to prevent oxidative degrada ⁇ tion of the copper surfaces.
  • solderability of circuit pads and through-holes can be provided to the ultimate fabricator by having the manu ⁇ facturer precoat these areas with a solderable metal, generally a tin-lead composite closely similar in com ⁇ position to the solder actually used in the eventual soldering of components and connections.
  • a solderable metal generally a tin-lead composite closely similar in com ⁇ position to the solder actually used in the eventual soldering of components and connections.
  • soldering is to be conducted in mass techniques, such as with wave soldering or dip soldering methods, inadvertent soldering and improper connections can occur.
  • manufacturers apply a solder resist or solder mask over those areas of the board to be protected from solder, including the tin-lead coated copper traces.
  • solder resist over tin-lead coated copper can, however, lead to its own peculiar problems.
  • the tin- lead is a reflowable metal
  • ultimate wave or dip solder- ing can cause the tin-lead to wick up under the mask or simply to melt and no longer provide support for the mask.
  • This "solder mask over bare copper" (SMOBC) technique avoids the problems inherent in the application of the mask over tin-lead coated copper, and can yield printed circuit boards with finer line definition and higher current density capabilities.
  • SMOBC solder mask over bare copper
  • FIGS. 1A through 1J a typical SMOBC process is schematically set forth in the cross-sections represented by FIGS. 1A through 1J.
  • Layer thicknesses and through-hole sizes are not representative of either actual or relative scale.
  • a section of the printed circuit board is shown involving, on each side, one through-hole, one pad, and one trace line; the trace will be in association with a different pad and through-hole area on the board .not shown) , while the through-hole and pad will be associated with a different trace on the board (not shown).
  • a non-conductive substrate 10 typically an epoxy glass resin
  • a through-hole 14 has been drilled in the laminated board, and the inner hole surfaces are thus composed of the non-conductive substrate.
  • the through-hole surfaces must be made con ⁇ ductive.
  • the first step in this process is to electrolessly deposit a copper layer 16 on the entirety of the board, i.e.,. on the through-hole surfaces and on the copper foil 12 (conditioning and activating steps preliminary to copper deposition not shown).
  • the desired circuit pattern is then applied to the electroless copper layer through application and sub ⁇ sequent exposure and development of a negative photo ⁇ resist.
  • the areas of the photoresist exposed to light cross-link and become insoluble to developers which remove non-exposed, non-cross-linked areas.
  • an etch resist 22 is electroplated onto exposed copper surfaces as depicted in FIG. IE.
  • the plating resist 18 is removed (FIG. IF) in preparation for copper etching, the etching resulting in the configuration shown in FIG. 1G.
  • the solder mask is to be applied to bare copper, the tin-lead etch resist 22 is stripped away in -5-
  • solder mask 24 is applied to the board in a pattern appropriate to protect all areas where solder is undesired, as shown in FIG. II. Thereafter, the exposed copper at the holes and pads is cleaned and prepared for solder coating, and then solder coated by, e.g., hot air level solder to present the solder-coated surface 26 as shown in FIG. 1J. Electrolytic processes for application - of a solder coat cannot be employed in this method at this stage since the prior step of copper etching has removed the electrical continuity among areas of the board.
  • solder mask over bare copper while effective for elimi ⁇ nating problems inherent in application of solder mask to tin-lead coated copper, involve a number of steps which on their face appear almost duplicative but which never ⁇ theless are necessary to gain the advantages of SMOBC.
  • tin-lead is applied in the normal course of manufacture as an etch-resist over surfaces such as traces, pads and holes, and this tin-lead etch-resist is generally of the same or similar alloy composition as the solder eventually applied to the pads and holes.
  • a further object of the invention is to provide a process for ma ⁇ ufacturing boards of the type described which is economical in execution and eliminates problems present in known processes as to waste disposal.
  • a more particular object of the invention is to provide printed circuit boards, and methods for their manufacture, of the type containing solder-coated pads and through-holes, and bare copper traces having a directly-applied solder mask thereon.
  • Still another object of the invention is to provide printed circuit boards, and methods for their manu ⁇ facture, of the type having solder-coated pads and through-holes, bare copper traces having solder mask directly applied thereon, and additional bare copper surface configurations for application of other compon ⁇ ents and structures.
  • the method of the invention eliminates the need for stripping away of tin-lead etch resist and the need for subsequen _t application and leveling of molten solder.
  • a non-conductive substrate material of the type commonly employed for printed circuit boards is provided with through-holes and pads which surround the surface openings to the through holes.
  • the hole surfaces and the pad surfaces are built up of copper over which is applied a tin-lead plating.
  • Other surfaces of the non-conductive substrate are built up solely with copper, resistance to tin-lead plating being conferred by a suitable resinous plating resist which is applied to those copper surfaces, including those areas of the copper surface where traces or other surface configurations eventually will be patterned, and then stripped off after tin-lead plating is applied to pads and holes.
  • a resinous material resistant to copper etching solutions is applied to the copper surfaces in a pattern which defines the traces and any other desired surface con ⁇ figurations, while at the same time protecting them from copper etching.
  • Resistance to copper etching already is conferred to pads and holes by reason of the previously- applied tin-lead plate. Any exposed copper is then etched away down to the surface of the non-conductive substrate and the etch resist removed so as to expose bare copper in the desired pattern of traces and any other areas (e.g., lands for surface mount devices, bases for shield cans) desired.
  • solder mask may -8-
  • a non-reflowable metal coating can first be applied to at least the traces, followed by application of the solder mask over at least the non-reflowable metal.
  • the pad and hole areas containing tin-lead plating are not so masked, and thus present the desired solder coating without any need for tin-lead stripping and separate solder application.
  • the tin-lead coating on the pads and holes preferably- will be reflowed and solidified for provision of the desired solder coat.
  • the method of the invention eliminates the need for tin-lead stripping because tin-lead is applied only to those areas (pads, through- holes) which eventually are to be provided with solder coating.
  • the need for tin-lead plate on traces (which must be removed so as to permit solder mask over bare copper) is eliminated by utilization of resinous organic resist materials as the etch-resist for these areas.
  • FIGS. 1A through 1J represent schematic illustrations of a circuit board cross-section during its various stages in a known solder mask over bare copper manufacturing method.
  • FIGS. 2A through 2J schematically -illustrate by cross-section the manufacturing method of the present invention, there again being no attempt to accurately represent relative layer thicknesses, hole sizes, etc.
  • the depicted hole and pad areas are associated with traces (not shown) other than those shown, and the depicted traces are associated with holes and pads (not shown) other than the depicted hole and pads.
  • the method of the invention makes use of a conventional non-conductive substrate 100, typically having a nominal thickness of 0.059 inches, containing through holes 140, and having copper foil 120 laminated on both sides of the substrate (FIG. 2A) , generally in an amount to provide a coverage of about one ounce of copper per square foot on each side (0.0014 inches in thickness).
  • the copper foil surfaces 120 and the exposed non-conductive through hole surfaces are then treated according to any known electroless copper depositing process (including the various conditioning, activating, accelerating, rinsing steps involved in conditioning the surfaces and securing suitable deposition) to deposit a copper layer 160 thereon (FIG. 2B), generally of about 40 to 120 X 10 "6 inches in thickness. -10-
  • a plating resist 180 of suitable pattern is applied to the electroless copper surfaces.
  • the resist will be of the photosensitive type (negative or positive-acting) and can be of the dry film or liquid type. Dry film resists typically will be employed where it is desired that certain through-holes receive no further coatings, since the dry film will easily tent over and protect these holes.
  • the resist will be a negative photoresist in which exposure to light results in insolubilization (cross-linking) of the resist material, while those areas not exposed to light remain in a form which permits dissolution and removal with a suitable developer.
  • the plating resist on the copper layer will be as shown in FIG. 2C.
  • pads and through-holes are exposed in this configuration while areas of the board where traces eventually will be applied are protected by the resist.
  • the pads and holes, which are not protected with plating resist material, are then provided with an electroplated copper coating 200, (generally about 0.001 inches thick) as shown in FIG. 2D, utilizing any known plating technique and bath suitable for such purpose.
  • a tin-lead alloy 220 suitable both as an etch-resist and as the eventual solder coating for the through-holes and pads, is then electroplated onto the exposed pad and hole surfaces as shown in FIG. 2E, generally to a thickness of about 0.0003 inches.
  • the plating resist 180 is removed to provide a board as shown in FIG. 2F.
  • a liquid photosensitive resist which may be either a negative or positive resist, is applied to the surfaces 160 and exposed and -11-
  • the trace pattern is in the form of exposed, cross-linked resist, while unexposed, non-cross-linked areas are removed.
  • the trace pattern is in the form of unexposed, insoluble resist, while exposed, solubilized portions are removed.
  • the configuration of the board with the applied, exposed and developed resist 240 is schematically shown in FIG. 2G.
  • traces are now protected by the resist 240 while the pads and holes already have been plated with etch-resistant tin-lead 220.
  • exposed copper areas are removed with a suitable copper etchant to which the etch resist and tin-lead coating are resistant to arrive at the configuration shown in FIG. 2H.
  • the resist 240 is then stripped away to expose the bare copper traces as shown in FIG. 21.
  • a solder mask 260 is then applied over the bare copper traces and other areas to be protected from solder (FIG. 2J).
  • the entire board will be solder masked except those areas (pads, holes) where solder is desired.
  • the pads and through-holes are then "provided" with solder simply by the presence thereon of the previously-applied tin-lead etch resist 220. If desired, this tin-lead coating can be reflowed and solidified as known in the art to provide the solder coating.
  • the method of manufacture according to the present invention provides all the advantages of solder mask over bare copper techniques, while greatly simplifying the process, eliminating need for stripping of tin-lead, eliminating concern over waste disposal, and eliminating need for application and leveling of molten solder as the means for providing pads and through-holes with solder coat.
  • This method of manufacture has the advantage of providing the copper with improved corrosion resistance and improved solderability characteristics (for those areas which are not solder masked where subsequent component connections will take place), while still retaining all the advan ⁇ tages of solder mask over bare copper (as compared to solder mask over tin-lead) and, relative to other SMOBC methods, all the advantages of the present inventive manufacturing method.
  • the coating applied to the bare metal to be solder masked is a non-reflowable metal, the wicking and other problems encountered when solder mask is applied over tin-lead are avoided.
  • the method exhibits all the earlier-discussed advantages over prior art SMOBC techniques.
  • Suitable non-reflowable metals are those metals or metal compositions whose melting point is above the temperatures at which any operations subsequent to their application will occur.
  • the non-reflowable metals other than copper which can be used according to this mode of processing are immersion tin coatings, electro ⁇ less nickel-boron coatings and immersion gold coatings.
  • the various procedures and materials employed in the manufacturing method of the present invention are all known and used for the same or related individual pur ⁇ poses in the art.
  • the non-conductive substrate generally will be an epoxy glass resin although other resinous materials such as phenolic resins and polyimide may also be employed.
  • the composite board, i.e., non-conductive substrate clad on both sides with copper film is readily available from manufacturers in such form.
  • the bare copper traces which form the circuitry on the surface of the finished board may (for example as in the previously described detailed embodiment) consist (in terms of copper) only of the original copper foil provided on the starting board and the layer of electro ⁇ lessly deposited copper.
  • the traces are required to be of particular thickness for given applications, such thickness may be obtained by use of copper foil of sufficient thickness such that the overall thickness in conjunction with the later electro ⁇ less copper plate is of the desired specification, or by any other suitable method.
  • the starting boards are provided with at least about 0.5 ounces of copper foil per square foot on each side, and most preferably at least about 1.0 ounce of copper foil.
  • electroless copper coatings of from about 40 to 120 X 10 ⁇ 6 inches generally will be employed with the aforementioned thicknesses of copper foil.
  • the electroless copper deposition may be effected in any of the known manners using, for example, formaldehyde- reduced baths and the typical preliminary surface treating and catalytic activation sequences.
  • Application of a suitable pattern for the plating resist according to the invention can be effected by means of any of the known resist materials, including the known organic photoresists, ' and, as to these, can be employed with either positive or negative resists, dry film or liquid type.
  • these areas include trace precursor areas, i.e., those areas at which the traces subsequently will be patterned.
  • negative photoresist films are preferred, and a host of suitable such resist materials are known in the art.
  • the films chosen are those of a thickness generally equal to the final plating thickness in the unprotected areas so that mushrooming of the plating coat can be minimized.
  • Suit ⁇ able negative films are the Riston-series from duPont, Dynache Laminar and Hercules Aquamer, all of which are three-ply systems in which the film is drawn on a poly ⁇ ester backing sheet and then covered with a protective polymer film removed before lamination to the board surfaces. Once applied, the films are exposed through a light mask exhibiting the desired artwork configuration. Exposure results in cross-linking of the resist material and unexposed areas can then be washed away in dilute solutions of, e.g., sodium bicarbonate.
  • Electroplating of copper and tin-lead in sequence to the areas of the board not protected with resist may employ any of the methods (e.g., pyrophosphate or copper sulphate baths for copper and tin fluoborate, lead fluoborate, fluoboric acid for the tin-lead) known and available in the art.
  • the copper will be -15-
  • the resist film is stripped away using any solvent suitable for the type film employed, e.g., caustic if a fully aqueous film was used or an organic material such as methylene chloride for semi-aqueous or solvent-strippable resists, in an immersion or spray technique.
  • any solvent suitable for the type film employed e.g., caustic if a fully aqueous film was used or an organic material such as methylene chloride for semi-aqueous or solvent-strippable resists, in an immersion or spray technique.
  • the board is now ready for subsequent processing so as to attain solder mask over bare copper traces (or over copper coated with non-reflowable metal), but without the need for the costly and problematical methods of the prior art.
  • the key feature for achieving this goal is arranging on the required board areas a resinous material resistant to the subsequent copper etching. This preferably is attained by application, exposure and development of a liquid photoresist.
  • liquid positive or negative photoresist for this stage in the process is highly advantageous in terms of its ability to adhere and conform to the desired surfaces and its range of flexibility in building up a desired thickness.
  • the topography of the circuit board is not perfectly level, and known commercially available dry films could either crack along the edges of the traces (leaving those areas exposed and unprotected during etching) or tent over areas which should be etched.
  • Liquid resists can adhere to non-level surfaces and reduce or eliminate these problems.
  • the liquid resists can be applied to the board surfaces in any of the techniques known in the art, such as spray coating, roller coating, curtain coating or screening.
  • positive or negative liquid photo ⁇ resists each has certain characteristics which may make choice of one over the other expedient for certain applications. Each can conform and adhere to non-level surfaces and be applied to desired thickness. Positive resists have the advantage of being exposed and developed multiple times but, under some circumstances, plugging of through holes with positive liquid resists can occur. Thus, when positive liquid is used, the exposed areas are the areas which become solubilized and capable of being washed away, while the unexposed areas are those, that remain as the etch resist. If in the course of application the liquid resist bleeds into a hole, the difficulty in exposing that bleed-in to light of proper exposure for solubilization can lead to resist residues remaining in the hole which could break down electrical connections. Liquid negative resists, on the other hand, have reduced sensitivity to this problem since negative resist which might bleed into a hole can be washed away, because it is exposure which insolubilizes the negative resist material.
  • the liquid resist may be applied according to any known method to produce a variety of coating thicknesses which will provide etch resistance to the covered areas (generally on the order of 0.3 to 0.4 mil). Screening using a standard squeegee and mesh sizes from 110 to 310 threads per inch are appropriate. After application, the liquid resist is post-baked for removal of solvent contained therein, after which the resist is exposed to light in appropriate patterns and developed in, e.g., aqueous alkaline solutions. Any suitable positive or negative liquid resist may be employed, such as PR 64 (MacDermid, Inc., Waterbury, Connecticut (positive) and the 747 type microresists available from the Eastman Kodak Company (negative).
  • the resist remaining on the board surface defines and protects the traces in the board circuitry against subsequent etching, while pads and holes already are protected by their tin-lead coating.
  • Etching away of the copper in unprotected areas can be conducted using standard processes and materials that do not attack the liquid resist or the tin-lead, such as alkaline, ammonium chloride-based etchants and acid hydrogen peroxide-based etchants such as hydrogen- peroxide/sulfuric acid-based etchants, and the like.
  • the photoresist used to protect traces is stripped (e.g., using 20% caustic).
  • solder mask may then be applied at least to the now- exposed bare copper traces.
  • ease of appli- ⁇ cation usually dictates that all areas of the board except those areas where solder is to exist (pads, holes) be solder masked and, indeed, solder mask on the dielectric substrate will generally improve its insulation resistance.
  • solder mask is then applied over defined areas coated with non-reflowable metal, and, as earlier described, will generally be applied to all board areas except those where solder is to be present.
  • solder mask may be any of the known organic materials suitable for application to bare copper, non- reflowable metals and other board areas where protection from solder is required, such as Novoiak epoxy cured using a methylene dianiline catalyst.
  • the tin-lead coating on the pads and holes provides the requisite solder coating on these areas and, if desired, can be reflowed in conventional manner to render the deposit molten, accelerate alloying and produce a fused, dense, amorphous solder coat on solidification.
  • etch-resists used to define and protect copper traces can at the same time be patterned so as to define and protect other areas of the board surface, such as areas which serve as lands for surface mounted devices or bases for shield cans used for EMI-RFI shielding.
  • these areas exhibit an excep ⁇ tionally flat copper surface (made up, e.g., of the copper foil and electrolessly deposited copper) , highly suitable for effecting complete bonding and connections, and particularly, e.g., for surface mount devices.
  • These copper-exposed areas generally will be protected with an electroless or immersion coating of non-reflowable metal (such as immersion tin), particularly if reflow of the tin-lead on the pads and through-holes is to be effected.
  • non-reflowable metal such as immersion tin

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Cartes à circuits imprimés ayant des pastilles enrobées de soudure et des trous traversants (140) ainsi que des traces (160) en cuivre nu, protégées par un masque de soudure (260) qui est appliqué directement ou par une couche de métal ne devant pas refondre, et par un masque de soudure posé par-dessus. Les cartes sont fabriquées par un procédé qui évite la nécessité d'éliminer la couche d'étain/plomb et rend superflue l'application séparée de la soudure en fusion, ainsi que son égalisation. Dans le procédé préféré, des réserves liquides (240) sont appliquées aux cartes à circuits ayant des trous (140) plaqués au cuivre avec adjonction d'étain/plomb par-dessus, et des pastilles pour définir et protéger contre l'attaque les traces en cuivre (160) d'un circuit ayant la configuration désirée ou d'autres configurations. Des zones de cuivre autres que celles protégées par la réserve (240) et le placage étain/plomb (220) sont enlevées par attaque. La réserve (240) est ensuite enlevée et le masque de soudure (260) est appliqué aux traces en cuivre nu (160) ou à d'autres zones de cuivre nu, ou bien appliqué à du cuivre nu recouvert préalablement d'un métal que ne refond pas. Le placage étain/plomb (220) est ensuite de préférence refondu et solidifié pour garnir les pastilles et les trous traversants d'une couche de soudure.
PCT/US1986/001270 1985-08-08 1986-06-09 Procede de fabrication de cartes a circuits imprimes WO1987000938A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76381285A 1985-08-08 1985-08-08
US763,812 1985-08-08

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WO1987000938A1 true WO1987000938A1 (fr) 1987-02-12

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PCT/US1986/001270 WO1987000938A1 (fr) 1985-08-08 1986-06-09 Procede de fabrication de cartes a circuits imprimes

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EP (1) EP0233201A4 (fr)
JP (1) JPS63500837A (fr)
AU (1) AU5956286A (fr)
CA (1) CA1258138A (fr)
WO (1) WO1987000938A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2246243A (en) * 1990-05-18 1992-01-22 Nippon Cmk Kk Printed wiring boards

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293694A (ja) * 1988-05-23 1989-11-27 Mitsubishi Electric Corp プリント配線基板の製造方法

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GB2246243B (en) * 1990-05-18 1994-06-29 Nippon Cmk Kk Printed wiring board and method of manufacturing same

Also Published As

Publication number Publication date
AU5956286A (en) 1987-03-05
CA1258138A (fr) 1989-08-01
EP0233201A4 (fr) 1987-11-30
JPS63500837A (ja) 1988-03-24
EP0233201A1 (fr) 1987-08-26

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