JPS57145353A - Preparation of tape carrier type substrate - Google Patents

Preparation of tape carrier type substrate

Info

Publication number
JPS57145353A
JPS57145353A JP3087981A JP3087981A JPS57145353A JP S57145353 A JPS57145353 A JP S57145353A JP 3087981 A JP3087981 A JP 3087981A JP 3087981 A JP3087981 A JP 3087981A JP S57145353 A JPS57145353 A JP S57145353A
Authority
JP
Japan
Prior art keywords
tin
tape carrier
whisker
carrier type
type substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3087981A
Other languages
Japanese (ja)
Inventor
Masao Hayakawa
Takamichi Maeda
Fushinobu Wakamoto
Yasunori Senkawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3087981A priority Critical patent/JPS57145353A/en
Publication of JPS57145353A publication Critical patent/JPS57145353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To check the growth of a whisker of tin by subjecting a tape carrier type substrate to heat treatment after Sn plating is applied on the surface of an etched copper leaf on the substrate. CONSTITUTION:An Sn plating is applied uniformly on the surface of a copper leaf pattern on an insulator substrate 1. When heat treatment is conducted subsequently under the conditions of a temperature of 70-100 deg.C and of a time within five hours, copper-tin diffusion is promoted, the growth of the whisker 6 of tin can be checked, short-circuiting between conductors due to the whisker of tin is prevented, and thus the yield of the device is improved.
JP3087981A 1981-03-03 1981-03-03 Preparation of tape carrier type substrate Pending JPS57145353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3087981A JPS57145353A (en) 1981-03-03 1981-03-03 Preparation of tape carrier type substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3087981A JPS57145353A (en) 1981-03-03 1981-03-03 Preparation of tape carrier type substrate

Publications (1)

Publication Number Publication Date
JPS57145353A true JPS57145353A (en) 1982-09-08

Family

ID=12316017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3087981A Pending JPS57145353A (en) 1981-03-03 1981-03-03 Preparation of tape carrier type substrate

Country Status (1)

Country Link
JP (1) JPS57145353A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500837A (en) * 1985-08-08 1988-03-24 マツクダ−ミツド　インコ−ポレ−テツド Printed circuit board manufacturing method
WO2010061259A1 (en) * 2008-11-27 2010-06-03 Toyota Jidosha Kabushiki Kaisha Plating substrate having sn plating layer, and fabrication method therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53134364A (en) * 1977-04-28 1978-11-22 Nippon Mektron Kk Method of producing chip carrier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53134364A (en) * 1977-04-28 1978-11-22 Nippon Mektron Kk Method of producing chip carrier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500837A (en) * 1985-08-08 1988-03-24 マツクダ−ミツド　インコ−ポレ−テツド Printed circuit board manufacturing method
WO2010061259A1 (en) * 2008-11-27 2010-06-03 Toyota Jidosha Kabushiki Kaisha Plating substrate having sn plating layer, and fabrication method therefor

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