Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
  • H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
  • H10W76/10—Containers or parts thereof
  • H10W76/12—Containers or parts thereof characterised by their shape
  • H10W76/15—Containers comprising an insulating or insulated base
  • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the present invention relates to a semiconductor device having a structure in which a semiconductor element formed on one surface of a semiconductor chip is shielded from radiation radiated from a package component.
• a chip having a semiconductor element formed on one surface is fixed to a concave portion of a carrier made of an insulating material such as ceramic, and furthermore, a power gap is provided at a predetermined interval. C or sealed with a lid. It has a pocket structure.
• C. If the semiconductor device encapsulated in the package structure is composed of a MOS device (a charge transport device) and a ⁇ product circuit, c. Traces of trace elements present in the package components, semiconductors that are affected by radiation and other radiation emitted by the radioactive decay of radioactive elements such as aluminum The device is liable to malfunction and characteristic deterioration. In particular, ⁇ irradiation on the surface of a semiconductor element is an important obstacle. Therefore, the main purpose of the present invention is to prevent a semiconductor element formed on one surface of a semiconductor chip from being radiated from a package constituent member and being shielded from other radiation.
• the semiconductor device of the present invention has a chip having a semiconductor element formed on one surface, and the chip is fixed to a recess formed in a carrier made of an insulating material, and further has a predetermined interval. And sealed with a cap or lid.
• This semiconductor device comprises: (a) a heat-resistant insulating layer substantially containing a radioactive element; and (b) an insulating layer formed on the semiconductor element of the chip; ) It is characterized by having a radiation shielding metal layer formed on the layer of the insulator.
• the drawing is a cross-sectional view showing one example of the semiconductor device according to the present invention.
• a semiconductor element 2 is formed on one side of the silicon substrate chip 1.
• the semiconductor element 2 is derived from an integrated circuit such as a MOS device or an electric charge transfer device.
• an insulator layer 3 having heat resistance and containing substantially no radioactive element is formed on the semiconductor element 2. It is desirable to use a polyimide resin as an insulator having heat resistance.
• Line 0 is the particle dose rate 0.1 p Zc ⁇ 'h r. Or less, preferably
• the thickness of the heat-resistant insulator layer 3 is preferably in the range of 5 to 100 micron, particularly preferably in the range of 5 to 15 micron.
• the chip 1 is formed on the insulator layer 3
• Radiation shielding metal layer It has a radiation shielding metal layer 4. Radiation shielding metal layer
• the radiation shielding metal layer 4 is made of, for example, gold
• It may be a single layer, such as a tuck layer, or
• a combination of a nickel-deposited undercoat layer and a gold plating layer For example, a combination of a nickel-deposited undercoat layer and a gold plating layer
• Multi-layer such as a combination of layers and gold plating layers
• the heat-resistant insulator layer 3 is composed of the radiation shielding metal layer 4 and S i 0 2
• the semiconductor element 2 is formed exposed through the film
• No Bonn de fin grayed C 0 head 5 is arranged, which Raha 0 head 5 that are connected to the wiring of the integrated circuit 2.
• the drawing head 5 routes the wiring of the integrated circuit 2 through the indices and vias 6. It is connected to an external connection lead (not shown) provided on the package carrier 7.
• the semiconductor device of the present invention can be manufactured as follows. First, the semiconductor element 2 and the drawing device on one side. A silicon substrate chip on which a head 5 is formed is prepared. A polyimide resin is coated on one entire surface of the chip 1, and then the polyimide coating layer 3 is cured. After that, a gold film layer 4 having a thickness of several micro ⁇ is formed on the polyimide coating layer 3 by, for example, vapor deposition or plating. The chip on which the gold film layer is formed is subjected to an etch treatment to remove the gold film layer in other regions except for the region covering the semiconductor element 2. Thereafter, the polymide coating layer 3 is partially removed by treating the polymide coating layer with a solvent using the remaining gold film layer 4 as a mask. .
• the thus-prepared polymer coating layer 3 on the semiconductor element 2 and the gold film layer 4 on the polyimide coating layer 3 are formed as follows.
• the formed silicon substrate chip 1 is placed on a preform made of, for example, gold, which is previously placed in a recess of the carrier 7 made of an insulating material.
• the carrier 7 is heated to an appropriate temperature to form a silicon-gold eutectic, Attach the chip to the carrier.
• the connection between the head 5 and the lead through the winding wire 16 and the sealing of the whole apparatus in the furnace may be performed in a conventional manner.
• the semiconductor element is completely shielded from rays and other radiation radiated from the housing, such as a carrier, a power par or a lid. Therefore, the semiconductor device of the present invention does not cause malfunction or characteristic deterioration.

Landscapes

• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=13571920

Family Applications (1)

Country Status (4)

Cited By (4)

Families Citing this family (9)

Citations (1)

Family Cites Families (3)

• 1979
  • 1979-06-15 JP JP7528979A patent/JPS55166943A/ja active Granted
• 1980
  • 1980-06-14 DE DE8080901079T patent/DE3071242D1/de not_active Expired
  • 1980-06-14 WO PCT/JP1980/000131 patent/WO1980002891A1/ja not_active Ceased
  • 1980-12-30 EP EP80901079A patent/EP0029858B1/en not_active Expired

Patent Citations (1)

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