WO1980000900A1 - Amplificateur operationnel avec tension de decalage d'entree compensee - Google Patents

Amplificateur operationnel avec tension de decalage d'entree compensee Download PDF

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Publication number
WO1980000900A1
WO1980000900A1 PCT/CH1979/000102 CH7900102W WO8000900A1 WO 1980000900 A1 WO1980000900 A1 WO 1980000900A1 CH 7900102 W CH7900102 W CH 7900102W WO 8000900 A1 WO8000900 A1 WO 8000900A1
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WO
WIPO (PCT)
Prior art keywords
switch
operational amplifier
voltage
input
amplifier
Prior art date
Application number
PCT/CH1979/000102
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German (de)
English (en)
Inventor
J Vries
Original Assignee
Landis & Gyr Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Landis & Gyr Ag filed Critical Landis & Gyr Ag
Publication of WO1980000900A1 publication Critical patent/WO1980000900A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/38—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
    • H03F3/387—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
    • H03F3/393—DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only with field-effect devices

Definitions

  • the invention relates to an operational amplifier with compensated offset voltage according to the preamble of claim 1.
  • Integrated operational amplifiers are versatile differential amplifiers, which due to their construction on a single silicon wafer have a constant, tight thermal coupling of the switching elements. They each have an inverting and a non-inverting input and output and have a high input resistance and a high gain. However, they have the disadvantage that they do not act as ideal differential amplifiers in which the magnitude of the output voltage is zero with the same input voltages. In order to achieve the ideal output voltage zero, a certain compensating voltage called offset voltage must be superimposed on one of the inputs.
  • the known compensation circuits by means of a voltage divider connected into a supply line to an input of the operational amplifier or between the emitters or collectors of an input differential amplifier act purely statically and have thermal drift.
  • FIGS. 1 and 2 require an operational amplifier with a small offset voltage, so that no improvement is achieved in operational amplifiers integrated in MOS technology.
  • a second circuit, shown in FIG. 3, of a so-called chopper-stabilized operational amplifier is described in the book "Operational Amplifiers, Design and Applications" by J.G. Graeme, G.E. Tobey and L.P. Huelsmann, pp. 152 and 153 described which resistors and capacitors with high values, which are difficult to achieve in some integrated technologies, are required.
  • the present invention is the object. based on creating a circuit with offset voltage sufficiently compensated for precision purposes, which is suitable to be implemented in integrated MOS circuit technology without large capacitance and resistance values.
  • FIG. 3 shows a diagram of a chopper-stabilized operational amplifier
  • Fig. 5 is a diagram
  • Fig. 6 shows a partial circuit according to the invention.
  • the general, known scheme of an operational amplifier with dynamic compensation of the offset voltage according to FIG. 1 consists of an operational amplifier 3 connected to an input 1 for a voltage to be amplified, with an offset voltage Uov between an inverting - and a non-inverting + input in combination with a controller 2 with two inputs, the first of which is connected to the inverting input of the operational amplifier 3 and the second to a reference potential U ref ' , preferably zero.
  • the output of controller 2 is connected to the non-inverting + input of the operational amplifier.
  • Controller 2 is designed as an integral controller. It contains a second operational amplifier 5, which is connected to the inverting input of the operational amplifier 3 by means of a resistor 4 and has a capacitor 6 connected to its inverting input, connected to the resistor 4 and to its output, and its output to the non-inverting + input of the operational amplifier 3 is connected.
  • a circuit according to FIG. 3 which differs from the circuit described above for realizing an operational amplifier with a low offset voltage uses "chopper stabilization". It is described in the book “Operational Amplifiers, Design and Application” by JG Graeme, GE Tobey and LP Huelsmann, McGraw-Hill Kogakusha, Ltd., Tokyo, Düsseldorf, ea on pages 151 to 154. Their basic circuit is shown in Fig. 3. It has two branches with filters for the amplification of higher-frequency and lower-frequency or direct voltages, which are connected to the common input 1. One is branch connected to the inverting input of an operational amplifier 7 by means of a high-pass filter consisting of a capacitor 9 and a resistor 10.
  • the second branch consists of a resistor 12 and a capacitor 13 as a low-pass filter, a further resistor 14, a switch S 1 , a capacitor 15, an inverting AC amplifier 11, a capacitor C 1 in its output, a second switch S 2 and a second Low pass from a resistor 16 and a capacitor C 2 in connection with the non-inverting + input of the operational amplifier 7.
  • the switches S 1 and S 2 are controlled synchronously by a control circuit (not shown).
  • the chopper-stabilized amplifier described is not suitable for implementation in integrated MOS technology because of the high values which the capacitors and resistors used in the low-pass filters have, which are essential to achieve a sufficient filter effect.
  • the operational amplifier of FIG. 4 compensated for its offset voltage according to the invention, which is preferably embodied in the integrated MOS technology which has the known advantages, contains an integrating control circuit 2 with a series connection of an AC voltage amplifier 11 with a switching arm of a changeover switch S. 1 on the input side, the capacitor C 1 on the output side and the switching arm of a switch S 2, which is preferably connected to the latter via a resistor 17
  • the first switch contact of the switch S 1 is connected to the inverting input of the operational amplifier 3.
  • the first switch contact of the second switch S 2 is connected to the capacitor C 2 and the non-inverting + input of the operational amplifier 3.
  • the second switch contacts of the switches S 1 and S 2 are connected to the line with the reference potential U ref .
  • the switches S 1 and S 2 according to this FIG. 4 are push-pull switches and the AC voltage amplifier 11 is non-inverting. They are also inte in the MOS circuit freezes.
  • the switch S 1 of the circuit according to FIG. 4 can also be replaced by a series connection of a resistor 18 and an on / off switch S 1 according to FIG. 6, the switching arm on the line with the reference potential U ref and the switching contact on Connection point of the resistor 18 with the AC voltage amplifier 11 is located.
  • the offset voltage is continuously tapped by the regulator circuit 2, amplified and applied to the non-inverting + input of the operational amplifier 3. This amplified voltage counteracts the offset voltage occurring at the inverting input of the operational amplifier 3, as a result of which this can be more or less compensated for.
  • the known regulator circuit 2 according to FIG. 2 uses the low-drift operational amplifier 5 connected as an integrator, by means of which the amplified offset voltages are summed and by which they are transmitted to the non-inverting + input of the operational amplifier 3, as a regulator. Since it is difficult or even impossible in some technologies for the production of integrated semiconductor circuits, it is possible to produce operational amplifiers with particularly low drift and low offset voltages with larger offset voltages but other operational properties with other advantageous properties on the same chip the circuit according to FIG. 2 only a limited use.
  • the voltage occurring at input 1 is distributed over two branches.
  • the input voltage U a is a high-pass filter from the capacitor 9 and transferred to the resistor 10 to the inverting input of the operational amplifier.
  • the input voltage Uei.n is sifted through the low-pass filter consisting of the resistor 12 and the capacitor 13, chopped by means of the switch S .. and the chopped voltage via the capacitor 15 blocking the DC voltage, the inverting AC voltage amplifier 11 and the Capacitor C 1 for decoupling the amplified AC voltage is tapped in synchronism with the first switch S 1 by means of the second switch S 2 and sieved through the resistor 16 and the capacitor C 2 .
  • the resistor 16 also prevents a complete discharge of the capacitor C 2 when the switch S 2 is closed.
  • the voltage across the capacitor C 2 is supplied to the non-inverting + input of the operational amplifier 7. Due to the AC voltage coupling, the offset voltage is not effective in this type of operational amplifier.
  • the simple integrated compensation circuit according to the invention according to FIG. 4 can be explained on the basis of the diagram in FIG. 5.
  • this means ⁇ ) the token signals with sections t a and t b at the output of the control circuit (not shown in FIG. 4) for the switches S 1 and S 2 ; b) the profile of the offset voltage U off to the reference voltage U ref , which preferably has the value zero; c) the voltage U 11 at the output of the inverting AC voltage amplifier 11 and d) the voltage U C1 at the output of the capacitor C 1 .
  • the switches S 1 and S 2 are controlled cyclically by the signals according to FIG. 5a.
  • the offset voltage U off chopped by the switch S 1 is connected to the non-inverting AC amplifier 11 and appears at its output as voltage U 11 according to line c of FIG. 5.
  • voltage U C1 occurs after line d 5 on.
  • the capacitor C 1 is at the voltage A. U off charged.
  • A means the gain of the AC voltage amplifier 11.
  • Constant reference voltage U ref shown on the line according to lines b of FIG. 5.
  • the offset voltage U ov of the operational amplifier 3 is reduced to a very small amount, determined by the amplification of the AC voltage amplifier 11, which practically does not limit the usability of this circuit.
  • the product of the gain A of the AC amplifier 11 should be the ratio of the capacitances of the capacitors C 1 and C 2 according to the formula:
  • the clock frequency depends on the integration technology used and the use of the operational amplifier 3 to be compensated for in FIG. 4.
  • the two switches S 1 and S 2 work synchronously. For good functioning, it can be advantageous to control the switches S 1 and S 2 in such a way that the switch S 2 is activated somewhat earlier than the switch S 1 .
  • Resistor 17 has only a current-limiting function when transferring the charge from capacitor C 1 to capacitor C 2 and when charging C 1 . It is therefore of a small size and offers no difficulty in the implementation in an integrated MOS circuit.
  • the circuit with common mode switches S 1 and S 2 and with an inverting AC voltage amplifier 11 acts in the same way as that according to FIG. 4.
  • the switch S. according to FIG. 6 operates in an analogous manner to that in FIG. 4, the control being carried out in such a way that the switch S 1 closes in the excited state.
  • the circuits according to FIGS. 4 and 6 are very simple and can be easily integrated on a chip in any technology. They work reliably and a very small offset voltage, which does not limit the applicability, can be achieved, so that one can speak of a virtually complete compensation of the offset voltage.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

La compensation de la tension de decalage d'entree de l'amplificateur operationnel (3) est obtenue a l'aide d'un circuit de reglage comportant un premier commutateur (S1) qui preleve alternativement la tension de decalage (Uoff) et une tension de reference (Uref). Un deuxieme commutateur (S2) du circuit redresse, en synchronisme avec le premier commutateur (S1), la tension amplifiee delivree a travers un condensateur (C1) par un amplificateur de tension alternative (11) et charge un condensateur d'integration (C2) relie a l'entree non-inversee (+) de l'amplificateur operationnel. On utilise pour cela la technique d'integration MOS. Le produit de l'amplification A avec le rapport des capacites de C1 et C2: A. C1/C1 + C2 est inferieur a 2. Les commutateur (S1, S2) peuvent etre des commutateurs push-pull, l'amplificateur de tension alternative (11) etant non-reversible, ou des commutateurs en phase, l'amplificateur de tension alternative (11) etant alors reversible. Les commutateurs (S1, S2) ont des durees de commutation differentes. Le premier commutateur (S1) peut etre dispose de maniere a avoir son bras de contact mis au potentiel de reference (Ureff), une resistance etant montee entre l'entree (1) et le contact de commutation.
PCT/CH1979/000102 1978-10-13 1979-07-17 Amplificateur operationnel avec tension de decalage d'entree compensee WO1980000900A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH11373/78 1978-10-13
CH1137378A CH637509A5 (de) 1978-10-13 1978-10-13 Operationsverstaerker mit kompensierter offset-spannung.

Publications (1)

Publication Number Publication Date
WO1980000900A1 true WO1980000900A1 (fr) 1980-05-01

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PCT/CH1979/000102 WO1980000900A1 (fr) 1978-10-13 1979-07-17 Amplificateur operationnel avec tension de decalage d'entree compensee

Country Status (4)

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CH (1) CH637509A5 (fr)
IT (1) IT1123810B (fr)
WO (1) WO1980000900A1 (fr)
YU (1) YU246279A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4210212A1 (fr) * 2022-01-11 2023-07-12 Mediatek Inc. Appareil et procédé de commande de circuit élévateur de tension transitoire de régulateur de tension par l'intermédiaire de signaux de rétroaction obtenus par détection différentielle appliquée à un condensateur de sortie

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1357832A (fr) * 1963-03-01 1964-04-10 Dispositif stabilisant le zéro et annulant la dérive des amplificateurs de signaux continus
DE2239277A1 (de) * 1971-08-10 1973-02-22 Gen Motors Corp Gleichspannungsverstaerker

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1357832A (fr) * 1963-03-01 1964-04-10 Dispositif stabilisant le zéro et annulant la dérive des amplificateurs de signaux continus
DE2239277A1 (de) * 1971-08-10 1973-02-22 Gen Motors Corp Gleichspannungsverstaerker

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
EDN Electrical Design News, November 1965, Denver (USA) B.J. Barranger "FET Chopper samples microvolt signals", Seiten 38, 40, 41 siehe Seiten 40 und 41 *
Electron Engineering, vol. 30, no. 366, August 1958, London (GB) I.C. Hutcheon "Performance Calculations for D.C. Chopper Amplifiers", Seiten 476-480 siehe Seite 477, rechte Spalte, Zeile 217 bis Seite 478, rechte Spalte, Zeile 4 *
Electronics, vol. 27, no. 4, April 1954, New York (USA) D.W. Slaughter: "TimeShared Amplifier Stabilizes Computers", Seiten 188-190 siehe Seite 188, linke Spalte und mittelste Spalte; Zeilen 1-10; Seite 190, linke Spalte, Zeilen 23-53 *
Journal of the Institution of Electrical Engineers, vol. 2, no. 23, November 1956, London (GB) "DC Computer Amplifiers", Seiten 672-675 siehe Seite 674, linke Spalte, Zeilen 1-12, Figur 3b *
Philips Application Note, no. 185, November 1972, Eindhoven (NL) J. Oosterling: "Chopper Stabilized Operational Amplifier CSA70" siehe Seite 2, zweiter Absatz *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4210212A1 (fr) * 2022-01-11 2023-07-12 Mediatek Inc. Appareil et procédé de commande de circuit élévateur de tension transitoire de régulateur de tension par l'intermédiaire de signaux de rétroaction obtenus par détection différentielle appliquée à un condensateur de sortie

Also Published As

Publication number Publication date
IT1123810B (it) 1986-04-30
IT7926416A0 (it) 1979-10-11
CH637509A5 (de) 1983-07-29
YU246279A (en) 1982-06-30

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