US8878504B2 - Switching regulator - Google Patents

Switching regulator Download PDF

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US8878504B2
US8878504B2 US13/187,013 US201113187013A US8878504B2 US 8878504 B2 US8878504 B2 US 8878504B2 US 201113187013 A US201113187013 A US 201113187013A US 8878504 B2 US8878504 B2 US 8878504B2
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switching
pulse
control signal
stopping
load
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US20120091981A1 (en
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Yasuhide KOMIYA
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Morgan Stanley Senior Funding Inc
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Spansion LLC
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H02M2001/0032—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y02B70/16—

Definitions

  • the embodiment relates to a switching regulator.
  • a switching regulator generates internal power supply voltage which is used by a load circuit, from power supply voltage which is supplied.
  • a switching regulator which generates DC internal power supply voltage from a DC power supply voltage is also called a “DC-DC convertor”.
  • a switching regulator has a first transistor which is connected to a higher power supply voltage side, and a second transistor which is connected to a lower power supply voltage (ground) side, and supplies the output voltage to a load circuit via an LC smoothing circuit connected to the connection nodes of both transistors. By appropriately controlling the switching operation of both transistors, the output voltage is maintained at a desired potential.
  • the LC smoothing circuit is disposed outside an integrated circuit chip where the switching regulator is formed, or is disposed on the integrated circuit chip.
  • the switching regulator monitors the output voltage, and alternately turns the first transistor and the second transistor ON so that the output voltage is maintained at a desired potential. For example, if the load is heavy and the output voltage drops, the “ON” period of the first transistor is increased, so as to suppress a drop in the output voltage.
  • the switching regulator monitors the output current and controls the “ON” period of the first transistor according to the level of the output current, which changes according to the level of the output load.
  • the switching regulator is disclosed in the Japanese Patent Application Laid-Open No. 11-155281, and the Japanese Patent Application Laid-Open No. 2009-148111.
  • switching counts of both transistors are decreased in a light load state. For example, the switching frequency is lowered in a light load state to decrease the switching counts. Alternatively, the switching counts are decreased for a certain period by stopping the switching operation of both transistors in a light load state. Thereby when the load is light, a switching loss generated with the switching operation is decreased so as to improve efficiency.
  • a switching regulator having an output circuit which has a first transistor connected to a higher power supply side, a second transistor connected to a lower power supply side, and a connection node of the first transistor and the second transistor as an output terminal; a switching control unit which generates a first switching pulse and a second switching pulse for alternately switching the first transistor and the second transistor according to a load of a load circuit connected to the output terminal via a smoothing circuit; and a first comparator which monitors an output voltage generated through the smoothing circuit, and generates a pulse stopping control signal for stopping the generation of the first switching pulse and the second switching pulse when the output voltage rises, and for generating the first switching pulse and the second switching pulse when the output voltage drops.
  • the switching control unit performs a stopping operation for stopping the generation of the first switching pulse and the second switching pulse and a switching operation for generating the first switching pulse and the second switching pulse in response to the pulse stopping control signal, and outputs, to the first comparator, a timing control signal for quickening a switching timing from the stopping operation to the switching operation as the load of the load circuit increases.
  • FIG. 1 illustrates operation of the switching regulator.
  • FIG. 2 is a graph depicting the relationship of load current Io of the switching regulator and efficiency.
  • FIG. 3 is a block diagram of the electric current mode type switching regulator.
  • FIG. 4 illustrates the operation of the switching regulator in FIG. 3 .
  • FIG. 5 is a block diagram of a comparator type switching regulator.
  • FIG. 6 illustrates an operation of the switching regulator in FIG. 5 .
  • FIG. 7 is a block diagram of a switching regulator according to the first embodiment.
  • FIG. 8 is a block diagram of the pulse generation circuit 21 .
  • FIG. 9 is a circuit diagram of the PFM comparator COMP 1 .
  • FIG. 10 illustrates the operation of the switching regulator of the first embodiment.
  • FIG. 11 is a block diagram of a switching regulator according to the second embodiment.
  • FIG. 12 is a block diagram of the pulse generation circuit.
  • FIG. 13 illustrates the operation of the switching regulator of the second embodiment.
  • FIG. 14 is a circuit diagram of a PFM comparator COMP 1 in the comparator type switching regulator according to the third embodiment.
  • FIG. 15 illustrates operation of the comparator type switching regulator according to the third embodiment.
  • FIG. 16 is a circuit diagram of the electric current mode type PFM comparator COMP 1 according to the fourth embodiment.
  • FIG. 17 illustrates the operation of the switching regulator according to the fourth embodiment.
  • a switching regulator has: an output circuit which has a first transistor connected to a higher power supply side, and a second transistor connected to a lower power supply side; and a switching control unit which generates a first switching pulse and a second switching pulse for alternately switching the first transistor and the second transistor according to a load of a load circuit which is connected to an output terminal, that is, a connection node of the first transistor and the second transistor, via a smoothing circuit.
  • a switching control unit which generates a first switching pulse and a second switching pulse for alternately switching the first transistor and the second transistor according to a load of a load circuit which is connected to an output terminal, that is, a connection node of the first transistor and the second transistor, via a smoothing circuit.
  • FIG. 1 illustrates operation of the switching regulator.
  • the switching control unit continuously generates the first switching pulse and the second switching pulse on which pulse width modulation (PWM) was performed according to the load of the load circuit.
  • PWM pulse width modulation
  • the pulse width of the switching waveform is constant, but actually the pulse width is controlled according to the load. For example, as the load becomes heavier, the “ON” time of the first transistor is increased, and as the load becomes lighter, the “ON” time is decreased. As a result, the output voltage is maintained to be approximately constant.
  • the switching control unit alternately repeats a switching operation period (SW in FIG. 1 ), where the first and second switching pulses are generated by pulse width modulation or the like, and a stopping period (ST in FIG. 1 ), where the generation of the first and second switching pulses is stopped.
  • SW in FIG. 1 switching operation period
  • ST in FIG. 1 stopping period
  • the first and second transistors perform the switching operation by PWM, while in the light load mode, the switching period SW and the stopping period ST are alternately repeated.
  • a kind of PFM is performed in the light load mode since the density of the switching pulses decreases.
  • FIG. 2 is a graph depicting the relationship of load current Io of the switching regulator and efficiency.
  • the efficiency is a ratio of the power supplied to the load circuit, with respect to the input power.
  • efficiency drops as the load becomes lighter, because the ratio of power consumption for the switching operation, with respect to the power supplied to the load circuit, is greater.
  • decreasing the current consumption in the stopping period ST in the light load state is indispensable to increase the efficiency. Therefore in the case of a comparator which controls the switching period SW and the stopping period ST when the load is light, the bias current is set to the minimum in order to minimize the current consumption during the stopping period.
  • FIG. 3 is a block diagram of the electric current mode type switching regulator.
  • the output voltage Vo to be supplied to a load circuit 10 is generated from the power supply voltage Vin.
  • the switching regulator has an output circuit having a P-channel MOS transistor PMOS (first transistor) which is connected to the power supply voltage Vin side (higher power supply voltage), and an N-channel MOS transistor NMOS (second transistor) which is connected to a ground Vss side (lower power supply voltage).
  • a smoothing circuit constituted by an inductor Lo and the capacitor Co is connected to a connection node LX of the two transistors.
  • the output voltage Vo is generated via the smoothing circuit.
  • the smoothing circuit constituted by the inductor Lo and the capacitor Co is, in many cases, disposed outside a semiconductor chip where the switching regulator is formed. But in some cases, the smoothing circuit may be disposed on the semiconductor chip.
  • the switching control unit 20 of the switching regulator has an error amplifier ERRAMP which amplifies the difference of feedback voltage FB generated by dividing the output voltage Vo by resistors Ra and Rb and the first reference voltage Vref 1 , and an I/V conversion circuit 22 , which converts the electric current IP, flowing through a resistor R 1 between the first transistor PMOS and the power supply voltage Vin, into voltage Vdr, and a second comparator (PWM comparator) COMP 2 which compares the converted voltage Vdr with differential voltage Verr which is output by the error amplifier ERRAMP, and outputs a pulse width modulation (PWM) signal PWM_out.
  • ERRAMP error amplifier
  • I/V conversion circuit 22 which converts the electric current IP, flowing through a resistor R 1 between the first transistor PMOS and the power supply voltage Vin, into voltage Vdr
  • PWM comparator COMP 2 second comparator
  • PWM pulse width modulation
  • the error amplifier ERRAMP controls so that the feedback voltage FB becomes equal to the first reference voltage Vref 1 .
  • the electric current Ip and the voltage Vdr converted therefrom, which depends on the weight of the load, are intermittently generated synchronizing with the switching operation of the first transistor PMOS. Therefore the PWM signal PWM_out is a pulse signal having a duty ratio in accordance with the weight of the load.
  • the error amplifier ERRAMP has a feedback capacitor C 1 , and if the load becomes heavy and the output voltage Vo decreases and the feedback voltage FB decreases, then the differential voltage Verr increases. If the load becomes light and the output voltage Vo increases, on the other hand, the differential voltage Verr decreases. In other words, the differential voltage Verr changes so as to have the opposite phase of the output voltage Vo.
  • the pulse width of the PWM signal PWM_out generated by the PWM comparator COMP 2 becomes wider. If the load becomes light, on the other hand, the voltage Vdr decreases and the pulse width of the PWM signal PWM_out becomes narrower.
  • the switching control unit 20 also has a pulse generation circuit 21 for generating the first and second switching pulses Pout and Nout, and an oscillator OSC for generating a reference clock OSC_REF. Synchronizing with the reference clock OSC_REF, the pulse generation circuit 21 generates the first and second switching pulses Pout and Nout of which duty ratio is controlled based on the PWM signal PWM_out.
  • the switching control unit 20 has a first comparator (PFM comparator) COMP 1 which compares the differential voltage Verr generated by the error amplifier (minus input), with a second reference voltage (PFM threshold voltage) pfmvth (plus input).
  • the PFM comparator COMP 1 determines the timings of the switching operation and the stopping operation in the PFM mode in the light load state. In other words, the PFM comparator COMP 1 sets an output signal compout to H level if the output voltage Vo rises and the differential voltage Verr falls, and sets the output signal compout to L level if the output voltage Vo falls and the differential voltage Verr rises.
  • the pulse generation circuit 21 stops the generation of the first and second switching pulses Pout and Nout if compout is in H level, and generates the first and second switching pulses Pout and Nout if compout is in L level.
  • the PFM comparator COMP 1 is a comparator for generating the PFM control signal compout.
  • the PFM control signal compout is a pulse stopping control signal
  • the second reference voltage pfmvth is the PFM threshold voltage for differentiating the stopping operation and the switching operation in the PFM mode.
  • the pulse generation circuit 21 continues to generate the first and second switching pulses Pout and Nout.
  • the PFM operation in the light load state on the other hand, the output voltage Vo ripples, and if the output voltage Vo rises, the PFM control signal compout becomes H level, the pulse generation circuit 21 enters the stopping operation where the switching pulse is not generated, and if the output voltage Vo falls, the PFM control signal compout has L level, and the pulse generation circuit 21 enters the switching operation where the switching pulse is generated.
  • FIG. 4 illustrates the operation of the switching regulator in FIG. 3 .
  • three light load states from light to heavy, and a heavy load state, are depicted.
  • the output current Io increases as the load becomes heavier.
  • the pulse generation circuit 21 continuously generates the PWM-controlled first and second switching pulses Pout and Nout.
  • the switching period SW where the first and second switching pulses are generated, and the stopping period ST where the first and second switching pulses are not generated, are alternately repeated.
  • the differential voltage Verr of the error amplifier ERRAMP changes to have the opposite phase of the output voltage Vo. If the differential voltage Verr becomes lower than the PFM threshold voltage pfmvth, the PFM control signal compout becomes H level, and the switching stopping period ST begins. This is as depicted with t 1 , t 3 and t 5 and T 1 , T 3 and T 5 in FIG. 4 . If the differential voltage Verr becomes higher than pfmvth, on the other hand, the PFM control signal compout becomes L level, and the switching period SW begins. This is as depicted with t 2 , t 4 and t 6 and T 2 , T 4 and T 6 in FIG. 4 .
  • the time T 1 to T 6 when the PFM control signal compout changes, require a certain delay time with respect to the time t 1 to t 6 when the differential voltage Verr crosses the threshold pfmvth.
  • the bias current is designed to be minimum in order to make the efficiency higher in the light load, therefore, the response speed of the first comparator COMP 1 is slow.
  • the first and the second transistors do not perform switching operation, hence no electric current is supplied to the smoothing circuit. Therefore the output voltage Vo drops during the stopping period ST due to the load current of the load circuit. Furthermore, as depicted in FIG. 4 , the voltage drop of the output voltage Vo is different depending on the level of the load, even within the light load state. The dropping level of the output voltage Vo is larger in the light load 3 state where load is heaviest than in the light load 1 state where load is the lightest.
  • FIG. 5 is a block diagram of a comparator type switching regulator.
  • a PFM comparator COMP 1 for generating a PFM control signal compout compares the feedback voltage FB generated by dividing the output voltage Vo by resistors Ra and Rb (minus input) with reference voltage (PFM threshold voltage) Vref 3 (plus input). The output of the PFM comparator COMP 1 becomes the PFM control signal compout via an invertor 24 .
  • a PWM circuit 23 monitors the output voltage Vo and generates a PWM pulse PWM_out, which is modulated to have a pulse width in according with Vo. Then based on the PWM pulse PWM_out, a pulse generation circuit 21 generates first and second switching pulses Pout and Nout synchronizing with the reference clock, which is not illustrated.
  • the pulse generation circuit 21 repeats a switching period SW when the first and second switching pulses are generated, and a stopping period ST when the first and second switching pulses are not generated, according to the PFM control signal compout, and in the case of the PWM control in the heavy load state, the first and second switching pulses are generated.
  • FIG. 6 illustrates an operation of the switching regulator in FIG. 5 .
  • FIG. 6 just like FIG. 4 , three light load states, from light to heavy, and a heavy load state are depicted.
  • the output current To increases as the load becomes heavier.
  • the pulse generation circuit 21 continuously generates the PWM-controlled first and second switching pulses Pout and Nout.
  • the switching period SW when the first and second switching pulses are generated, and the stopping period ST, where the first and second switching pulses are not generated, are alternately repeated.
  • the PFM comparator COMP 1 compares the divided voltage FB of the output voltage Vo with the reference voltage Vref 3 , and sets the PFM control signal compout to H level if the output voltage Vo rises and exceeds the reference voltage Vref 3 . This is as depicted in time t 1 , t 3 and t 5 and T 1 , T 3 and T 5 . If the output voltage Vo drops and becomes lower than the reference voltage Vref 3 , on the other hand, the comparator COMP 1 sets the PFM control signal compout to L level. This is as depicted in time t 2 , t 4 , t 6 and T 2 , T 4 and T 6 .
  • the stopping period ST begins at time T 1 , T 3 and T 5
  • the switching period SW begins at time T 2 , T 4 and T 6 .
  • the time T 1 to T 6 when the PFM control signal compout changes, is after a certain delay time with respect to the time t 1 to t 6 , when the output voltage Vo crosses the reference voltage Vref 3 . This is because the bias current of the PFM comparator is set to minimum.
  • the first and second transistors do not perform switching operation, hence no electric current is supplied to the smoothing circuit Lo and Co, and the output voltage Vo drops during the stopping period ST due to the load current of the load circuit. Furthermore, the voltage drop of the output voltage Vo is different depending on the level of the load even within the light load state. The dropping level of the output voltage Vo is larger in the light load 3 state where load is heaviest than in the light load 1 state where load is lightest.
  • FIG. 7 is a block diagram of a switching regulator according to the first embodiment. This is an electric current mode type switching regulator, and composing elements the same as FIG. 3 are denoted with a same reference number.
  • a difference from FIG. 3 is that the pulse generation circuit 21 outputs a control signal CTL corresponding to a switching count in the switching period SW in the PFM mode in the light load state, and the response speed of the first comparator COMP 1 is controlled according to this control signal CNT.
  • the control signal CNT is a timing control signal for controlling the switching timing of the PFM comparator COMP 1 to be faster.
  • the response speed is controlled by controlling the bias current value of the first comparator COMP 1 . In other words, the response speed increases by increasing the bias current.
  • FIG. 8 is a block diagram of the pulse generation circuit 21 .
  • an anti-shoot circuit 30 synchronizes with the reference clock OSC_REF, and generates the first and second switching pulses Pout and Nout having a duty ratio corresponding to the PWM signal PWM_out.
  • the anti-shoot circuit 30 generates the first and second switching pulses Pout and Nout, so that the first and second transistors do not turn ON simultaneously.
  • the pulse generation circuit 21 has a counter 32 which determines the switching count SWC in the switching period SW, and count signals A to D of the counter 32 are output as control signals CTL. In the count signals A to D, a number of count signals A to D which become “1” increases as the switching count increases. When the PFM control signal compout rises from the L level to the H level, the count value is loaded in the PFM comparator COMP 1 , and is reset immediately after that.
  • FIG. 9 is a circuit diagram of the PFM comparator COMP 1 .
  • a bias current circuit 35 and a differential transistor circuit 34 of the PFM comparator are depicted.
  • the bias current circuit 35 is comprised of a current mirror circuit 33 and the switches SW 1 to SW 4 , of which ON/OFF is controlled by the count signals A to D of the control signals CTL.
  • FIG. 10 illustrates the operation of the switching regulator of the first embodiment.
  • a count value of the counter 32 , bias current Ibias of the PFM comparator COMP 1 , and first and second switching pulses Pout and Nout are depicted in addition to the output current Io, output voltage Vo, differential voltage Verr, voltage of the connection node LX and PFM control signal compout depicted in FIG. 4 .
  • the PFM mode in the light load mode and the PWM mode in the heavy load mode are depicted, and in the light load mode, a light load 1 where load is lightest, a light load 2 where load is second lightest, and a light load 3 where load is heaviest sequentially transit.
  • the output voltage Vo and the differential voltage Verr have opposite phases.
  • the PFM control signal compout becomes H level if the difference voltage Verr becomes lower than the threshold pfmvth, and the PFM comparator COMP 1 sets the pulse generation circuit to the stopping operation ST state, and if the differential voltage Verr becomes higher than the threshold, on the other hand, the PFM control signal compout becomes L level, and the PFM comparator sets the pulse generation circuit to the switching operation SW state.
  • the duty ratio of the switching pulses Pout and Nout is variably controlled as the electric current Ip increases, so that the drive time by the transistor PMOS increases.
  • the pulse width is constant to simplify the drawing.
  • FIG. 10 depicts, corresponding to the change of the differential voltage Verr at time t 1 to t 6 , the PFM comparator COMP 1 inverts the PFM control signal compout to H level or L level after a certain time delay.
  • the switching regulator in order to suppress an increase in the width of a drop in the output voltage Vo, that is in order to suppress an increase in the ripple voltage, in the stopping operation period ST in the PFM mode in the light load state, the switching regulator performs the following operation.
  • the counter 32 determines the switching count in the switching operation period SW.
  • the switching operation period SW the first and second switching pulses Pout and Nout are generated, and the output voltage Vo rises due to the drive operation of the first transistor PMOS when the first switching pulse Pout is at L level. If the output voltage Vo rises to a certain voltage, the differential voltage Verr becomes lower than the threshold pfmvth (time t 1 , t 3 , t 5 ), and in response to this state, the PFM comparator COMP 1 inverts the PFM control signal compout to H level (time T 1 , T 3 , T 5 ). When the PFM control signal compout becomes H, the PFM comparator enters the stopping operation period ST.
  • the PFM comparator COMP 1 inverts the PFM control signal compout to L level (time T 2 , T 4 , T 6 ).
  • the respective delay time from the time t 2 , t 4 and t 6 to the time T 2 , T 4 and T 6 corresponds to the response speed of the PFM comparator COMP 2 .
  • the bias current Ibias of the PFM comparator is increased to make the response speed of the PFM comparator faster, so as to decrease (shorten) the respective delay time from time t 2 , t 4 and t 6 to the time T 2 , T 4 and T 6 .
  • the delay time from the time t 4 to T 4 and the delay time from time t 6 to T 6 are decreased in this sequence, and in the light load 2 and light load 3 where the load becomes heavier, the end timing of the stopping operation period ST is quickened, and the dropping level of the output voltage Vo in the stopping operation operation ST is decreased. Thereby the ripple voltage of the output voltage Vo can be suppressed.
  • the PFM control signal compout does not change from L level to H level, hence the control signal CTL of the count value of the counter is not loaded and reflected in the bias circuit 35 of the PFM comparator.
  • the bias current of the PFM comparator is increased only when the load becomes heavier, and as a result, the efficiency is improved.
  • FIG. 11 is a block diagram of a switching regulator according to the second embodiment. This is a comparator type switching regulator, and is the same as FIG. 5 . The difference from FIG. 5 is that in the PFM mode in the light load state, the pulse generation circuit 21 outputs a control signal CTL corresponding to the switching count in the switching period SW, and the response speed of the first comparator COMP 1 is controlled according to this control signal CNT. This operation is approximately the same as the first embodiment.
  • FIG. 12 is a block diagram of the pulse generation circuit.
  • the pulse generation circuit 21 has an anti-shoot circuit 30 which generates the first and second switching pulses Pout and Nout based on the PWM signal PWM_out, so as not to turn ON simultaneously, and a counter 32 which determines a switching count in the switching operation period SW in the PFM mode in the light load state.
  • the operation of the counter 32 is the same as the first embodiment.
  • the bias current of the PFM comparator COMP 1 is variably controlled according to the counter value.
  • the configuration of the PFM comparator is the same as FIG. 9 . Since the load is heavier as the switch count in the switching operation period SW is higher, the bias current of the PFM comparator is controlled to be increased as the switch count is higher. Then the response speed of the PFM comparator becomes faster as the load becomes heavier in the light load mode, and as a result, the dropping level of the output voltage Vo can be suppressed by decreasing the stopping period ST.
  • FIG. 13 illustrates the operation of the switching regulator of the second embodiment.
  • the PFM comparator COMP 1 generates the PFM control signal compout based on the comparison of the output voltage Vo and the reference voltage Vref 3 .
  • Control of the PFM control signal compout, the count value counter and the bias current Ibias of the PFM comparator in the other light load states is the same as FIG. 10 .
  • the counter 32 determines the switching count in the switching operation period SW, where the count value is small if the load is light, and the count value is large if the load is heavy. Therefore corresponding to the increase of the count value, the bias current Ibias of the PFM comparator is increased and the response speed of the PFM comparator is increased, so as to decrease the respective delay time from the time t 2 , t 4 and t 6 to the time T 2 , T 4 and T 6 . Since the count value in the time T 2 to T 3 is “2”, the bias current Ibias in the time T 3 to T 4 increases, and since the count value in the time T 4 to 15 is “3”, the bias current Ibias in the time T 5 to T 6 further increases.
  • the delay time from time t 4 to T 4 , and the delay time from time t 6 to T 6 are decreased in this sequence, and in the light load 2 and light load 3 where the load becomes heavier, the end timing of the stopping operation period ST is quickened, and the dropping level of the output voltage Vo in the stopping operation period ST is decreased.
  • the ripple voltage of the output voltage Vo in the case of a heavy load is suppressed.
  • FIG. 13 depicts, the ripple voltage of the output voltage Vo decreases, and as a result, the average voltage of the output voltage Vo in the light load state is approximately the same as the average value of the ideal output voltage Vo in the heavy load state.
  • the load in the PFM mode in the light load state, the load is measured, and as the load becomes heavier, the bias current of the PFM comparator is increased and the response speed thereof is increased, so that the switching timing from the stopping operation ST to the switching operation SW is quickened.
  • the offset voltage of the PFM comparator is increased as the load becomes heavier in the comparator type switching regulator, so that the PFM comparator COMP 1 performs the comparison operation using a level higher than the reference voltage Vref 3 .
  • FIG. 14 is a circuit diagram of a PFM comparator COMP 1 in the comparator type switching regulator according to the third embodiment.
  • the bias current circuit 35 generates a constant bias current Ibias.
  • the differential transistor circuit 34 has: a P-channel transistor P 10 where minus input feedback voltage FB is applied to the gate, a P-channel transistor groups P 11 to P 14 where plus input reference voltage Vref 3 is applied to the gate, N-channel load transistors N 10 and N 11 , a resistor R 12 , and an N-channel transistor N 12 .
  • the differential transistor circuit 34 also has switches SW 11 to SW 14 corresponding to the transistor groups P 11 to P 14 respectively.
  • the total transistor size (gate width) of the transistor groups P 11 to P 14 is the same as that of the transistor P 10 , and the offset voltage of the transistor P 10 and the transistor groups P 11 to P 14 is 0.
  • the switches SW 11 to SW 14 are controlled by the count signals A to D respectively, and the transistor size (gate width) on the plus input side P 11 to P 14 is variably controlled.
  • the control signals A to D are “1”, the switches SW 11 to SW 14 turn OFF.
  • FIG. 15 illustrates operation of the comparator type switching regulator according to the third embodiment.
  • the offset voltage offset of the PFM comparator COMP 1 is higher in the stopping periods ST (T 3 to T 4 , T 5 to T 6 ) after the time T 2 to T 3 and time T 4 to T 5 , where the counter values becomes “2” and “3”. Therefore if the output voltage Vo drops to a level higher than the reference voltage Vref 3 (time t 4 , t 6 ), the PFM comparator COMP 1 starts the switching operation SW, and the PFM control signal compout is switched from H level to L level after the response time elapses.
  • the switching timing from the stopping operation ST to the switching operation SW is quickened, and the dropping level of the output voltage Vo during the stopping period can be suppressed, by controlling the offset voltage.
  • the ripple voltage of the output voltage Vo can be kept low.
  • the average value of the output voltage Vo in the light load state matches with the average value in the heavy load state.
  • the bias current Ibias of the PFM comparator COMP 1 is set to a minimum value according to the minimum operation speed of the PFM comparator, and the offset voltage is variably controlled without increasing the bias current Ibias. Then the current consumption of the PFM comparator in the light load mode can be further suppressed, and efficiency can be increased.
  • the switching regulator according to the fourth embodiment is an electric current mode type, and is a switching regulator to which the PFM comparator COMP 1 of the third embodiment depicted in FIG. 14 is applied.
  • FIG. 16 is a circuit diagram of the electric current mode type PFM comparator COMP 1 according to the fourth embodiment. Unlike FIG. 14 , the output Verr of the error amplifier is input to the minus input side, and the PFM threshold voltage pfmvth is input to the plus input side respectively. It is designed such that when only one switch SW 11 is turned ON, the transistor size (gate width) of the transistor P 11 is the same as that of the transistor P 10 , and the offset voltage of the transistor P 10 and the transistor groups P 11 to P 14 is 0.
  • the switches SW 11 to SW 14 are controlled by the count signals A to D respectively, and just like FIG. 14 , the transistor size (gate width) on the plus input side is variably controlled, and the offset voltage of the comparator is variably controlled.
  • the control signals A to D are “1”, in this case, the switches SW 11 to SW 14 turn ON.
  • the switching timing of the PFM comparator becomes quicker when the load is heavy compared with the case when the load is light.
  • the PFM comparator COMP 1 compares the output Verr of the error amplifier, having the opposite phase of the output voltage Vo, with the threshold voltage pfmvth.
  • the threshold voltage pfmvth In the light load mode, more count signals A to D become “1” as the load becomes heavier, and a number of transistor groups P 11 to P 14 which are connected increases, and the total transistor size (gate width) increases accordingly.
  • the offset voltage changes, and when the differential voltage Verr rises, the transistor P 10 side switches to the “OFF” state at a level lower than the threshold voltage pfmvth, and the PFM control signal compout becomes L level.
  • FIG. 17 illustrates the operation of the switching regulator according to the fourth embodiment.
  • the PFM comparator COMP 1 In the light load 2 and light load 3 where the load becomes heavier, the PFM comparator COMP 1 generates the switching operation at a level lower than the threshold voltage pfmvth when the differential voltage Verr rises (time t 4 , t 6 ). As a result, the switching time T 4 and T 6 from the stopping operation ST to the switching operation PWM is quickened. In this case as well, the average value of the output voltage Vo in the light load state matches with the average value thereof in the heavy load state.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
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CN102457183A (zh) 2012-05-16

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