US8649198B2 - Power conversion device - Google Patents

Power conversion device Download PDF

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Publication number
US8649198B2
US8649198B2 US13/330,735 US201113330735A US8649198B2 US 8649198 B2 US8649198 B2 US 8649198B2 US 201113330735 A US201113330735 A US 201113330735A US 8649198 B2 US8649198 B2 US 8649198B2
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normally
switching element
conversion device
power conversion
diode
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US20120087167A1 (en
Inventor
Atsuhiko Kuzumaki
Hiroshi Mochikawa
Takeru MURAO
Masahiro TAKASAKI
Tadao Ishikawa
Toshiaki KIKUMA
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Central Research Institute of Electric Power Industry
Toshiba Energy Systems and Solutions Corp
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Toshiba Corp
Central Research Institute of Electric Power Industry
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Assigned to CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY, KABUSHIKI KAISHA TOSHIBA reassignment CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIKAWA, TADAO, KIKUMA, TOSHIAKI, TAKASAKI, MASAHIRO, MURAO, TAKERU, KUZUMAKI, ATSUHIKO, MOCHIKAWA, HIROSHI
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/5388—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with asymmetrical configuration of switches

Definitions

  • the present invention relates to a power conversion device in which arms each having series connected normally-on switching element and a normally-off switching element are bridge-connected to each other.
  • JFET junction field effect transistor
  • SIT static induction transistor
  • the power semiconductor switching element may be typified by a normally-on characteristic in which drain current flows therein when the gate voltage is 0 [V].
  • a transistor having a normally-off characteristic such as a bipolar transistor, a metal-oxide semiconductor field-effect transistor (MOSFET), or an insulated gate bipolar transistor (IGBT).
  • a power conversion device is disclosed in Jpn. Pat. Appln. Laid-Open Publication No. 2001-251846, the entire content of which is incorporated herein by reference.
  • the power conversion device constituted by a normally-off composite semiconductor element (hereinafter, referred to merely as “cascode element”) in which a static induction transistor (SIT) and an insulated gate field-effect transistor (IGFET) are cascode-connected to each other is proposed.
  • FIG. 4 is a main circuit diagram of a bridge-connected power conversion device in which some power semiconductors are replaced by other ones.
  • a normally-on semiconductor element is changed from a static induction transistor (SIT) to a junction field effect transistor (JFET) 111 , and an inverter main circuit 3 of the power conversion device includes six three-phase arms connected in a bridge configuration, wherein an arm of each phase is constituted by a cascode element 110 including the junction field effect transistor 111 and a metal-oxide semiconductor field-effect transistor (MOSFET) 112 of a normally-off semiconductor element which are electrically connected in series to each other.
  • SIT static induction transistor
  • JFET junction field effect transistor
  • reference numeral “ 1 ” denotes a DC power supply
  • “ 2 ” denotes a smoothing capacitor
  • “ 113 ” denotes a diode (rectifier diode) parasitic (incorporated) between the source and the drain regions at the manufacturing time of the metal-oxide semiconductor field-effect transistor 112 .
  • the cascode element 110 is put into an OFF state in a gate power at the loss of gate power supply occurring, e.g., at power-on time or at abnormal time, so that it is possible to prevent a short circuit fault of the inverter main circuit 3 .
  • a gate driving circuit (not illustrated) is connected to the gate terminal of the metal-oxide semiconductor field-effect transistor 112 to thereby switch ON/OFF of the cascode element 110 .
  • the diode (rectifier diode) 113 is incorporated between the source and the drain regions of the metal-oxide semiconductor field-effect transistor 112 .
  • current (hereinafter, referred to merely as “return current”) can be made to flow from an output terminal U (common connection terminal shared with a negative arm that is the X-phase arm) to a positive-side DC bus 1 p through a diode 113 u and a junction field effect transistor 111 u.
  • a diode 113 x of a metal-oxide semiconductor field-effect transistor 112 x of the counterpart arm (X-phase arm) is turned non-conductive (OFF).
  • junction field effect transistor 111 constituting the cascode element 110 in the power conversion device but occurs also in the case where the junction field effect transistor 111 is replaced by the static induction transistor (SIT).
  • SIT static induction transistor
  • the present invention has been made to solve the above problem, and an object thereof is to provide a power conversion device capable of reducing the switching loss and the heat generation loss caused by the reverse recovery current.
  • FIG. 1 is a main circuit diagram illustrating a configuration of a power conversion device according to a first embodiment of the present invention
  • FIG. 2 is a main circuit diagram illustrating a configuration of the power conversion device according to a second embodiment of the present invention
  • FIG. 3 is a circuit diagram illustrating a concrete configuration of a gate drive according to a third embodiment of the present invention.
  • FIG. 4 is a main circuit diagram illustrating a power conversion device of a related art.
  • FIG. 1 is a main circuit diagram illustrating a power conversion device according to a first embodiment.
  • a DC power supply 1 is obtained by rectifying three-phase AC power supply.
  • a smoothing capacitor 2 and an inverter main circuit 3 are connected between a positive-side DC bus 1 p and a negative-side DC bus 1 n of the DC power supply 1 .
  • inverter main circuit 3 is a two-level/three-phase output inverter, the number of levels thereof may be three or more, and the output phase thereof may be single-phase or multi-phase.
  • Output terminals U, V, and W which are common connection points shared by the respective phases (U-phase, V-phase, and W-phase) constituting the positive arm of the inverter main circuit 3 and respective phases (X-phase, Y-phase, and Z-phase) constituting the negative arm are connected to an AC load 9 such as an AC electric motor.
  • the output terminals U, V, and W which are common connection points between the respective phases of the positive arm of the inverter main circuit 3 and respective phases of the negative arm are connected to the AC load 9 such as an AC electric motor in FIG. 1 , they may be connected not to the AC load 9 but connected so as to be used in utility grid interconnection.
  • the cascode elements 21 u , 21 v , . . . , 21 z constituting the arms of respective phases are constructed as follows. That is, the normally-on switching elements 4 u , 4 v , 4 w , 4 x , 4 y , and 4 z and the normally-off switching elements 5 u , 5 v , 5 w , 5 x , 5 y , and 5 z are electrically connected in series, and the cascode-connecting diodes 7 u , 7 v , 7 w , 7 x , 7 y , and 7 z are connected (cascode-connected) in a forward direction between the gates of the normally-on switching elements 4 u , 4 v , 4 w , 4 x , 4 y , and 4 z and the sources of the normally-off switching elements 5 u , 5 v , 5 w , 5 x , 5 y , and 5 z .
  • diodes 5 bu , 5 bv , 5 bw , 5 bx , 5 by , and 5 bz are incorporated between the source regions and the drain regions of the normally-off switching elements 5 u , 5 v , 5 w , 5 x , 5 y , and 5 z.
  • High-speed diodes 6 u , 6 v , 6 w , 6 x , 6 y , and 6 z are connected in reverse parallel between the drains of the normally-on switching elements 4 u , 4 v , 4 w , 4 x , 4 y , and 4 z and the sources of the normally-off switching elements 5 u , 5 v , 5 w , 5 x , 5 y , and 5 z.
  • the gates of the normally-on switching elements 4 u , 4 v , . . . , 4 z and gates of the normally-off switching elements 5 u , 5 v , . . . , 5 z are connected to gate driving circuits 8 u , 8 v , 8 w , 8 x , 8 y , and 8 z , respectively.
  • the normally-on switching elements 4 u , 4 v , . . . , 4 z of the cascode elements 21 u , 21 v , . . . , 21 z are each constituted by a junction field effect transistor.
  • the junction field effect transistor one that is turned non-conductive (OFF) when the gate potential applied to a gate electrode is lower than the source potential applied to the source region by, e.g., 25 [V] or more and turns conductive (ON) when the gate potential is higher than the source potential by 25 [V] or more may be used.
  • the normally-on switching element 4 u , 4 v , . . . , 4 z may be constituted by a static induction transistor in place of the junction field effect transistor.
  • Both the junction field effect transistor and the static induction transistor can each achieve high-speed operation in high-voltage/high power region and reduce switching loss in forward and backward directions.
  • the normally-off switching elements 5 u , 5 v , . . . , and 5 z are each of a transistor having a metal-insulator-semiconductor structure. That is, in the first embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and an IGFET (Insulated Gate Field Effect Transistor) may be used as the normally-off switching element 5 .
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • IGFET Insulated Gate Field Effect Transistor
  • the high-speed diodes 6 u , 6 r , . . . , and 6 z are, in e.g., the U-phase, connected in reverse parallel to the cascode element 21 u for the purpose of mainly actively making current flow not in the cascode element 21 u but in the high-speed diode 6 u when the current flows from an output terminal U of the inverter main circuit 3 to the positive-side DC bus 1 p so as to reduce loss.
  • a Fast Recovery Diode can practically be used as the high-speed diode 6 . This is because the FRD is shorter in reverse recovery time and smaller in reverse recovery loss than the built-in diodes 5 bu , 5 bv , . . . , and 5 bz of the normally-off switching element 5 .
  • the normally-on switching element 4 , the normally-off switching element 5 , and the high-speed diode 6 of the cascode element 21 are each constituted by a single semiconductor chip, and a single or a plurality of packages are formed from these semiconductor chips to thereby construct the power conversion device.
  • two or more of the normally-on switching element 4 , the normally-off switching element 5 , and the high-speed diode 6 of the cascode element 21 may be packaged into one package for modularization purposes.
  • a plurality of semiconductor chips each having one or more of the above elements may be formed into one package as a module.
  • the gate driving circuit 8 u of the U-phase cascode element 21 u maintains the normally-off switching element 5 u in an ON state by constantly applying positive voltage of a sufficient magnitude to turn ON the normally-off switching element 5 u between the gate and the source of the element 5 u.
  • cascode elements other than the 21 u i.e., cascode elements 21 v , 21 w , 21 x , 21 y , and 21 z are the same as those of the 21 u , so that the descriptions thereof will be omitted.
  • the return current flows into the positive-side DC bus 1 p through a first current path passing through the normally-off switching element 5 u and the normally-on switching element 4 u of the cascode element 21 u and a second current path passing through the high-speed diode 6 u .
  • the entire return current can be made to flow in the cascode element 21 u.
  • an induction component causes the return current to continue flowing into the positive-side DC bus 1 p from the output terminal U through the U-phase arm.
  • the return current flows through the second current path passing through the high-speed diode 6 u and a third current path passing through a built-in diode (not illustrated) of the normally-off switching element 5 u and the normally-on switching element 4 u .
  • a high-speed diode whose reverse recovery time is shorter than that of the built-in diode (not illustrated) of the normally-on switching element 4 u has been adopted as the high-speed diode 6 u , so that the reverse recovery loss of the high-speed diode 6 u is small.
  • Operation in the arms of other phases than the U-phase is basically the same as that in the U-phase, and operation in the case where the negative arm-side cascode element is turned OFF while the positive arm-side cascode element is turned ON is the same as abovementioned operation, so that descriptions thereof will be omitted.
  • the cascode element 21 assumes an OFF state. This prevents the inverter main circuit 3 from failing clue to DC short circuit.
  • switching loss caused by the reverse recovery current can be reduced to reduce heat generation loss occurring in association with the switching loss, which contributes a size reduction of the cascode element and then to a size reduction of the inverter main circuit. Further, at power-on time or at abnormal time, short-circuit fault can be prevented.
  • the reduction of the heat generation loss due to the switching loss can eliminate the need to provide a cooling heat sink or can reduce the size of the cooling heat sink. As a result, the size of the power conversion device can be reduced.
  • FIG. 2 is a main circuit diagram of the power conversion device according to a second embodiment.
  • the second embodiment significantly differs from the first embodiment illustrated in FIG. 1 in the configuration of the negative arm. Other configurations are the same as those of the first embodiment.
  • the cascode elements 21 u , 21 v , and 21 w each constituting the positive arm are constructed as in the first embodiment. That is, the normally-on switching elements 4 u , 4 v , and 4 w and normally-off switching elements 5 u , 5 v , and 5 w are electrically connected in series, and the cascode-connecting diodes 7 u , 7 v , and 7 w are connected (cascode-connected) in a forward direction between the gates of the normally-on switching elements 4 u , 4 v , and 4 w , and the sources of the normally-off switching elements 5 u , 5 v , and 5 w .
  • the high-speed diodes 6 u , 6 v , 6 w , 6 x , 6 y , and 6 z are connected in reverse parallel between the drains of the normally-on switching elements 4 u , 4 v , 4 w , 4 x , 4 y , and 4 z and the sources of the normally-off switching elements 5 u , 5 v , 5 w , 5 x , 5 y , and 5 z.
  • the gates of the normally-on switching elements 4 u , 4 v , and 4 W and the gates of the normally-off switching elements 5 u , 5 v , and 5 w are connected to the gate driving circuits 8 u , 8 v , and 8 w , respectively.
  • the configuration of the negative arm differs from the first embodiment as follows.
  • the normally-on switching elements 4 x , 4 y , and 4 z of the X, Y, and Z-phase arms and a normally-off switching element 5 y shared by the X, Y, and Z-phase arms are electrically connected in series, and the cascode-connecting diodes 7 x , 7 y , and 7 z are connected (cascode-connected) in the forward direction between the gates of the normally-on switching elements 4 x , 4 y , and 4 z , and the negative-side DC bus 1 n.
  • the high-speed diodes 6 x , 6 y , and 6 z are connected in reverse parallel between the drains of the normally-on switching elements 4 x , 4 y , and 4 z and the negative-side DC bus 1 n.
  • the gates of the normally-on switching elements 4 x , 4 y , and 4 z are connected to the gate driving circuits 8 x , 8 y , and 8 z , respectively, and the gate of the normally-off switching element 5 y is connected to the gate driving circuit 8 y.
  • the sharing of the normally-off switching elements 5 y among the negative arm of the respective phases achieves a shared use of the invalid area (e.g., chip outer periphery) of the semiconductor chip and prevents the three phases from being conductive simultaneously.
  • the area of the semiconductor chips of the normally-off switching elements 5 y is smaller than the total area of the semiconductor chips of the normally-off switching elements 5 x , 5 y , and 5 z in the first embodiment.
  • Output terminals U, V, and W of the inverter main circuit 3 are connected to the load 9 , for example, an AC electric motor.
  • the number of levels of the inverter main circuit 3 may be three or more, and the output phase thereof may be single-phase or multi-phase.
  • normally-off switching element 5 y is provided in the y-phase in the above description, it may be provided in the X-phase or Z-phase and may be provided in any phase in a multi-level inverter.
  • the return current flows into the output terminal U through the first current path passing through the normally-off switching element 5 y and the normally-on switching element 4 x of the cascode element 21 x and the second current path passing through the high-speed diode 6 x.
  • an induction component causes the return current to continue flowing into the output terminal U from the negative-side DC bus 1 n .
  • the return current flows through the second current path passing through the high-speed diode 6 u and the third current path passing through the normally-off switching element 5 y and a built-in diode (not illustrated) of the normally-on switching element 4 x .
  • a high-speed diode whose voltage drop due to current inflow is less than that of the built-in diode of the normally-on switching element 4 x has been adopted as the high-speed diode 6 x , so that the entire return current is made to flow through the second current path, i.e., flow in the high-speed diode 6 x.
  • a high-speed diode whose reverse recovery time is shorter than that of the built-in diode (not illustrated) of the normally-on switching element 4 x has been adopted as the high-speed diode 6 x , so that the reverse recovery loss of the high-speed diode 6 x is small.
  • the same operation as in the first embodiment is performed and, in the negative arm constituting the X, Y, and Z-phases, negative voltage is applied between the gate and the source of each of the normally-on switching elements 4 x , 4 y , and 4 z with the normally-off switching element 5 y shared by the X, Y, and Z-phase arms, putting the normally-on switching elements 4 x , 4 y , and 4 z into an OFF state.
  • the cascode element 21 assumes an OFF state. This prevents the inverter main circuit from failing due to DC short circuit.
  • the following effect can be obtained in addition of the effect obtained in the first embodiment. That is, by the sharing of the normally-off switching element of the negative arm, cost of the cascode element and then the cost of the inverter main circuit can be reduced as compared with the case of the first embodiment.
  • FIG. 3 is a circuit configuration diagram of a third embodiment in which the gate driving circuit of the first and the second embodiments is embodied.
  • FIG. 3 the same reference numerals are given to the same parts as those illustrated in FIGS. 1 and 2 for avoiding an overlapping description.
  • a low-voltage DC power supply 10 is obtained by converting rectified DC power supply 1 using a DC/DC converter.
  • the output of the low-voltage DC power supply 10 is connected to the input of an insulated DC/DC converter for common power supply (DC/DC converter for common power supply in FIG. 3 ) for the purpose of achieving electrical insulation between the arms.
  • the insulated DC/DC converter 28 for common power supply is a power supply common to all the gate driving circuits for driving the normally-on switching element 4 and the normally-off switching element 5 .
  • the output of the insulated DC/DC converter 28 for common power supply is connected between the gate and the source of the normally-off switching element 5 through the input terminal of an insulated DC/DC converter (DC/DC converter for switching element in FIG. 3 ) 11 for normally-off switching element and a gate resistor 12 .
  • the insulated DC/DC converter 11 for normally-off switching element achieves electrical insulation between power sources for the normally-on switching element 4 and the normally-off switching element 5 .
  • the insulated DC/DC converter 11 for normally-off switching element has two channel outputs (e.g., ⁇ 24 [V]), and the outputs are connected in series to obtain 48 [V] power supply.
  • Capacitors 13 and 14 are connected in parallel among output terminals of the insulated DC/DC converter 11 for normally-off switching element for output voltage stabilization.
  • a positive-side DC bus 11 p of 48 [V] power supply is connected to the source of the normally-on switching element 4 , and a negative-side DC bus 11 n thereof is connected to the gate of the normally-on switching element 4 through a series circuit composed of a gate drive n-type MOSFET 25 and a gate resistor 27 .
  • a capacitor 13 is connected in parallel between the positive-side DC bus 11 p and an intermediate DC bus 11 c of the insulated DC/DC converter 11 for normally-off switching element. Further, a capacitor 14 , a signal transmission element 15 , and a logic signal inversion element 16 are connected in parallel between the intermediate DC bus 11 c and the negative-side DC bus 11 n.
  • a resistor 17 a circuit composed of a capacitor 18 and a zener diode 19 connected in parallel, a resistor 22 , a resistor 20 , and a zener diode 23 are connected in series in this order from the positive side between the positive-side DC bus lip and the negative-side DC bus 11 n.
  • a gate drive p-type MOSFET 24 , a gate resistor 26 , a gate resistor 27 , and a gate drive n-type MOSFET 25 are connected in series in this order from the positive side.
  • the gate drive n-type MOSFET 25 and the gate drive p-type MOSFET 24 bear a complementary (a pair of n and p-types having the same characteristics) relationship and are connected such that when one of them is turned ON, the other one is turned OFF. That is, the gate of the gate drive p-type MOSFET 24 is connected to the cathode of the zener diode 19 , and the gate of the gate drive n-type MOSFET 25 is connected to the cathode of the zener diode 23 .
  • the zener diode 19 and the zener diode 23 are selected so as to adjust voltage to be input to the gates of the gate drive p-type MOSFET 24 and the gate drive n-type MOSFET 25 to predetermined values, respectively.
  • the signal transmission element 15 plays a role of transmitting a signal from an inverter control circuit (not illustrated) to the logic signal inversion element 16 while providing electrical insulation between the inverter control circuit and the gate driving circuit 8 .
  • the signal transmission element 15 of FIG. 3 has a characteristic of outputting an ON signal when receiving an ON signal from the inverter control circuit (not illustrated).
  • the logic signal inversion element 16 is connected so as to invert the polarity of an output signal from the signal transmission element 15 and supplies it between the resistors 22 and 20 .
  • ON voltage e.g., 15 [V]
  • ON voltage is constantly applied to the gate of the normally-off switching element 5 to maintain turn-ON state of the normally-off switching element 5 .
  • the normally-off switching element 5 When the insulated DC/DC converter 28 for common power supply is turned ON, the normally-off switching element 5 is maintained in an ON state. At the same time, the gate of the normally-on switching element 4 is driven through the insulated DC/DC converter 11 for normally-on switching element.
  • the gate drive p-type MOSFET 24 When the gate drive p-type MOSFET 24 is tuned ON, the source and the gate of the normally-on switching element 4 assume the same potential, i.e., 0 [V], and the normally-on switching element 4 is tuned ON. At this time, the gate drive p-type MOSFET 24 is tuned ON, the gate drive n-type MOSFET 25 having a complementary relationship with the gate drive p-type MOSFET 24 is in an OFF state.
  • the gate drive n-type MOSFET 25 when the gate drive n-type MOSFET 25 is turned ON, the negative-side bus 11 n of the insulated DC/DC converter 11 for normally-on switching element is connected to the gate of the normally-on switching element 4 , and the positive-side bus lip of, e.g., 48 [V] power supply connected in series to the output of the insulated DC/DC converter 11 for normally-off switching element is connected to the source of the normally-on switching element 4 . That is, 48 [V] negative bias ( ⁇ 48 [V]) is input to the gate of the normally-on switching element 4 , turning OFF the normally-on switching element 4 . At this time, the gate drive p-type MOSFET 24 is in an OFF state.
  • 48 [V] negative bias ⁇ 48 [V]
  • the signal transmission element 15 When the signal from the not illustrated inverter control circuit is ON, the signal transmission element 15 outputs an ON signal (e.g., 24 [V]). The ON signal is then converted into an OFF signal (0 [V]) by the logic signal inversion element 16 . The OFF signal (0 [V]) output from the logic signal inversion element 16 is input to the gate of the gate drive n-type MOSFET 25 , turning OFF the gate drive n-type MOSFET 25 .
  • an ON signal e.g., 24 [V]
  • the ON signal is then converted into an OFF signal (0 [V]) by the logic signal inversion element 16 .
  • the OFF signal (0 [V]) output from the logic signal inversion element 16 is input to the gate of the gate drive n-type MOSFET 25 , turning OFF the gate drive n-type MOSFET 25 .
  • the OFF signal is adjusted by the characteristic of the zener diode 19 to a voltage that turns ON the gate drive p-type MOSFET 24 , and the adjusted voltage is then input to the gate of the gate drive p-type MOSFET 24 having a complementary relationship with the gate drive n-type MOSFET 25 , turning ON the gate drive p-type MOSFET 24 .
  • the source and the gate of the normally-on switching element 4 assume the same potential, i.e., 0 [V], turning ON the normally-on switching element 4 .
  • the signal transmission element 15 When the signal from the inverter control circuit is OFF, the signal transmission element 15 outputs an OFF signal (0 [V]). The OFF signal (0 [V]) is then converted into an ON signal (e.g., 24 [V]) by the logic signal inversion element 16 .
  • the ON signal (24 [V]) output from the logic signal inversion element 16 is adjusted by the characteristic of the zener diode 23 to a voltage that turns ON the gate drive n-type MOSFET 25 , and the adjusted voltage is then input to the gate of the gate drive n-type MOSFET 25 , turning ON the gate drive n-type MOSFET 25 .
  • the ON signal (24 [V]) output from the logic signal inversion element 16 is adjusted by the capacitor 18 to a voltage that turns OFF the gate drive p-type MOSFET 24 , and the adjusted voltage is then input to the gate of the gate drive p-type MOSFET 24 having a complementary relationship with the gate drive n-type MOSFET 25 , turning OFF the gate drive p-type MOSFET 24 .
  • the voltage to be input to the gate drive p-type MOSFET 24 is shifted to negative bias by the capacitor 18 , thus turning OFF the gate drive p-type MOSFET 24 at high-speed.
  • the negative-side bus of 48 [V] power supply is connected to the gate of the normally-on switching element 4
  • the positive-side bus of 48 [V] power supply is connected to the source of the normally-on switching element 4 . That is, 48 [V] negative bias ( ⁇ 48 [V]) is input to the gate of the normally-on switching element 4 , turning OFF the normally-on switching element 4 .
  • the normally-on switching element 4 can be turned OFF even when the return current is flowing, so that the return current can be made to flow into the high-speed diode G. Since a high-speed diode whose reverse recovery time is shorter than that of the built-in diode of the normally-on switching element 4 has been adopted as the high-speed diode 6 , so that the reverse recovery loss of the high-speed diode 6 u is small.
  • the normally-on switching element 4 can be driven (turned ON/OFF) by a signal (ON/OFF signal) of the not illustrated inverter control circuit to be input to the signal transmission element 15 .
  • the output (e.g., 48 [V]) of the insulated DC/DC converter 11 for normally-on switching element is input between the gate and the source of the normally-on switching element 4 at ⁇ 48 [V] (at 48 V between source and gate) in the above description; actually, however, the same voltage is not applied due to voltage drop across the fate drive n-type MISFIT 25 and the gate resistor 27 .
  • the signal transmission element 15 with typical output characteristics has been assumed in FIG. 3 .
  • the logic signal inversion element 16 of FIG. 3 can be omitted.
  • a common source is shared by the normally-off switching elements 5 x , 5 y , and 5 z of the negative arm of X, Y, and Z-phases of the inverter main circuit 3 , so that the insulated DC/DC converter 28 for common power supply in FIG. 3 can be shared in the negative arm and combined into one.
  • the whole number of the insulated DC/DC converters 28 for common power supply is reduced from six (corresponding to six phases) to four.
  • the following effect can be obtained in addition of the effect obtained in the first embodiment. That is, by the sharing of the insulated DC/DC converter for common power supply by the negative arm, cost reduction can be achieved.
  • the fourth embodiment is featured in that the withstand voltage of the normally-off switching element 5 is set to a lower value than that of the normally-on switching element 4 in the first to third embodiments.
  • the withstand voltage of the normally-off switching element 5 may be set to a value corresponding to voltage to be input to the gate so as to turn OFF the normally-on switching element 4 .
  • withstand voltage of a semiconductor element when the withstand voltage of a semiconductor element is reduced, on-resistance thereof can be reduced.
  • the withstand voltage of the normally-off switching element 5 By setting the withstand voltage of the normally-off switching element 5 to a lower value than that of the normally-on switching element 4 , on-resistance of the normally-off switching element 5 can be reduced to reduce conduction loss. Further, when semiconductor elements are compared under the condition of the same current rating, one having a lower withstand voltage is of greater advantage for cost reduction.
  • the following effect can be obtained in addition of the effect obtained in the first embodiment. That is, by lowering the withstand voltage of the normally-off switching element, cost of the semiconductor element and then the cost of the inverter main circuit can be reduced.
  • the fifth embodiment is featured in that the withstand voltage of the cascode-connecting diode 7 is set equal to that of the normally-off switching element 5 in the first to fourth embodiments.
  • the withstand voltage of the cascode-connecting diode 7 may be set to a value corresponding to voltage to be input to the gate so as to turn OFF the normally-on switching element 4 , that is, may be equal to the withstand voltage of the normally-off switching element 5 .
  • withstand voltage of a semiconductor element when the withstand voltage of a semiconductor element is reduced, on-resistance thereof can be reduced.
  • the withstand voltage of the cascode-connecting diode 7 By setting the withstand voltage of the cascode-connecting diode 7 equal to that of the normally-off switching element 5 , cost of the semiconductor element can be reduced.
  • the following effect can be obtained in addition of the effects obtained in the first to third embodiments. That is, by setting the withstand voltage of the cascode-connecting diode equal to that of the normally-off switching element, cost of the semiconductor element and then the cost of the inverter main circuit can be reduced.
  • the sixth embodiment is featured in that the high-speed diode 6 is a unipolar diode in the power conversion device according to the first to fifth embodiments.
  • the seventh embodiment is featured in that the high-speed diode 6 which is a unipolar diode formed as a Schottky Barrier Diode (SBD), a Junction Barrier Controlled Schottky Diode, or a Merged PiN Schottky Diode.
  • SBD Schottky Barrier Diode
  • Junction Barrier Controlled Schottky Diode or a Merged PiN Schottky Diode.
  • the SBD Schottky Barrier Diode
  • the SBD is shorter in reverse recovery time and thus smaller in reverse recovery loss than those of the built-in diode of the normally-on switching element 4 .
  • the Junction Barrier Controlled Schottky Diode (JBS) or a Merged PiN Schottky Diode (MPS) each in which Schottky junction and a PiN junction coexist can be used for the unipolar diode.
  • the eighth embodiment is featured in that the normally-on switching element 4 is constituted by a wide-gap semiconductor such as SiC (silicon carbide), GaN (gallium nitride), or diamond in the power conversion device according to any of the first to seventh embodiments.
  • a wide-gap semiconductor such as SiC (silicon carbide), GaN (gallium nitride), or diamond in the power conversion device according to any of the first to seventh embodiments.
  • the normally-on switching element 4 constituted by the wide-gap semiconductor can increase breakdown electric field strength by about one digit and can reduce the thickness of a drift layer for keeping the withstand voltage to about one-tenth, thereby reducing the conduction loss of the normally-on switching element 4 .
  • the normally-on switching element 4 constituted by the wide-gap semiconductor can increase a saturated electron drift speed about twice, thus allowing for implementation of a high frequency about ten times increased. This allows turn-on and turn-off losses of the normally-on switching element 4 to be reduced.
  • the use of the normally-on switching element 4 constituted by the wide-gap semiconductor allows the conduction loss and switching loss of the normally-on switching element 4 to be reduced, thereby providing the inverter main circuit with lower loss and smaller size.
  • the ninth embodiment is featured in that the high-speed diode 6 is constituted by a wide-gap semiconductor such as SiC (silicon carbide), GaN (gallium nitride), or diamond in the power conversion device according to any of the first to eighth embodiments.
  • a wide-gap semiconductor such as SiC (silicon carbide), GaN (gallium nitride), or diamond in the power conversion device according to any of the first to eighth embodiments.
  • the high-speed diode 6 constituted by the wide-gap semiconductor can increase breakdown electric field strength by about one digit, thereby achieving high withstand voltage of the high-speed diode 6 .
  • the high-speed diode 6 constituted by the silicon semiconductor can be used only in a bipolar configuration, while the high-speed diode 6 constituted by the wide-gap semiconductor can be used even in a unipolar configuration.
  • the reverse recovery loss is reduced to reduce the loss of the high-speed diode 6 as in the sixth embodiment.
  • the loss of the cascode element 21 can be reduced as in the sixth embodiment.
  • a high-withstand voltage unipolar diode is constituted by silicon, the conduction loss is so large that the diode cannot practically be used.
  • silicon unipolar diodes e.g., Schottky Barrier Diode
  • the withstand voltage of a product called “high withstand voltage” diode is about 200 [V] at most.
  • a high-speed diode 6 having a high withstand voltage of e.g., 1200 [V] can be realized.
  • the loss of the cascode element 21 can be reduced, thereby allowing a small-sized power conversion device to be provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)
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JP2009152504A JP5461899B2 (ja) 2009-06-26 2009-06-26 電力変換装置
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EP2448102A1 (fr) 2012-05-02
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EP2448102A4 (fr) 2017-11-29
CN102449898A (zh) 2012-05-09

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