US8509859B2 - Apparatus and methods for control of sleep modes in a transceiver - Google Patents

Apparatus and methods for control of sleep modes in a transceiver Download PDF

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US8509859B2
US8509859B2 US11/372,876 US37287606A US8509859B2 US 8509859 B2 US8509859 B2 US 8509859B2 US 37287606 A US37287606 A US 37287606A US 8509859 B2 US8509859 B2 US 8509859B2
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sleep
receiver
components
transceiver
processor
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US20060240798A1 (en
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Tadeusz Jarosinski
Chinnappa K. Ganapathy
Michael Mao Wang
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/1607—Supply circuits
    • H04B1/1615—Switching on; Switching off, e.g. remotely
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • H04W52/0229—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal where the received signal is a wanted signal
    • H04W52/0232—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal where the received signal is a wanted signal according to average transmission signal activity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/0293—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present disclosure relates to apparatus and methods for control of sleep modes in a transceiver and, more particularly, for automated control of different sleep modes using a hardware implemented sleep mode controller.
  • the cost effective crystal oscillator as the sleep controller clocking device is at the expense of some accuracy in time keeping because the clock frequency tends to drift with temperature.
  • This clock is otherwise known as the “sleep clock” or “slow clock.”
  • the system clock or “fast clock” (and VCTCXO) is off.
  • the sleep clock is used as a timer to wake up the system. Upon wake up, once the fast clock becomes stable after waking up, system timing is once again handed over to the fast clock.
  • a wireless transceiver including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver; and a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down and waking up of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.
  • a method for controlling sleep modes in a wireless transceiver includes determining timing information concerning sleep periods for at least a portion of components within the transceiver with a processor; and receiving information concerning sleep periods from the processor with a sleep control logic coupled to the processor; and shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of and synchronously with the system time.
  • the transceiver apparatus includes means for determining timing information concerning sleep periods for at least a portion of components within the transceiver; means for outputting information concerning sleep periods from the means for determining; and means for executing sleep periods configured to shut down the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with the means for determining timing information.
  • a computer-readable medium encoded with a set of instructions includes an instruction for determining timing information concerning sleep periods for at least a portion of components within the transceiver with a processor; an instruction for receiving information concerning sleep periods from the processor with a sleep control logic coupled to the processor; and an instruction for shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with a transceiver system timing.
  • FIG. 1 is an exemplary block diagram of wireless device including an implemented sleep controller.
  • FIG. 2 is an exemplary block diagram illustrating a more detailed architecture of the transceiver of FIG. 1 including a hardware implemented sleep controller.
  • FIG. 3 is a block diagram of an exemplary baseband receiver chipset including sleep control logic.
  • FIG. 4 is an exemplary timing diagram showing the timing operation of the sleep control logic.
  • FIG. 5 is an exemplary timing diagram showing a “snooze” operation.
  • FIG. 6 is a flow diagram of an exemplary method for sleep mode control.
  • FIG. 7 is a block diagram of a further exemplary transceiver.
  • FIG. 1 illustrates a wireless device 100 , such as a mobile transceiver for receiving and transmitting wireless communication signals, such as CDMA and OFDM signals.
  • the transceiver 100 includes a transceiver chipset 102 used for processing communications signals received or to be transmitted.
  • the chipset 102 includes a microprocessor 104 , which may be a single processor or multiple processors such as a general purpose processor (GPP) and a digital signal processor (DSP). It also includes the baseband transceiver 106 and the RF integrated circuits 108 , which are used to actually receive and transmit the wireless communication signals via antenna(s) 110 .
  • GPS general purpose processor
  • DSP digital signal processor
  • the microprocessor 104 is configured to execute software that determines timing of sleep modes for the transceiver device 100 . That is, the software run by the microprocessor 104 determines when particular components of the transceiver device 100 may be powered down to conserve life of the device battery (not shown).
  • the transceiver 100 also includes another chipset used to receive communication signals, such as burst communications in an orthogonal frequency division multiplexed (OFDM) system, for example.
  • This chipset is shown as a receiver chipset 112 in the example of FIG. 1 .
  • the chipset 112 is another baseband circuit including a baseband receiver 114 , which processes received communication signals.
  • the baseband receiver 114 receives communication signals from a RF chip 116 and an analog-to-digital converter (ADC) 118 (e.g., a sigma-delta modulator ADC).
  • ADC analog-to-digital converter
  • the chipset 112 includes sleep control logic 120 that is used to execute sleep modes within the receiver chipset 112 .
  • Logic 120 may be implemented with digital logic or any other suitable hardware that characteristically execute instructions quickly with low latency.
  • the chipset is coupled to the microprocessor 104 via bus 122 , such as external parallel or serial bus and GPIO (general purpose input/output), in order to communicate sleep mode timing information to the hardware sleep control logic 120 .
  • Logic 120 in turn, then actually executes the sleep mode timing, as will be discussed in more detail below.
  • the transceiver 100 includes a fast and accurate system clock 124 , originating from a stable source, such as a voltage controlled temperature compensated crystal oscillator (VCTCXO) used for providing system timing when the transceiver 100 is in awake modes.
  • a sleep clock source 126 which consumes less power and is slower than the fast clock 124 , is used for system timing during sleep modes to conserve battery energy.
  • Each of the chipsets 102 and 112 receive clock signals from clocks 124 and 126 as illustrated by connections 128 and 130 , respectively.
  • FIG. 2 illustrates an exemplary detailed block diagram of portions of the transceiver 100 utilizing chipset-based phone architecture.
  • the transceiver 100 includes the transceiver chipset 102 , such as a CDMA transceiver chipset, which includes microprocessor 104 .
  • the transceiver 100 also includes receiver chipset 112 that is used to receive broadcast wireless signals, including those utilizing burst communication (i.e., bursts of packets of information). Examples of such standards include orthogonal frequency division multiplexing (OFDM) standards.
  • OFDM orthogonal frequency division multiplexing
  • the baseband receiver 114 utilizes sleep control logic 120 , which executes sleep modes determined by the microprocessor 104 .
  • the microprocessor 104 determines the sleep functionality for sleep modes to be effected. This determination is made with software run by the processor 104 .
  • This sleep software (“Sleep SW”) is indicated diagrammatically by cloud 200 .
  • the software interacts with the sleep control logic 120 via the bus 122 to program logic 120 with information concerning what timing is to be executed by logic 120 when going to sleep or waking up from sleep.
  • the transceiver chipset 102 includes the baseband transceiver 106 , which includes respective sleep controllers for supporting other modes such as CDMA 1 ⁇ , High Data Rate (HDR), UMTS, Global System for Mobile Communications (GSM), Global Positioning System (GPS), and other modes.
  • the sleep software also controls or sets the operation of the sleep controllers in the baseband transceiver 106 , where communication is effected by a bus 208 between the baseband transceiver 106 and the processor 104 .
  • the processor 104 also runs software (VCTCXO Controller SW 202 ) to control a Pulse Density Modulator (PDM) of the VCTCXO clock 124 in concurrent support of different modes as illustrated by communication bus 214 .
  • Connections between the VCTCXO Controller SW 202 and the Sleep SW 200 illustrate that an exchange information occurs therebetween concerning when the VCTCXO can be turned off and on, as illustrated in FIG. 2 .
  • the sleep functionality of the present disclosed system interacts or affects various devices in the transceiver 100 .
  • various components within the transceiver chipset 102 are controlled to enter sleep modes.
  • the baseband transceiver 106 may include sleep control.
  • the processor 104 may actually be put to sleep as well.
  • the sleep clock or crystal oscillator 126 is run continuously to provide a low power, uninterrupted clock source for the transceiver 100 during sleep modes.
  • the system clock 124 also is affected by the sleep functionality.
  • the sleep software 200 running on microprocessor 104 will issue controls via a bus 216 to a power management chip 204 , which, in turn, controls the delivery of power to the VCTCXO 124 (thereby turning the system clock 128 on and off).
  • the high power consumption clock 124 is turned off during sleep modes to converse energy.
  • the RF ICs 108 which support the baseband transceiver 106 and accompanying modes, are also affected by sleep functionality.
  • the microprocessor 104 may issue instructions to RF IC 108 via a bus 218 , such as a serial bus interface.
  • the baseband receiver 114 may issue control signals to the RF IC or chip 116 via a serial bus 220 .
  • FIG. 2 also illustrates that the transceiver 100 may include a user interface (UI) 210 , such as a keypad, microphone, or other interfacing apparatus which input to the microprocessor.
  • UI user interface
  • the transceiver 100 may also connect to various peripherals 212 , such as via a Universal Serial Bus (USB) or other serial or parallel connection.
  • USB Universal Serial Bus
  • the sleep functionality is responsive to these input or communication connections since they present “rude” interrupts that may require sleep modes to be aborted or rescheduled.
  • each of the sleep controllers i.e., the baseband transceiver sleep controllers and sleep control logic 120
  • receive input from the sleep clock 126 receives both the system clock and sleep clock signals directly.
  • the sleep controllers are configured to switch their timing to the low-power sleep clock 126 during sleep modes to conserve power.
  • the microprocessor 104 (with system clock turned on) can continue to display data on a display (not shown) of the transceiver 100 during streaming of packets received via the baseband receiver 112 , such as streaming video via an OFDM system. Nonetheless, the receiver chipset 112 can still conserve power during “off” time by switching its system clocks and PLL off (e.g., disabling clocks in order to inactivate sub-blocks in the chipset 112 ) and switching the sleep control logic's ( 120 ) clock source to the sleep clock 126 . In instances that do not involve direct display to the display, the microprocessor 104 may have time to go to sleep too.
  • sleep modes can be activated during various states of the receiver chipset 112 .
  • the first of these states is an active state where data received via the RF chip 116 and ADC 118 is being demodulated burst by burst (e.g., a group of adjacent active symbols is forming a burst, in the case of an OFDM system).
  • bursts of information in the active state for example, sleep modes may be effected such as when received overhead information is being demodulated (e.g. OFDM overhead information symbols) or when receiving traffic or control channel data.
  • Another state when sleep modes may be effected include deep sleep states, which are dormant states where no pending requests are being received and only periodic wakeups are necessary, such as for example updating information concerning what information will be broadcast (e.g., a program guide).
  • a function of the sleep control logic 120 is to minimize power consumption during sleep when the receiver chipset 112 is not receiving active bursts of information. Due to the nature of burst communication that the receiver chipset 112 is designed to receive, the operation of the chipset 112 tends to be systolic (i.e., occurring in bursts of processing corresponding to received bursts of information with idle processing times in between bursts). In certain systems, such as OFDM systems, bursts can last about 10 ms (4% duty cycle) or longer, depending on the payload configuration.
  • the presently disclosed example includes independent sleep timelines for processor 104 , which may include separate sleep timelines for multiple processors in the transceiver 102 , and the baseband receiver chipset 112 , although they share the same system clock derived from the VCTCXO clock 124 . Furthermore, in order to prevent problems due to latencies inherent to software run by the microprocessor 104 and that the receiver chipset 112 could not tolerate such latency, it was recognized that sleep control for the receiver 112 would be more efficient using separate hardware logic (e.g., 120 ) to execute sleep modes in the receiver 112 .
  • separate hardware logic e.g., 120
  • the sleep control logic 120 executes a separate sleep timing operation for chipset 112 , logic 120 nonetheless is configured to interface with various other portions of the transceiver 100 . This is because the timing operation of the receiver affects and is affected by other operations of other parts of the transceiver 100 .
  • FIG. 3 A more detailed block diagram of an exemplary implementation of the sleep control logic 120 and its interactions is illustrated in FIG. 3 .
  • the sleep control logic 120 includes sleep core logic 300 having sleep timers 302 and system time buffer 304 .
  • the sleep timers 302 are programmed by the processor 104 via a bus interface 306 which interfaces with bus 308 between the processor 104 and the receiver chipset 112 .
  • the bus 308 is coupled to another interface 310 in the sleep control logic 120 .
  • a sleep register 312 is used to then direct programming information to sleep timers 302 , such as timing information and predefined that the logic 120 will automatically execute when effecting the sleep timeline.
  • the baseband receiver 112 also includes a phase lock loop (PLL) 314 , which generates the system clock and other clock domains or regimes. These clock signals are fed to a clock gating logic 316 , which is used to selectively turn on and off the different clock domains based on clock disable signals received from core logic 300 . From the Sleep Control Logic standpoint in the disclosed example of FIG. 3 , multiple clock regimes are controlled through the clock gating logic 316 . The first of these is a primary system clock regime. The next is a secondary clock regime, which is used during the draining process of the decoder output buffer (not shown on the diagram), when the burst demodulation has ended. Additional domains include a Sleep Core Logic fast clock regime (sleep_fast_clk), a sleep controller core sleep clock regime (not shown), and a RF serial interface block clock regime (used with serial bus interface 318 , not shown).
  • PLL phase lock loop
  • microprocessor 104 can disable or enable each clock via a halt input, overriding the sleep controller hardware.
  • the core logic 300 is configured to issue a wakeup interrupt signal (wakeup_int) to the interrupt controller in the transceiver chipset 102 . It is noted that this interrupt is dynamically determined based on programming information from the microprocessor 104 since the wakeup point is not the same for every sleep mode operation and changes from burst to burst.
  • wakeup_int a wakeup interrupt signal
  • sleep control logic 120 disables the primary and secondary system clocks via clock disable signals to conserve energy during a sleep mode.
  • the sleep core logic 300 also disables one or more Phase Lock Loops (PLLs) 314 , which are used to generate system clock regimes.
  • PLLs Phase Lock Loops
  • the control logic receives a system time synchronization pulse, sys_time_en, and exact timing information (sys_time_in) from Receiver Core Logic 114 before sleep begins, and updates (or triggers the update) the system time before sleep finishes.
  • the microprocessor 104 and sleep control logic 120 operation are synchronized via interrupts multiplexed to a single transceiver GPIO signal 322 by interrupt controller 320 , and wakeup_int.
  • the microprocessor 104 (not shown in FIG. 3 ) communicates with the control logic 120 over the interface 306 , 308 , and 310 .
  • the control logic further interfaces to the RF and ADC chips 116 , 118 , through a serial bus interface 318 and a couple of discrete lines for issuing direct signals such as turning on the TXCO buffer in the RF chip 116 .
  • software or instructions run by the microprocessor 104 are used to configure the sleep timeline. It is noted that the software can also “tag” bursts after which a snooze cycle or partial sleep cycle can automatically start. It is further noted that the sleep control logic hardware 120 executes the sleep and/or snooze timeline with the resolution of the system clock (sys_clk), which is greater than sleep clock frequency to preserve maximum accuracy.
  • system clock sys_clk
  • FIG. 4 is an exemplary timing diagram showing the timing operation of the sleep control logic 120 .
  • the baseband receiver 114 is configured to tightly control the sleep time (i.e., the period between the assertion of the next sample-aligned trigger signal (sys_time_en), and pulsing of the on_line_int signal when system time counter is restored after wakeup.
  • Sleep time i.e., the period between the assertion of the next sample-aligned trigger signal (sys_time_en)
  • pulsing of the on_line_int signal when system time counter is restored after wakeup.
  • System time is known when sys_time_en is pulsed and an estimate is made for the system time when on_line_int is pulsed.
  • the VCTCXO 124 is shut down during sleep mode and, thus, the sleep_fast_clock which uses clock 124 as the source for timing, is also shut down.
  • the sleep clock 126 is used for timing during the sleep mode (e.g., for determining how long to stay in sleep mode and when to issue the wakeup interrupt signal).
  • the sleep clock is used for timing until the PLLs settle after wakeup as shown in FIG. 4 .
  • the PLL settled i.e., sleep_fast_clk is restored
  • timing for receiver 112 reverts to the system clock domain.
  • the presently disclosed sleep control logic 120 includes a “snooze” feature to provide for immediate RF chips 116 shutdown after the end of a received burst.
  • the “snooze” allows shutdown of a portion of components, while leaving a minimum clock domain (secondary system clock) active, in order to allow the microprocessor 104 to finish processing the current task and drain the decoder output buffer. After processing is finished, the secondary system clock regime and the PLL can also be shut down.
  • the majority of power consumption is due to resources that are shut down at snooze time, particularly the RF chip 116 . Thus, a significant degree of efficiency can be garnered through partial shutdown of components in the “snooze”.
  • the “snooze” feature allows software to tag received bursts after which snooze/sleep cycle can occur, and let the sleep control logic 120 initiate RF and part of the digital circuitry shutdown automatically at the end of those bursts, when the snooze trigger (snooze_trig) is generated by hardware (see FIG. 3 and reference 402 as the start of a “snooze” cycle after a snooze tagged burst).
  • the burst snooze tags in the FFT descriptors are used to detect the last tagged burst sample.
  • the snooze trigger is generated by Receiver Core Logic 114 and sent to the sleep control logic 120 , as shown in FIG. 3 .
  • the RF chip 116 , ADC 118 , the front end blocks and the FFT are ready to be shut down. It is noted also that most of the time, interrupts to the microprocessor that indicate commencement of the snooze cycle will have already occurred by the time the software is ready to issue a go_to_sleep request.
  • the sleep control logic 120 can effect a full sleep mode immediately after microprocessor 104 issues the go_to_sleep request.
  • sleep control logic 120 executes the sleep timeline based on the secondary system clock during snooze. The reason for this is twofold. First, the secondary system clock domain is still needed by the decoder output buffer, interrupt controller, and other blocks. Second, the process of computing sleep parameters and sleep clock frequency estimation is too complex to be done by hardware. For those reasons, the complete shutdown of the system clock and the PLL and switch to the sleep clock is not possible.
  • FIG. 5 illustrates a timeline for an exemplary snooze operation, which was discussed above.
  • an over the air signal comprising a snooze tagged burst 502 (tagged by software run on processor 104 ) is received by the transceiver 100 .
  • front end processing 504 is performed, such as FFT processing in the case of an OFDM system, as an example.
  • the receiver core logic 114 which may be hardware, issues a snooze trigger signal (snooze trig) 506 to the sleep control logic 120 (see FIG. 3 also).
  • Logic 120 then initiates a snooze cycle 508 where part of the components in chipset 112 may be shut down, such as the RF chip 116 , and ADC 118 , as examples. Since other processing 510 , such as decoding, is still being performed, not all components may be put to sleep.
  • a go_to_signal 514 may be processed. After signal 514 has issued, synchronization occurs between hardware and software and software proceeds to issue a sleep execution 518 . If request 518 occurs before wakeup signal 520 , then sleep is accepted by hardware and starts immediately. Otherwise it is rejected and snooze 508 continues to start of next pulse and the remaining components are put to sleep for a full sleep cycle 516 . If the latency 512 is longer than processing 510 (this is not shown on timeline), then the sleep control logic will not initiate a full sleep.
  • FIG. 6 illustrates an exemplary flow diagram of a process 600 for effecting sleep mode control.
  • the process 600 begins at start block 602 .
  • Flow proceeds to block 604 where the microprocessor 104 determines timing information concerning sleep periods for at least a portion of components within the transceiver 100 . That is, microprocessor determines through the sleep software 200 configures the timeline for sleep modes and also may determine which components are allowed to be powered down, such as during “snooze” modes which effect only partial shutdowns.
  • the sleep control logic 120 automatically shuts down at least a potion of the components of the transceiver 100 during sleep modes, either full sleep mode or snooze modes.
  • the operation in block 608 also includes bringing back or using sleep control logic 120 independent of, but synchronous with receiver or transceiver 106 or 114 . That is, the sleep control logic 120 is configured to effect or execute the sleep timeline from entering sleep modes to bringing powered down components back out of sleep mode to powered up operation. This operation is automatically executed by the logic 120 independent of the microprocessor 104 in the sense that the microprocessor does not trigger the sleep modes for the receiver chipset 112 . Notwithstanding, the sleep mode operation is performed synchronous with the system timing (e.g., TCXO system clock) used by the receiver or transceiver 106 or 114 .
  • system timing e.g., TCXO system clock
  • block 608 is repeated for each awake/sleep mode cycle, which continue while the transceiver is operational.
  • the process in blocks 604 and 606 may be performed during initialization of the transceiver 100 , but can also be performed anytime after initialization as well if desired.
  • FIG. 7 is block diagram of a further exemplary transceiver 700 according to the present disclosure.
  • the transceiver 700 includes means for determining timing information concerning sleep periods for at least a portion of components within the transceiver 702 .
  • This means may be, for example, processor 104 discussed previously.
  • Coupled to means 702 is means for outputting information concerning sleep periods from the means for determining 704 .
  • Means 704 may be implemented by bus interface 306 , bus 308 , bus interface 310 , and sleep register 312 , for example.
  • Coupled to means 704 is a means for executing sleep periods 706 , which is configured to shut down the at least a portion of the components of the transceiver during power reduction periods independent of and synchronous with the means for determining timing information.
  • Means 706 may be implemented, for example, by sleep control logic 120 .
  • the baseband receiver 114 and the sleep control logic 120 may reside in a separate ASIC or similar processing circuit as illustrated, but may also be part of an ASIC or chipset incorporated with the transceiver chipset 102 . It is further noted that the above-described apparatus and methods may also be utilized for sleep control performed by the baseband transceiver 106 .

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Transceivers (AREA)
  • Telephone Function (AREA)
  • Circuits Of Receivers In General (AREA)
  • Power Sources (AREA)
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US20100015916A1 (en) * 2008-07-16 2010-01-21 Qualcomm Incorporated Network server having an information and scheduling controller to support one or more low duty cycle wireless devices
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