US8072019B2 - Flash memory and manufacturing method of the same - Google Patents

Flash memory and manufacturing method of the same Download PDF

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Publication number
US8072019B2
US8072019B2 US12/200,423 US20042308A US8072019B2 US 8072019 B2 US8072019 B2 US 8072019B2 US 20042308 A US20042308 A US 20042308A US 8072019 B2 US8072019 B2 US 8072019B2
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region
ion implantation
trench isolation
shallow trench
active region
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US20090065840A1 (en
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Sung-Kun Park
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DB HiTek Co Ltd
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Dongbu HitekCo Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

Definitions

  • nonvolatile memory devices such as a floating gate memory device or a metal insulator semiconductor (MIS) memory device constructed having two or more multilayered dielectric layers.
  • the floating gate memory device embodies memory characteristics using a potential well and may be constructed in an electrically erasable programmable read only memory (EEPROM) tunnel oxide (ETOX) structure.
  • EEPROM electrically erasable programmable read only memory
  • ETOX tunnel oxide
  • the ETOX structure is a simple stack structure which is presently being the most widely applicable as an EEPROM, or a split gate structure having two transistors for each cell.
  • MIS type memory device performs a memory function using a trap existing at a dielectric layer bulk, a dielectric layer/dielectric layer interface, and a dielectric layer/semiconductor interface.
  • a metal/silicon oxide nitride oxide semiconductor (MONOS/SONOS) structure which is being presently applicable as a flash EEPROM, is a representative example.
  • a flash memory device has a source connection layer that interconnects sources of respective unit cells to form a source line.
  • a source line which is a dopant diffusion layer obtained through a self-aligned source (SAS) process to achieve high integration of the flash memory device, has been greatly applied as the source connection layer of the flash memory device.
  • SAS self-aligned source
  • a method of forming a source line includes a step of forming shallow trench isolation 120 in substrate 110 to define active region 130 .
  • a stack gate is then formed on and/or over active region 130 and shallow trench isolation 120 is filled in the field region with, e.g., an oxide film, and is then etched by reactive ion etching (RIE) using a photoresist mask to form trench T.
  • RIE reactive ion etching
  • ions are implanted in substrate 110 where trench T is formed by double ion implantations, i.e., a vertical ion implantation (I v ) and a tilt ion implantation (I t ), to form common source 140 having laterally extending surface portions 141 and 143 and vertical surface portion 142 connected to each other as illustrated in example FIG. 4 .
  • double ion implantations i.e., a vertical ion implantation (I v ) and a tilt ion implantation (I t )
  • CDE chemical dry etching
  • RIE oxide film etching
  • high etching selectivity between the oxide film and the substrate is required, and therefore, high-priced equipment is required, and an additional process is also required.
  • a margin is reduced at a subsequent photo process due to high step difference between the substrate and the etched shallow trench isolation.
  • a read failure may also occur when a photoresist (PR) residue is generated at a valley portion of the portion where the shallow trench isolation is etched.
  • PR photoresist
  • the active damage may be caused, at the time of performing the oxide etching, as follows. While the source line is being etched, damage is caused at the active region adjacent thereto due to stress. As a result, the W/L stress is caused, and therefore, a stress failure may occur. Also, a CDE process and a SW annealing step are additionally required due to the damage to a control gate and a floating gate at the time of etching the shallow trench isolation. When curing is not appropriately performed, a retention failure may occur. For example, side poly damage is caused only at the source region at the time of performing the oxide etching at the recessed common source (PCS), with the result that an oxide film grows thinner than a drain region when forming oxide by a subsequent SW oxidation.
  • PCS recessed common source
  • Embodiments relate to a flash memory and a manufacturing method of the same that do not perform a field oxide etching step at the time of performing a recessed common source (RCS) process and secure characteristics of a common source less than the same sheet resistance (R s ), thereby simplifying the process and preventing the occurrence of problems which may occur while performing the process.
  • RCS recessed common source
  • Embodiments relate to a flash memory that may include at least one of the following: a shallow trench isolation and an active region formed in a substrate; a plurality of stack gates formed on and/or over the active region; a deep implant region formed at a lower side of the shallow trench isolation and the active region between the stack gates; and a shallow implant region formed at a surface of the active region between the stack gates.
  • Embodiments relate to a manufacturing method of a flash memory that may include at least one of the following steps: forming a shallow trench isolation to define an active region in a substrate; and then forming a plurality of stack gates on the active region; and then forming a deep implant region at a lower side of the shallow trench isolation and the active region between the stack gates; and then forming a shallow implant region in a surface of the active region between the stack gates.
  • Embodiments relate to a method that may include at least one of the following steps: forming a trench isolation in a substrate defining an active region at a first depth; and then sequentially performing a first ion implantation process to form a first ion implantation region in the active region at a second depth, a second ion implantation process to form a second ion implantation region in the active region at a third depth and a third ion implantation process to form a third ion implantation region in the active region and the trench isolation at a fourth depth; and then forming a shallow implant region at the active region at a fifth depth.
  • Example FIGS. 1 to 4 illustrates of a flash memory.
  • FIGS. 5 to 9 illustrate a flash memory device and a manufacturing method of a flash memory in accordance with embodiments.
  • Example FIG. 10 illustrates a flash memory
  • each layer includes forming something directly to each layer or indirectly to each layer via another layer.
  • a flash memory in accordance with embodiments includes shallow trench isolation 220 and active region 230 formed in substrate 210 .
  • a plurality of stacked gates 260 are formed on and/or over active region 230 and deep implant region 240 a is formed extending between the middle and the lower region of shallow trench isolation 220 and active region 230 between the respective stacked gates 260 .
  • Shallow implant region 240 b is formed at the upper region of active region 230 between the respective stacked gates 260 .
  • deep implant region 240 a and shallow implant region 240 b are electrically connected to each other to form common source 240 .
  • Each stacked gate 260 has a height greater than the depth of shallow trench isolation 220 .
  • FIG. 9 is a sectional view of a flash memory according to an embodiment of the present invention taken along line I-I′ of FIG. 5 .
  • Deep implant region 240 a includes first ion implantation region 242 formed at active region 230 between stacked gates 260 , and second ion implantation region 244 formed at active region 230 between stacked gates 260 and third ion implantation region 246 formed at the lower region of shallow trench isolation 220 and active region 230 between stacked gates 260 .
  • First ion implantation region 242 is formed at a depth less than that of shallow trench isolation 220 .
  • Third ion implantation region 246 is formed at a depth greater than that of shallow trench isolation 220 .
  • Second ion implantation region 244 is formed between first ion implantation region 242 and third ion implantation region 246 .
  • second ion implantation region 244 is formed at a depth greater than that of first ion implantation region 242 but less than that of third ion implantation region 246 .
  • Third ion implantation region 246 may be formed in the shape of a straight line interconnecting the lower region of shallow trench isolation 220 and active region 230 between stacked gates 260 .
  • the recessed common source may be constructed in a three-dimensional structure, i.e., in a crooked pattern.
  • the common source is connected in a straight line to the lower region of shallow trench isolation 220 .
  • Current path 211 follows the straight line path of common source region.
  • an active etching process which increases sheet resistance (R s ) due to damage is removed, and thus, a reduction in variation of resistance as compared to an RCS method is achieved.
  • Such a crooked connection is achieved in a three-dimensional structure to connect common source 140 .
  • the total resistance necessary to reach an N-th active region is 3NR.
  • common source 240 includes deep implant region 240 a and shallow implant region 240 b . Also, a short circuit occurs vertically, common source 240 may be formed connected in a straight line to the lower region of shallow trench isolation 220 . Specifically, resistance (R) is proportion to the length of a resistant object, and the total resistance decreases as the length of the resistance object decreases. In accordance with embodiments, regions connected to the common source below shallow trench isolation 220 are connected in a straight line to each other, and active region 230 and common source 240 are connected by implant regions 242 , 244 and 246 in consideration of the above fact.
  • the total resistance necessary to reach an N-th active region may be the same value as the conventional method, i.e., 3NR.
  • Example FIG. 5 illustrates a manufacturing method of a flash memory in accordance with embodiments.
  • shallow trench isolation 220 and active region 230 are defined in substrate 210 .
  • a plurality of stacked gates 260 are formed on and/or over active regions 230 .
  • Photoresist pattern 310 is formed to cover drain region 250 .
  • a common source line region, i.e., I-I′ line region is opened by photoresist pattern 310 .
  • Example FIG. 6 is a sectional view taken along line I-I′ of example FIG. 5 .
  • an ion implantation process is performed with respect to active region 230 and shallow trench isolation 220 to form deep implant region 240 a in shallow trench isolation 220 and active region 230 between stacked gates 260 .
  • deep implant region 240 a may be formed by performing an ion implanting process several times with respect to shallow trench isolation 220 and active region 230 between stacked gates 260 . While it is possible to form deep implant region 240 a by performing an ion implanting process three times, embodiments are not restricted to this, and thus, the ion implanting process may be performed twice or four or more times.
  • first ion implantation step (A) is carried out to form first ion implantation region 242 such that first ion implantation region 242 is formed at a depth less than that of shallow trench isolation 220 .
  • second ion implantation step (B) is carried out to form third ion implantation region 244 at shallow trench isolation 220 and active region 230 between stacked gates 260 such that second ion implantation region 244 is formed at a depth greater than that of first ion implantation region 242 .
  • Third ion implantation step (C) is then carried out to form third ion implantation region 246 at shallow trench isolation 220 and active region 230 between stacked gates 260 such that third ion implantation region 246 is formed at a depth greater than that of shallow trench isolation 220 .
  • third ion implantation region 246 may be connected in a straight line to the lower region of shallow trench isolation 220 and active region 230 .
  • Example FIG. 8 is a sectional view taken along line II-II′ of example FIG. 5 .
  • Some stacked gates 260 and drain region 250 are covered by photoresist pattern 310 and the common source region is thereby exposed by an etching process.
  • the height or thickness of stacked gates 260 may be in a range of between 2800 ⁇ to 3800 ⁇ , preferably 3400 ⁇ .
  • the depth of shallow trench isolation 220 may be in a range between 2000 ⁇ to 3000 ⁇ , preferably 2600 ⁇ . Accordingly, the height or thickness of stacked gates 260 may be greater than the depth of shallow trench isolation 220 .
  • a self aligning method is used based on a fact that the thickness of stacked gates 260 is greater by approximately 800 ⁇ than the depth of shallow trench isolation 220 , and therefore, the process is carried out in a more efficient manner.
  • an RIE is not carried out as compared with the performing of the ion implantation after the execution of the RIE according to other methods. Consequently, it is possible to prevent the reduction in process margin due to the difference of the depth profile and the stress caused by the RIE.
  • the thickness of the poly regions of stacked gates 260 is greater than the depth of shallow trench isolations 220 even at a portion not blocked by photoresist pattern 310 . Accordingly, the blocking is carried out by the poly regions of stacked gates 260 , and therefore, the entry into the channel is not achieved.
  • a shallow trench isolation (STI) etching step is omitted, and therefore, the step difference may be decreased to approximately 2000 to 4000 ⁇ as compared with other methods.
  • control gate having a thickness of 2100 ⁇ +ONO having a thickness of 250 ⁇ +floating gate having a thickness of 1000 ⁇ +STI having a thickness of 2800 ⁇ a combined thickness of 6150 ⁇ .
  • control gate having a thickness of 2100 ⁇ +ONO having a thickness of 250 ⁇ +floating gate having a thickness of 1000 ⁇ a combined thickness of 3350 ⁇ . Consequently, the height is reduced by approximately 54%.
  • first ion implantation step (A) includes implanting phosphorus ions at an energy of approximately 120 to 150 KeV, preferably 135 KeV, and a dosage of 10 to 10 14 /cm 2 to form first ion implantation region 242 at projection range (R p or ion implantation peak) having a depth of approximately 1350 ⁇ to 1650 ⁇ , preferably 1500 ⁇ .
  • second ion implantation step (B) includes implanting phosphorus ions at an energy of approximately 140 to 180 KeV, preferably 160 KeV, and a dosage of 10 13 to 10 14 /cm 2 to form second ion implantation region 244 at a projection range (R p or ion implantation peak) having a depth of approximately 2000 ⁇ to 2400 ⁇ , preferably 2200 ⁇ .
  • third ion implantation step (C) includes implanting phosphorus (P) at an energy of approximately 140 to 220 KeV, preferably 200 KeV, and a dose of 10 13 to 10 14 /cm 2 to form third ion implantation region 246 at a projection range (R p or ion implantation peak) having a depth of approximately 2500 ⁇ to 2900 ⁇ , preferably 2700 ⁇ .
  • P phosphorus
  • first ion implantation step (A) includes implanting arsenic ions at an energy of approximately 220 to 280 KeV, preferably 250 KeV, and a dosage of 10 13 to 10 14 /cm 2 to form first ion implantation region 242 at a projection range (R p or ion implantation peak) having a depth of approximately 1350 ⁇ to 1650 ⁇ , preferably 1500 ⁇ .
  • second ion implantation step (B) includes implanting arsenic ions at an energy of approximately 330 to 410 KeV, preferably 370 KeV, and a dosage of 10 13 to 10 14 /cm 2 to form second ion implantation region 244 at a projection range (R p or ion implantation peak) having a depth of approximately 2000 ⁇ to 2400 ⁇ , preferably 2200 ⁇ .
  • the third ion implantation step (C) includes implanting arsenic ions at an energy of approximately 410 to 510 KeV, preferably 460 KeV, and a dosage of 10 13 to 10 14 /cm 2 to form third ion implantation region 246 at a projection range (R p or ion implantation peak) having a depth of approximately 2400 ⁇ to 3000 ⁇ , preferably 2700 ⁇ .
  • shallow implant region 240 b is formed at the surface of active region 230 between stacked gates 260 .
  • the lower portion of shallow trench isolation 220 at desired regions are connected by the deep ion implantation process.
  • such connection is meaningless when the bottom of shallow trench isolation 220 and the surface of active region 230 are not connected to each other.
  • CSD cell source/drain
  • HV LDD high-voltage lightly doped drain
  • LV LDD low-voltage lightly doped drain
  • arsenic (As) ions are used for the ion implantation process carried out at an energy of approximately 13 to 17 KeV, preferably 15 KeV, and a dosage of 2 ⁇ 10 14 /cm 2 to form shallow implant region 240 b at a projection range (R p ) having a depth of approximately 130 ⁇ to 170 ⁇ , preferably approximately 150 ⁇ .
  • HV LDD high-voltage lightly doped drain
  • P phosphorus
  • LV LDD low-voltage lightly doped drain
  • arsenic (As) ions are used for the ion implantation process carried out at an energy of 36 to 44 KeV, preferably approximately 40 KeV, and a dosage of 2 ⁇ 10 14 /cm 2 to form shallow implant region 240 b at a projection range (R p ) having a depth of approximately 270 ⁇ to 330 ⁇ , preferably 300 ⁇ .
  • the process for forming the common source may be performed from approximately 1500 ⁇ . This means that the existing processes are used, and any additional process is not required.
  • embodiments are advantageous for at least the following. It is possible to skip two essential RIE processes (RCS oxide RIE and etch damage CDE) used in other methods, thereby simplifying the process and preventing or retraining the occurrence of defectiveness which may be caused using other methods. Also, an additional ion implanting process is not required, and a RIE step is omitted. For example, in an ion implanting method, 0-degree ion implantation+tilt ion implantation are substituted in embodiments by deep ion implantation depending upon the depth of the shallow trench isolation (STI). Moreover, an STI etch step is omitted, and therefore, the step difference is decreased to approximately 2000 to 4000 ⁇ as compared with other methods.
  • STI shallow trench isolation
  • the step difference may be decreased to approximately 2800 ⁇ .
  • a subsequent process margin is increased, and a possibility that a photoresist residue (PR residue) is generated is eliminated.
  • oxide etching is not performed in embodiments, with the result that damage to a control gate and a floating gate is minimized. While damage may occur during the deep ion implanting process, such damage is minimal when compared to the damage caused by oxide etching. Yet and still, since oxide etching is not performed, stress is not applied to the edge of the STI at the time of performing the RIE, and therefore, a failure does not occur.
  • a word line (W/L) stress failure occurs as the active region of the STI is damaged when a field at a recessed common source (RCS) region is removed.
  • the etching is not performed, and therefore, stress due to the etch damage does not occur at the active edge region.
  • the RCS is constructed in a three-dimensional structure, i.e., crooked, however, in embodiments the common source is connected in a straight line to the lower region of the STI and an active etching process, which increases sheet resistance (R s ) due to the cause of damage is removed. Therefore, it is possible to reduce variation of resistance as compared with other RCS methods.

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  • General Physics & Mathematics (AREA)
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KR1020070090832A KR100872720B1 (ko) 2007-09-07 2007-09-07 플래시 메모리 및 그 제조방법
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JP (1) JP5032421B2 (zh)
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Cited By (2)

* Cited by examiner, † Cited by third party
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US20100012999A1 (en) * 2008-07-15 2010-01-21 Ji Hwan Park Semiconductor memory device and method of manufacturing the same
US20150162329A1 (en) * 2013-10-31 2015-06-11 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and formation thereof

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CN103715145B (zh) * 2012-09-29 2017-07-14 中芯国际集成电路制造(上海)有限公司 Nor快闪存储器的形成方法
US9679979B2 (en) * 2014-02-13 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure for flash memory cells and method of making same
US9876019B1 (en) * 2016-07-13 2018-01-23 Globalfoundries Singapore Pte. Ltd. Integrated circuits with programmable memory and methods for producing the same
CN106941076B (zh) * 2017-04-24 2020-05-01 上海华力微电子有限公司 一种降低闪存源端导通电阻的方法
CN112309853A (zh) * 2020-11-12 2021-02-02 上海华虹宏力半导体制造有限公司 屏蔽栅极沟槽结构的制备方法

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US20060138524A1 (en) 2004-12-23 2006-06-29 Kim Jum S Flash memory cell and method for manufacturing the same
US7741179B2 (en) * 2006-07-24 2010-06-22 Dongbu Hitek Co., Ltd. Method of manufacturing flash semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100012999A1 (en) * 2008-07-15 2010-01-21 Ji Hwan Park Semiconductor memory device and method of manufacturing the same
US20150162329A1 (en) * 2013-10-31 2015-06-11 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and formation thereof
US9673194B2 (en) * 2013-10-31 2017-06-06 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and formation thereof

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DE102008045344A1 (de) 2009-05-28
JP5032421B2 (ja) 2012-09-26
JP2009065154A (ja) 2009-03-26
TW200913235A (en) 2009-03-16
CN101383354A (zh) 2009-03-11
US20090065840A1 (en) 2009-03-12
CN101383354B (zh) 2010-11-03
KR100872720B1 (ko) 2008-12-05

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