US7830174B2 - Input/output circuit - Google Patents

Input/output circuit Download PDF

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US7830174B2
US7830174B2 US11/882,660 US88266007A US7830174B2 US 7830174 B2 US7830174 B2 US 7830174B2 US 88266007 A US88266007 A US 88266007A US 7830174 B2 US7830174 B2 US 7830174B2
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input
output
channel mos
transistor
circuit
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US20080030232A1 (en
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Osamu Uno
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Socionext Inc
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • the present invention relates to an input/output circuit including an input/output terminal for receiving an input signal of which voltage is higher than a power supply voltage.
  • a tolerant input/output circuit is used in such a semiconductor device.
  • a tolerant input/output circuit operates with no difficulty even when inputting an input signal having a voltage higher than a power supply voltage.
  • it is required that power consumption be reduced and operation frequency be improved.
  • FIG. 1 shows a tolerant input/output circuit of a first conventional example.
  • the tolerant input/output circuit enters an output mode when an enable signal En has an L level.
  • either one of output transistors P 1 and N 1 is activated in response to data Do. This provides an output signal, which is in phase with the data Do, from an input/output terminal Tio to an external circuit (not shown).
  • the tolerant input/output circuit enters an input mode when the enable signal En has an H level. In the input mode, the output transistors P 1 and N 1 are both inactivated, and an input signal Di provided from the external circuit to an input/output terminal Tio is further provided to an internal circuit.
  • the supply of power supply voltage V DD is suspended regardless of the state of the external circuit connected to the input/output terminal Tio.
  • the P-channel MOS transistor P 2 is activated in a situation in which the tolerant input/output circuit is in the standby state, the supply of power supply voltage V DD is suspended, and input signal VIH having a voltage higher than the power supply voltage V DD is input to the input/output terminal Tio as the input signal Di.
  • the input signal VIH is applied to the gate of the output transistor P 1 , which is formed by a P-channel MOS transistor. Accordingly, the output transistor P 1 is not activated, and a current path from the input/output terminal Tio to the source of the power supply voltage V DD is not formed. That is, the input/output terminal Tio does not receive the power supply voltage V DD .
  • a P-channel MOS transistor P 3 which is included in a transfer gate 1 , is activated. Activation of the transistor P 3 applies the input signal VIH to the gate of a P-channel MOS transistor P 4 , which is included in a transfer gate 2 .
  • the P-channel MOS transistor P 4 and an N-channel MOS transistor N 2 which are included in a transfer gate 2 , are both inactivated. Therefore, a current path connecting the input/output terminal Tio, the transistor P 2 , the transfer gate 2 , and an NAND circuit 3 is not formed.
  • a back gate control circuit 4 supplies an N-well (back gate) of the transistors P 1 to P 4 with voltage having a level that is greater than or equal to the power supply voltage V DD even if the supply of power supply voltage V DD is suspended. This prevents the generation of a PN junction diode between the power supply voltage V DD and the N-well of the transistors P 1 to P 4 .
  • the tolerant input/output circuit enters the input mode when the power supply voltage V DD is supplied and the enable signal En has an H level.
  • the input mode when the input/output terminal Tio is provided with the input signal VIH having a voltage higher than the power supply voltage V DD by an amount that is greater than or equal to the threshold value of a P-channel MOS transistor, the transistor P 2 is activated and the input signal VIH is applied to the gate of the output transistor P 1 . This inactivates the output transistor P 1 .
  • a current path connecting the input/output terminal Tio, the output transistor P 1 , and the source of the power supply voltage V DD is not formed.
  • the transistor P 3 of the transfer gate 1 is activated, the input signal VIH is applied to the gate of the transistor P 4 of the transfer gate 2 , and the transistor P 4 is inactivated.
  • the transistor P 4 is inactivated.
  • only the N-channel MOS transistor N 2 is activated in the transfer gate 2 , and voltage that is lower than the power supply voltage V DD by an amount corresponding to the threshold value of the transistor N 2 is applied to the output terminal of the NAND circuit 3 .
  • the enable signal En has an H level
  • the output signal of the NAND circuit 3 has an H level, or the power supply voltage V DD level. Therefore, a current path connecting the input/output terminal Tio, the transistors P 2 and N 2 , and the NAND circuit 3 is not formed.
  • the N-channel MOS transistor N 3 is inactivated in response to the enable signal En having an H level.
  • a current path connecting the input/output terminal Tio, the transfer gate 1 , the transistor N 3 , and the ground GND is not formed.
  • Japanese Patent No. 3557694 describes a structure similar to the input/output circuit of FIG. 1 .
  • FIG. 2 shows a tolerant input/output circuit of a second conventional example described in Japanese Patent No. 3190233.
  • this tolerant input/output circuit when the enable signal En has an H level, either one of the output transistors P 5 and N 4 is activated in accordance with the data Do, and an output signal that is in phase with the data Do is output from the input/output terminal Tio.
  • the enable signal En has an L level
  • the output transistors P 5 and N 4 are both inactivated, and the input signal Di provided from an external circuit to the input/output terminal Tio is further provided to an internal circuit.
  • the supply of power supply voltage V DD is suspended regardless of the state of the external circuit connected to the input/output terminal Tio.
  • the tolerant input/output circuit When the tolerant input/output circuit is in the standby state and the supply of power supply voltage V DD is suspended, if a high voltage input signal VIH is input to the input/output terminal Tio as the input signal Di, the P-channel MOS transistor P 6 is activated, and the input signal VIH is applied to the gate of the output transistor P 5 . However, the output transistor P 5 is not activated in this state. Thus, a current path from the input/output terminal Tio to the source of the power supply voltage V DD is not formed.
  • the P-channel MOS transistor P 7 is activated, and the input signal VIH is applied to the gate of the P-channel MOS transistor P 8 .
  • the transistor P 8 is inactivated. Accordingly, a current path connecting the input/output terminal Tio, the transistors P 6 , P 8 , and P 9 , and the source of the power supply voltage V DD is not formed.
  • the P-channel MOS transistors P 10 and P 11 are inactivated.
  • the N-well of each of the transistors P 5 , P 6 , and P 8 is in an indefinite state. This prevents the formation of a PN junction diode between the power supply voltage V DD and the N-well of the transistors P 5 , P 6 , and P 8 .
  • Similar operations are performed when the tolerant input/output circuit is in the input mode, supplied with the power supply voltage V DD , and receives the enable signal En at an L level even if a high voltage input signal VIH is input to the input/output terminal Tio.
  • FIG. 3 shows a tolerant input/output circuit of a third conventional example described in Japanese Patent No. 3441238.
  • the tolerant input/output circuit drives output transistors P 12 and N 5 in accordance with a plurality of input signals IN 1 to INN.
  • the P-channel MOS transistor P 13 is activated in a situation in which the tolerant input/output circuit is in the standby state, the supply of power supply voltage V DD is suspended, and a high voltage input signal VIH is input to the input/output terminal Tio.
  • the input signal VIH is applied to the gate of the output transistor P 12 .
  • the output transistor P 12 is not activated in this state.
  • a current path connecting the input/output terminal Tio, the output transistor P 12 , and the source of the power supply voltage V DD is not formed.
  • the P-channel MOS transistor P 14 is activated, and the input signal VIH is applied to the gate of the P-channel MOS transistor P 15 .
  • the transistor P 15 is inactivated. Accordingly, a current path connecting the input/output terminal Tio, the transistors P 13 and P 15 , and the source of the power supply voltage V DD is not formed.
  • the P-channel MOS transistor P 16 is activated, and the input signal VIH is applied to the N-well of the transistors P 12 , P 13 , P 14 , P 15 , P 16 , and P 17 .
  • the output signal of the NAND circuit 3 is provided to the gate of the output transistor P 1 via the transfer gate 2 .
  • the transistor N 2 of the transfer gate 2 is activated, and the gate potential at the output transistor P 1 then increases.
  • the transistor P 4 is activated. Then, the gate potential at the output transistor P 1 increases to the power supply voltage V DD level.
  • the transistor P 4 When the output signal of the NAND circuit 3 falls from an H level to an L level, the transistor P 4 is activated. Then, the gate potential at the output transistor P 1 decreases. Subsequently, the transistor N 2 is activated, and the gate potential at the output transistor P 1 decreases to an L level.
  • the response of the increase and decrease of the gate potential at the output transistor P 1 with respect to the rise and fall of the output signal of the NAND circuit 3 is slow due to the on-resistance of the transistors P 4 and N 2 .
  • the inactivation of the output transistor P 1 is delayed.
  • the operation of the output transistor P 1 cannot follow the data Do when the frequency of the data Do becomes high since the increase and decrease of the gate potential at the output transistor P 1 is slow. This obstructs increase of the operation speed.
  • the transistors N 2 and P 4 of the transfer gate 2 are alternately activated when the output signal of the NAND circuit 3 rises and falls.
  • the output signal of the transfer gate 2 provided to the gate of the output transistor P 1 has a waveform that includes an inflection point near a median potential of the output signal. The inflection point slows the increase and decrease of the gate potential at the output transistor P 1 .
  • the transistors P 7 and N 6 are activated when high voltage input voltage VIH is input to the input/output terminal Tio during the input mode in which the power supply voltage V DD is supplied. This forms a current path connecting the input/output terminal Tio, transistors P 7 , N 6 , pull-down resistor R 1 , and the ground GND. Accordingly, power consumption increases.
  • the transistor P 14 when the high voltage input signal VIH is input to the input/output terminal Tio during the input mode in which the power supply voltage V DD is supplied, the transistor P 14 is activated. Further, the transistor N 7 is normally activated. This forms a current path connecting the input/output terminal Tio, the transistors P 14 , N 7 , and the ground GND. Accordingly, power consumption increases.
  • the input/output circuit includes an input/output terminal, a pull-up output transistor, a pull-down output transistor, and a first logic circuit that operates in accordance with data and an enable signal.
  • the first logic circuit includes an output node connected to the gate of the pull-up output transistor. The first logic circuit activates the pull-up output transistor in the output mode and inactivates the pull-up output transistor in the input mode.
  • a second logic circuit operates in accordance with the data and the enable signal. The second logic circuit operates the pull-down output transistor in a complementary manner with respect to the pull-up output transistor in the output mode. The second logic circuit inactivates the pull-down output transistor in the input mode.
  • a control circuit maintains the pull-up output transistor in the inactivated state regardless of voltage being applied to the input/output terminal in the input mode.
  • a switch circuit disconnects the first logic circuit from a power supply when an input signal having voltage higher than the power supply voltage of the power supply is input to the input/output terminal in the input mode.
  • a back gate control circuit supplies back gates of P-channel MOS transistors in the first logic circuit and the switch circuit with back gate voltage having the same voltage as the input signal when the input signal is input to the input/output terminal in the input mode.
  • FIG. 1 is a circuit diagram of a conventional input/output circuit
  • FIG. 2 is a circuit diagram of a conventional input/output circuit
  • FIG. 3 is a circuit diagram of a conventional input/output circuit
  • FIG. 4 is a circuit diagram of an input/output circuit according to a first embodiment of the present invention.
  • FIG. 5 is a circuit diagram of an NAND circuit arranged in an input/output circuit according to a second embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a back gate control circuit arranged in an input/output circuit according to a third embodiment of the present invention.
  • FIG. 4 shows an input/output circuit according to a first embodiment of the present invention.
  • the input/output circuit operates in an input mode and an output mode in accordance with an enable signal En and data Do.
  • the enable signal En is provided to each of a NOR circuit (second logic circuit) 11 , inverter circuits 12 a and 12 b , and the gate of an N-channel MOS transistor N 21 , which is included in a transfer gate 13 .
  • the data Do is provided to the NOR circuit 11 and the gates of a P-channel MOS transistor P 21 and an N-channel MOS transistor N 22 , which are included in a NAND circuit (first logic circuit) 14 .
  • the output signal of the NOR circuit 11 is output from its output terminal and is provided to the gate of an output transistor N 25 , which is formed by an N-channel MOS transistor.
  • the output signal of the inverter circuit 12 b is provided to the gate of an N-channel MOS transistor N 24 .
  • the source of the transistor N 24 is connected to ground GND.
  • the drain of the transistor N 24 is connected to the gate of a P-channel MOS transistor P 22 , which is included in the NAND circuit 14 .
  • the output signal of the inverter circuit 12 a is provided to the gates of an N-channel MOS transistor N 23 and a P-channel MOS transistor P 23 , which are included in the NAND circuit 14 .
  • the NAND circuit 14 will now be described.
  • the sources of the transistors P 21 and P 23 are connected to the power supply voltage V DD .
  • the drains of the transistors P 21 and P 23 are connected to the source of the transistor P 22 .
  • the drain of the transistor P 22 is connected to the drain of the transistor N 22 .
  • the source of the transistor N 22 is connected to the drain of the transistor N 23 .
  • the source of the transistor N 23 is connected to ground GND.
  • the drains of the transistors P 22 and N 22 are connected to an output node NN 1 .
  • the output node NN 1 functions as an output terminal of the NAND circuit 14 .
  • the NAND circuit 14 is in the output mode when the enable signal En has an L level.
  • the L level enable signal En activates the transistor N 23 , inactivates the transistor P 23 , activates the transistor N 24 , and activates the transistor P 22 . Accordingly, the NAND circuit 14 is activated, and an inverted signal of the data Do is provided to the output node NN 1 .
  • the NAND circuit 14 is in the input mode when the enable signal En has an H level.
  • the H level enable signal En activates the transistor P 23 , inactivates the transistor N 23 , and activates the NAND circuit 14 .
  • the output node NN 1 is connected to the gate of the output transistor P 26 , which is formed by the P-channel MOS transistor.
  • the source of the output transistor P 26 is connected to the power supply voltage V DD .
  • the drain of the output transistor P 26 is connected to the drain of the output transistor N 25 .
  • the source of the output transistor N 25 is connected to ground GND.
  • the drains of the output transistors P 26 and N 25 are connected to the input/output terminal Tio.
  • the transistor P 26 is one example of a pull-up output transistor.
  • the transistor N 25 is one example of a pull-down output transistor.
  • the input/output terminal Tio is connected to the transistor P 22 of the NAND circuit 14 via the transfer gate 13 .
  • the gate of a P-channel MOS transistor P 24 which is included in the transfer gate 13 , is connected to the power supply voltage V DD .
  • the input/output terminal Tio is connected to the output node NN 1 by way of the P-channel MOS transistor P 25 .
  • the gate of the transistor P 25 is connected to the power supply voltage V DD .
  • a back gate control circuit 15 is formed by P-channel MOS transistors P 27 and P 28 .
  • the source of the transistor P 27 is connected to the power supply voltage V DD .
  • the drain of the transistor P 27 is connected to the drain of the transistor P 28 .
  • the source of the transistor P 28 is connected to the input/output terminal Tio.
  • the gate of the transistor P 27 is connected to the gate of the transistor P 22 .
  • the gate of the transistor P 28 is connected to the power supply voltage V DD .
  • Back gate voltage VB is output from a connecting node NN 2 of the drains of the transistors P 27 and P 28 .
  • the back gate voltage VB is supplied to the transistors P 27 and P 28 and the transistors P 25 , P 26 , P 24 , and P 22 .
  • the back gate control circuit 15 is in the output mode when the enable signal En has an L level. In the output mode, the transistor N 24 is activated, and the transistor P 27 is activated. In this case, the transistor P 28 is inactivated. Therefore, the back gate voltage VB has the same level as the power supply voltage V DD .
  • the transistor N 21 of the transfer gate 13 is activated when the input/output terminal Tio shifts to an L level, or ground GND level.
  • the transistor P 27 is activated, and the back gate voltage VB becomes equal to the power supply voltage V DD .
  • the gate voltage of the transistor P 27 becomes lower than the level of the power supply voltage V DD by the threshold value of the transistor N 21 , and the transistor P 27 is maintained in the activated state.
  • the transistor P 24 is activated in the transfer gate 13 , and the input signal VIH is applied to the transistor P 27 . This inactivates the transistor P 27 .
  • the transistor P 28 is activated and the back gate voltage VB becomes equal to the voltage level of the input signal VIH.
  • a buffer circuit 16 is connected to the input/output terminal Tio.
  • a signal provided to the input/output terminal Tio in the input mode is further provided to the internal circuit via the buffer circuit 16 .
  • the enable signal En shifts to an L level when entering the output mode. This inactivates the transfer gate 13 and activates the transistor N 24 . Further, the NAND circuit 14 is activated, the inverted signal of the data Do is output to the output node NN 1 , and the inverted signal of the data Do is output from the NOR circuit 11 .
  • either one of the output transistors P 26 and N 25 is activated, and an output signal that is in phase with the data Do is output from the input/output terminal Tio.
  • the output transistor N 25 is operated in a complementary manner with respect to the output transistor P 26 in the output mode.
  • the transistor P 27 is activated, the transistor P 28 is inactivated, and the back gate voltage VB of the power supply voltage V DD level is output.
  • the enable signal En shifts to an H level when entering the input mode.
  • the output signal of the NOR circuit 11 shifts to an L level. This inactivates the output transistor N 25 .
  • the transistor P 23 is activated, the transistor N 23 is inactivated, the NAND circuit 14 is inactivated, and the transistor N 24 is inactivated. Furthermore, the transistor N 21 of the transfer gate 13 is activated.
  • the gate of the transistor P 27 is shifted to an L level via the transfer gate 13 .
  • the transistor P 27 is activated. Accordingly, the back gate voltage VB having the level of the power supply voltage V DD is output from the back gate control circuit 15 .
  • the transistor P 22 maintained in the activated state
  • the output node NN 1 is maintained at an H level
  • the output transistor P 26 is maintained in the inactivated state.
  • the transistor P 27 is activated, and the back gate voltage VB of the power supply voltage V DD level is output from the back gate control circuit 15 .
  • the transistor P 25 is activated, and the gate potential at the output transistor P 26 becomes equal to the voltage level of the input signal VIH.
  • the output transistor P 26 is maintained in the inactivated state even if the input signal VIH is applied to the input/output terminal Tio.
  • a current path connecting the input/output terminal Tio, the output transistor P 26 , and the source of the power supply voltage V DD is not formed.
  • the transistor P 24 of the transfer gate 13 is activated, and the input signal VIH is applied to the gate of the transistor P 22 .
  • the transistor P 22 is inactivated. Accordingly, a current path connecting the input/output terminal Tio, the transistors P 25 and P 22 , and the source of the power supply voltage V DD is not formed.
  • the transistor N 24 is inactivated. Thus, a current path connecting the input/output terminal Tio, the transistors P 24 and N 24 , and the ground GND is also not formed.
  • the back gate control circuit 15 when the input signal VIH is applied to the input/output terminal Tio, the transistor P 27 is inactivated and the transistor P 28 is activated. As a result, the back gate voltage VB, which is equal to the voltage of the input signal VIH, is output. As a result, formation of PN junction diode, that is, formation of a current path from the source of the power supply voltage V DD to the N-well is prevented in each of the transistors P 27 , P 28 , P 25 , P 26 , P 24 , and P 22 , which are supplied with the back gate voltage VB.
  • the output transistor P 26 is maintained in the inactivated state even if the input signal VIH is applied to the input/output terminal Tio. Further, a current path connecting the input/output terminal Tio, the output transistor P 26 , and the source of the power supply voltage V DD is not formed.
  • Such an operation ensures that the transistor P 25 , the transfer gate 13 , and the transistors P 22 and P 23 inactivate the output transistor P 26 in the input mode.
  • the transistor P 25 , the transfer gate 13 , and the transistors P 22 and P 23 operate as a control circuit.
  • the transistor P 24 of the transfer gate 13 is activated and the input signal VIH is applied to the gate of the transistor P 22 .
  • the transistor P 22 is inactivated. Accordingly, the transistor P 22 serves as a switch circuit and disconnects the output node NN 1 from the power supply voltage V DD .
  • a current path connecting the input terminal Tio, the transistors P 25 and P 22 , and the source of the power supply voltage V DD is not formed.
  • the transistor N 24 is inactivated. Thus, the current path connecting the input/output terminal Tio, the transistors P 24 and N 24 , and the ground GND is not formed.
  • the transistor P 27 is inactivated and the transistor P 28 is activated when the input signal VIH is applied to the input/output terminal Tio.
  • the formation of a PN junction diode that is, the formation of the current path from the source of the power supply voltage V DD to the N-well is prevented in each of the transistors P 27 , P 28 , P 25 , P 26 , 24 , and P 22 , which are supplied with the back gate voltage VB.
  • the input/output circuit outputs the output signal in phase with the data Do from the input/output terminal Tio.
  • the input/output circuit provides the input signal provided to the input/output terminal Tio to the internal circuit via the buffer circuit 16 .
  • the NAND circuit 14 is inactivated in the input mode since the transistors P 22 , P 23 , N 23 are inactivated. This prevents the formation of a current path connecting the input/output terminal Tio, the NAND circuit 14 , and the source of the power supply voltage V DD even if a signal having a level higher than or equal to the power supply voltage V DD is input to the input/output terminal Tio. Thus, the power consumption of the input/output circuit is reduced.
  • a current path connecting the output node NN 1 , the NAND circuit 14 , and the power supply voltage V DD or the ground GND is prevented from being formed even if the output node NN 1 of the NAND circuit 14 is directly connected to the gate of the output transistor P 26 . This reduces power consumption of the input/output circuit.
  • a transfer gate is not arranged between the output node NN 1 and the output transistor P 26 . This enables the operation frequency of the output transistor P 26 to increase.
  • a NAND circuit 17 shown in FIG. 5 is used as the first logic circuit in lieu of the NAND circuit 14 of the first embodiment.
  • the NAND circuit 17 is formed by an AND circuit 18 and an inverter circuit 19 . Data Do and an inverted signal of the enable signal En are input to the AND circuit 18 .
  • the inverter circuit 19 includes P-channel MOS transistors P 29 and P 30 and an N-channel MOS transistor N 26 .
  • the source of the transistor P 29 is connected to the power supply voltage V DD .
  • the drain of the transistor P 29 is connected to the source of the transistor P 30 .
  • the drain of the transistor P 30 is connected to the drain of the transistor N 26 .
  • the source of the transistor N 26 is connected to ground GND.
  • the output signal of the AND circuit 18 is input to the gates of the transistors P 29 and N 26 .
  • the drains of the transistors P 30 and N 26 are connected to the output node NN 1 .
  • the gate of the transistor P 30 is connected to the drain of the transistor N 24 and connected to the input/output terminal Tio via the transfer gate 13 .
  • the back gate voltage VB is supplied from the back gate control circuit 15 to the back gate of the transistor P 30 .
  • the parts other than the NAND circuit 17 are the same as the first embodiment.
  • the NAND circuit 17 when the enable signal En shifts to an L level in the output mode, a signal in phase with the data Do is output from the AND circuit 18 . Further, the transistor P 30 is activated. Thus, the inverted signal of the output signal of the AND circuit 18 is output from the inverter circuit 19 to the output node NN 1 .
  • the enable signal En shifts to an H level in the input mode
  • the output signal of the AND circuit 18 shifts to an L level.
  • the transistor N 26 is inactivated in the inverter circuit 19 .
  • the NAND circuit 17 operates in the same manner as the NAND circuit 14 of the first embodiment. Further, only the N-channel MOS transistor N 26 is arranged between the output node NN 1 and ground GND. Thus, the falling speed of the output node NN 1 increases, and the time required to shift the output transistor P 26 from an inactivated state to an activated state is shortened. Accordingly, the operation frequency of the input/output circuit may be increased.
  • a back gate control circuit 20 of FIG. 6 is used in lieu of the back gate control circuit 15 of the first embodiment.
  • the back gate control circuit 20 includes P-channel MOS transistors P 31 and P 32 .
  • the back gate control circuit 20 is similar to the back gate control circuit 15 of the first embodiment except in that the gate of the transistor P 31 is connected to the input/output terminal Tio.
  • the back gate control circuit 20 outputs back gate voltage VB having the level of the power supply voltage V DD .
  • the back gate control circuit 20 has the same advantages as the back gate control circuit 15 of the first embodiment.
  • the NAND circuit 14 and the NOR circuit 11 may be changed to other logic circuits in accordance with the logic of the enable signal En and the data Do.
  • the buffer circuit 16 may be omitted from each embodiment when connecting the output terminal to a signal wire having a level that is higher than or equal to the level of the power supply voltage V DD in the high impedance state or a state in which the supply of power supply voltage V DD is suspended.

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US8947131B2 (en) 2012-10-04 2015-02-03 Samsung Electronics Co., Ltd. Multi-voltage supplied input buffer
US20160191025A1 (en) * 2014-12-25 2016-06-30 Semiconductor Manufacturing Internatioanal (Shanghai) Corporation Interface device, related method, and related open-drain device

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EP1887697A2 (de) 2008-02-13
KR100919655B1 (ko) 2009-09-30
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EP1887697A3 (de) 2008-10-01
KR20080013759A (ko) 2008-02-13
JP2008042542A (ja) 2008-02-21

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