US6970035B2 - Charge pump circuit - Google Patents

Charge pump circuit Download PDF

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Publication number
US6970035B2
US6970035B2 US09/776,011 US77601101A US6970035B2 US 6970035 B2 US6970035 B2 US 6970035B2 US 77601101 A US77601101 A US 77601101A US 6970035 B2 US6970035 B2 US 6970035B2
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circuit
clock signal
transistor
terminal
charge pump
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US20010011919A1 (en
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Takashi Tanimoto
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Deutsche Bank AG New York Branch
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Definitions

  • the present invention relates to a charge pump circuit, and more particularly, to a charge pump for converting a voltage with a capacitor.
  • FIG. 1A is a schematic circuit diagram of a first example of a prior art charge pump circuit 501
  • FIG. 1B is a schematic circuit diagram of a second example of a prior art charge pump circuit 502
  • the charge pump circuit 501 includes two diodes D 1 , D 2 , a capacitor C 1 , and an output capacitor Cout.
  • the charge pump circuit 502 includes p-channel MOS transistors T 1 , T 2 in lieu of the diodes D 1 , D 2 .
  • a clock signal CLK is provided via the capacitor C 1 to a node N 1 between the diodes D 1 , D 2 of the charge pump circuit 501 or between the transistors T 1 , T 2 of the charge pump circuit 502 .
  • the charge pump circuits 501 , 502 each convert a power supply voltage VDD, the value of which is a high logic level of the clock signal CLK, to a negative voltage “ ⁇ VDD”.
  • FIG. 2 is a combined timing and waveform chart illustrating the operation of the charge pump circuits 501 , 502 .
  • the clock signal CLK is high, and the diode D 1 (transistor TR 1 ) is activated.
  • the voltage Vn 1 at node N 1 is substantially equal to zero volts (ground voltage GND), and the output voltage Vout is also substantially equal to the ground voltage GND.
  • the capacitor C 1 decreases the node voltage Vn 1 to substantially ⁇ VDD.
  • the diode D 1 transistor TR 1
  • the diode D 2 transistor TR 2
  • the output voltage Vout becomes equal to substantially ⁇ VDD, as shown in FIG. 2 . This charges the output capacitor Cout to ⁇ VDD.
  • the capacitor C 1 substantially increases the node voltage Vn 1 to the ground voltage GND. This deactivates the diode D 2 (transistor TR 2 ) and holds the output voltage Vout at the vicinity of the charge voltage ⁇ VDD of the output capacitor Cout.
  • an integrated circuit may be configured from the charge pump circuits 501 , 502 .
  • the charge pump circuits 501 , 502 are used in an IC as a voltage conversion circuit for obtaining a desired voltage value.
  • the charge pump circuits 501 , 502 are used in a charge-coupled device (CCD) driver IC or a memory IC.
  • CCD charge-coupled device
  • the charge pump circuits 501 , 502 enable step-up and step-down of a voltage with a simple circuit configuration. However, voltage decreases resulting from a threshold voltage value Vth of the diodes D 1 , D 2 (or the transistors T 1 , T 2 ) may decrease the absolute value of the output voltage Vout.
  • the absolute logic value of the output voltage Vout is VDD ⁇ 2Vth and decreased from the maximum logic value VDD by 2Vth. The decrease in the absolute value of the output voltage Vout decreases the voltage conversion efficiency of the charge pump circuit.
  • the p-channel MOS transistors T 1 , T 2 of FIG. 1B may be used in the conventional manner.
  • the through current generated when controlling the activation and deactivation of the transistors T 1 , T 2 decreases voltage conversion efficient and lowers transistor reliability.
  • the present invention provides a charge pump circuit including a plurality of switching transistors connected in series between an output terminal and reference potential terminal of the charge pump circuit.
  • the plurality of switching transistors includes a first transistor connected to the reference potential terminal and a second transistor connected to the first transistor.
  • the first transistor has a control terminal provided with a first clock signal
  • the second transistor has a control terminal provided with a second clock signal.
  • the first and second clock signals have inverted phases.
  • a capacitor as connected to a node between the first and second transistors and has a first terminal and a second terminal.
  • a delay circuit is connected between the second terminal of the capacitor and the control terminal of the first transistor. The delay circuit delays the first clock signal by a predetermined time and provides the delayed first clock signal to the second terminal of the capacitor.
  • FIG. 1A is a schematic circuit diagram of a first example of a prior art charge pump circuit
  • FIG. 1B is a schematic circuit diagram of a second example of a prior art charge pump circuit
  • FIG. 2 is a combined timing and waveform chart illustrating the operations of the charge pump circuits of FIGS. 1A and 1B ;
  • FIG. 3 is a schematic circuit diagram of a charge pump circuit according to a first embodiment of the present invention.
  • FIG. 4 is a combined timing and waveform chart of the charge pump circuit of FIG. 3 ;
  • FIG. 5 is a schematic circuit diagram of a charge pump circuit according to a second embodiment of the present invention.
  • FIG. 6 is a combined timing and waveform chart of the charge pump circuit of FIG. 5 ;
  • FIG. 7 is a schematic block diagram of a CCD driver incorporating the charge pump circuits of FIGS. 3 and 5 ;
  • FIG. 8 is a schematic circuit diagram of a charge pump circuit according to a third embodiment of the present invention.
  • FIG. 9 is a combined timing and waveform chart illustrating the operation of the charge pump circuit of FIG. 8 ;
  • FIG. 10 is a schematic circuit diagram of a charge pump circuit according to a fourth embodiment of the present invention.
  • FIG. 11 is a combined timing and waveform diagram illustrating the operation of the charge pump circuit of FIG. 10 .
  • FIG. 3 is a schematic circuit diagram of a charge pump circuit 51 according to a first embodiment of the present invention.
  • the charge pump circuit 51 converts a power supply voltage VDD to ⁇ VDD (logic value), which is a negative voltage, and includes two switching transistors TR 1 , TR 2 , which are preferably n-channel MOS transistors, a capacitor C 1 , and an output capacitor Cout,
  • the sources S and drains D of the switching transistors TR 1 , TR 2 are inverted in accordance with the operational status of the transistors TR 1 , TR 2 .
  • the charge pump circuit 51 further includes a timing adjustment circuit 10 , CMOS inverters 1 , 2 , and a buffer circuit B 1 , which serves as a delay circuit.
  • the timing adjustment circuit 10 includes inverters 11 , 12 , 13 and NAND circuits 14 , 15 .
  • the timing adjustment circuit 10 receives a clock signal CLK. Based on the clock signal CLK, the timing adjustment circuit 10 generates control clock signals ⁇ T 1 , ⁇ T 2 , which respectively activate and deactivate the switching transistors TR 1 , TR 2 , and adjusts the activation and deactivation timing of the switching transistors TR 1 , TR 2 .
  • the source S of an n-channel MOS transistor la of the CMOS inverter (buffer circuit) 1 is connected to the source S of the switching transistor TR 1 .
  • a source S of an n-channel MOS transistor 2 a of the CMOS inverter (buffer circuit) 2 is connected to a source S of the switching transistor TR 2 . Due to such connection, when the voltage at the sources of the switching transistors TR 1 , TR 2 become negative, the low voltage value of the control clock signals ⁇ T 1 , ⁇ T 2 become negative and the deactivation of the transistors TR 1 , TR 2 is ensured.
  • the buffer circuit (delay circuit) B 1 is connected between the output terminal of the CMOS inverter 1 and the capacitor C 1 .
  • the buffer circuit B 1 converts the signal level of the control clock signal ⁇ T 1 and delays the clock signal ⁇ T 1 by a predetermined time to generate a capacitor clock signal ⁇ C 1 .
  • the capacitor clock signal ⁇ C 1 is provided to the capacitor C 1 .
  • the buffer circuit B 1 is configured by, for example, a plurality of CMOS inverters (not shown).
  • the capacitor clock signal ⁇ C 1 is provided to the capacitor C 1 thereby changing the source voltage (voltage at node N 1 ) Vn 1 of the transistor TRI.
  • the switching transistor TR 1 when the switching transistor TR 1 is activated, the activation of a parasitic transistor of the transistor TR 1 in a semiconductor substrate is prevented. Further, when the transistor TR 1 is deactivated, fluctuation of the node voltage Vn 1 , which is caused by the transistor TR 1 , is prevented.
  • FIG. 4 is a combined timing and waveform chart illustrating the operation of the charge pump circuit 51 .
  • FIG. 4 illustrates normal operation of the charge pump circuit 51 and does not illustrate transitional operations performed when activating the charge pump circuit 51 .
  • the clock signal CLK goes high (VDD) This causes the output signal of the inverter 12 to go low (zero volts) and the output signal of the NAND circuit 15 to go high.
  • the output signal of the NAND circuit 15 is provided to the input terminal of the CMOS inverter 2 , and the inverter 2 outputs the control clock signal ⁇ T 2 at a low level ( ⁇ VDD).
  • the switching transistor TR 2 goes off, the output signal of the inverter 11 goes high, and the output signal of the NAND circuit 14 goes low (zero volts).
  • the output signal of the NAND circuit 14 is provided to the input terminal of the CMOS inverter 1 .
  • the inverter 1 outputs the control clock signal ⁇ T 1 at a high level (VDD).
  • VDD high level
  • the clock signal CLK goes low (zero volts). This causes the output signal of the NAND circuit 14 to go high.
  • the high output signal is provided to the CMOS inverter 1 .
  • the inverter 1 outputs the control clock signal ⁇ T 1 at the low level ( ⁇ VDD), and the switching transistor TR 1 goes off.
  • the capacitor clock signal ⁇ C 1 shifts to the low level (zero volts).
  • the output signal of the inverter 13 shifts to the high level (VDD) and causes the output signal of the NAND circuit 15 to go low (zero volts).
  • the output signal of the NAND circuit 15 is provided to the CMOS inverter 2 , and the inverter 2 outputs the control clock signal ⁇ T 2 at the high level (VDD)
  • the switching transistor TR 2 goes on, Afterward, when the clock signal CLK goes high again at time t 5 , operations are performed in the same manner as at time t 1 .
  • the charge pump circuit 51 by repeating the above operations, the influence of the threshold voltage Vth of the switching transistors TR 1 , TR 2 is eliminated, and the output voltage Vout that is close to the logic value ⁇ VDD is obtained.
  • the switching transistors TR 1 , TR 2 do not go on simultaneously. That is, referring to FIG. 4 , an activation time period ⁇ on 2 of the switching transistor TR 2 is set during a deactivation time period ⁇ off 1 of the switching transistor TR 1 . An activation time period ⁇ on 1 of the switching transistor TR 1 is set during a deactivation time period ⁇ off 2 of the switching transistor TR 2 Thus, the desired output voltage Vout is efficiently obtained, and a large through current is prevented from being generated in the transistors TR 1 , TR 2 . This increases the reliability of the charge pump circuit.
  • the source voltage (voltage at node N 1 ) Vn 1 of the transistor TR 1 changes after the gate voltage of the switching transistor TR 1 is determined. This avoids the influence of parasitic transistor during switching of the switching transistor TR 1 and prevents fluctuations of the node voltage Vn 1 . As a result, the operation of the charge pump circuit is guaranteed, and the reliability of the charge pump circuit is increased.
  • the sources S of the n-channel MOS transistors of the CMOS inverters 1 , 2 are respectively connected to the sources 3 of the switching transistors TR 1 , TR 2 .
  • the gate voltages (control clock signals ⁇ T 1 , ⁇ T 2 ) for ensuring the deactivation of the transistors TR 1 , TR 2 are obtained through a simple circuit configuration.
  • the timing adjustment circuit 10 generates control clock signals ⁇ T 1 , ⁇ T 2 , which prevent the switching transistors TR 1 , TR 2 from being activated simultaneously. This prevents a large through current from flowing through the transistors TR 1 , TR 2 . As a result, the reliability of the transistors TR 1 , TR 2 increases, and power consumption of the charge pump circuits decreases.
  • the threshold voltage Vth of the switching transistors TR 1 , TR 2 does not affect voltage conversion. Thus, the voltage conversion obtains a high voltage value (absolute value).
  • a charge pump circuit 52 according to a second embodiment of the present invention will now be described centering on parts differing from the charge pump circuit 51 of the first embodiment.
  • FIG. 5 is a schematic circuit diagram of the charge pump circuit 52 of the second embodiment.
  • the charge pump circuit 52 has a timing adjustment circuit 20 that differs from the timing adjustment circuit 10 of the charge pump circuit 51 of the first embodiment.
  • the charge pump circuit 52 includes four switching transistors TR 1 , TR 2 , TR 3 , TR 4 and three capacitors C 1 , C 2 , C 3 and converts the power supply voltage VDD to negative voltage ⁇ 3VDD (logic value).
  • the sources S and drains D of the switching transistors TR 1 , TR 2 , TR 3 , TR 4 are inverted in accordance with the operational conditions of the transistors TR 1 , TR 2 , TR 3 , TR 4 .
  • the timing adjustment circuit 20 includes three inverters 21 , 22 , 23 and two NOR circuits 24 , 25 .
  • the timing adjustment circuit 20 adjusts the timing of clock signals, which have inverted phases, so that the clock signals do not simultaneously activate two switching transistors.
  • CMOS inverters 1 , 2 , 3 , buffer circuits B 1 , B 2 , B 3 , and capacitors C 1 , C 2 , C 3 are connected to the switching transistors TR 1 , TR 2 , TR 3 , respectively.
  • a CMOS inverter 4 is connected to the switching transistor TR 4 .
  • the control clock signals ⁇ T 1 , ⁇ T 3 are the same signal
  • the control clock signals ⁇ T 2 , ⁇ T 4 are the same signal
  • the capacitor clock signals ⁇ C 1 , ⁇ C 3 are the same signal.
  • FIG. 6 is a combined timing and waveform diagram illustrating the operation of the charge pump circuit 52 .
  • the buffer circuits B 1 , B 3 delay the control clock signals ⁇ T 1 , ⁇ T 3 to generate the capacitor clock signals ⁇ C 1 , ⁇ C 3 , respectively.
  • the buffer circuit B 2 delays the control clock signals ⁇ T 2 to generate the capacitor clock signal ⁇ C 2 .
  • the set of the control clock signals ⁇ T 1 , ⁇ T 3 and the set of the Control clock signals ⁇ T 2 , ⁇ T 4 are generated so that when one set is low (the corresponding transistors being deactivated), the other set is high (the corresponding transistors being activated). That is, referring to FIG. 6 , the activation time period ⁇ on 1 of the switching transistors TR 1 , TR 3 is set during the deactivation time period ⁇ off 2 of the switching transistor TR 2 , TR 4 . The activation time period ⁇ on 2 of the switching transistors TR 2 , TR 4 is set during the deactivation time period ⁇ off 1 of the switching transistor TR 1 , TR 3 .
  • FIG. 7 is a schematic block diagram of the CCD driver 30 .
  • the CCD driver 30 drives a frame transfer CCD (not shown). More specifically, the CCD driver 30 synchronously transfers the charge generated at the imaging portion of the CCD to perform vertical transfer drive of charges.
  • the CCD driver 30 includes a high voltage generation charge pump circuit 51 A, a negative voltage generation charge pump 52 , and a vertical drive circuit 31 .
  • Pumping capacitors C 1 , C 2 , C 3 and an output capacitor Cout are externally connected to the driver 30 .
  • the charge pump circuit 52 obtains substantially ⁇ 3VDD as the logic value output voltage Vout.
  • the output voltage Vout is provided to the high voltage generation charge pump circuit 51 A and the vertical drive circuit 31 .
  • the high voltage generation charge pump circuit 51 A has the circuit configuration of, for example, the charge pump circuit 51 .
  • the switching transistors TR 1 , TR 2 are p-channel MOS transistors, and the drain of the transistor TR 1 is connected to the power supply voltage VDD.
  • the sources (power supply terminal) of the CMOS inverters 1 , 2 are connected to the node N 1 , and the sources of the n-channel MOS transistors of the CMOS inverters 1 , 2 are grounded.
  • the clock signal CLK undergoes level conversion based on the output voltage Vout of the charge pump circuit 52 .
  • the charge pump circuit 52 of the second embodiment has the advantages discussed below,
  • the sources S of the n-channel MOS transistors of the CMOS inverters 1 , 2 , 3 , 4 are respectively connected to the sources S of the switching transistors TR 1 , TR 2 , TR 3 , TR 4 .
  • the gate voltages (control clock signals ⁇ T 1 , ⁇ T 2 , ⁇ T 3 , ⁇ T 4 ) for ensuring the deactivation of the transistors TR 1 , TR 2 , TR 3 , TR 4 are obtained through a simple circuit configuration.
  • the timing adjustment circuit 20 generates control clock signals ⁇ T 1 , ⁇ T 2 , ⁇ T 3 , ⁇ T 4 , which prevent the switching transistors TR 1 , TR 2 , TR 3 , TR 4 from being activated simultaneously This prevents a large through current from flowing through the transistors TR 1 , TR 2 , TR 3 , TR 4 .
  • the reliability of the transistors TR 1 , TR 2 , TR 3 , TR 4 increases, and power consumption of the charge pump circuits decreases.
  • the threshold voltage Vth of the switching transistors TR 1 , TR 2 , TR 3 , TR 4 does not affect voltage conversion. Thus, the voltage conversion obtains a high conversion voltage value (absolute value).
  • a charge pump circuit 53 according to a third embodiment of the present invention will now be described centering on parts differing from the charge pump circuit 51 of the first embodiment.
  • the charge pump circuit 51 of the first embodiment is provided with the buffer circuit B 1 , which delays the control clock signal ⁇ T 1 by a predetermined time to generate the capacitor clock ⁇ C 1 .
  • the buffer circuit 51 changes the source voltage (voltage at node N 1 ) Vn 1 after the gate voltage of the switching transistor TR 1 is determined. This avoids the influence of parasitic transistor on the transistor TR 1 .
  • the step-up conversion efficiency of the charge pump circuit decreases. Since the output signal of the buffer circuit B 1 is the input signal of the capacitor C 1 , the drive power of the MOS transistor in the second inverter of the buffer circuit B 1 is especially set to be large. Thus, the power consumption of the MOS transistor is large, and the decrease in the step-up conversion efficiency of the charge pump circuit cannot be ignored.
  • the buffer circuit (delay circuit) of the charge pump circuit 53 of the third embodiment is configured in the following manner. Before the control clock signal ⁇ T 1 goes high, the feed line leading to the capacitor C 1 is set at a state of high impedance. After the control clock signal ⁇ T 1 goes high, the feed line is set at a high level.
  • FIG. 8 is a schematic circuit diagram of a charge pump circuit 53 according to a third embodiment of the present invention.
  • the charge pump circuit 53 includes a timing adjustment circuit 100 for adjusting the clock signal provided to two switching transistors TR 1 , TR 2 , a capacitor C 1 , an output capacitor Cout, and transistors TR 1 , TR 2 .
  • the charge pump circuit 53 has a buffer circuit (delay circuit) 110 .
  • the buffer circuit 110 includes a p-channel MOS transistor 111 , which controls the connection between the capacitor C 1 and a power supply terminal 112 provided with the power supply voltage VDD, and an n-channel MOS transistor 113 , which controls the connection between a capacitor C 2 and a ground terminal 114
  • the buffer circuit 110 further includes an AND circuit 115 , a NOR circuit 116 , and an inverter 117 .
  • the buffer circuit 110 After the transistor TR 1 goes on and until the signal received by the capacitor C 1 goes high, the buffer circuit 110 generates control signals of the transistors 111 , 113 as described below to reduce power consumption.
  • the timing adjustment control circuit 100 provides the buffer circuit 110 with an instruction signal that causes the control clock signal ⁇ T 1 to go high. Based on the instruction signal, the buffer circuit 110 generates a deactivation control signal for deactivating the transistor 113 and causes the control clock signal ⁇ T 1 to go high based on the deactivation control signal. Further, the buffer circuit 110 generates an activation control signal for activating the transistor 111 based on the high control clock signal ⁇ T 1 .
  • the AND circuit 115 of the buffer circuit 110 performs an AND logic operation with a control clock signal CSG, which is provided from the timing adjustment circuit 100 , and a control signal S 111 , which is provided to the gate of the transistor 111 , to generate a control signal S 113 .
  • the control signal S 113 is provided to the gate of the transistor 113 .
  • a NOR circuit 116 of the buffer circuit 110 performs a NOR logic operation with the control signal CSG and the output signal of the AND circuit 115 to generate the control clock signal ⁇ T 1 .
  • the control signal ⁇ T 1 is provided to the gate of the transistor TR 1 .
  • An inverter 117 of the buffer circuit 110 inverts the output signal of the NOR circuit 116 to generate the control signal S 111 and provides the control signal S 111 to the gate of the transistor 111 .
  • the buffer circuit 110 Before the clock signal ⁇ T 1 , which is provided to the gate of the transistor TR 1 , goes high, the buffer circuit 110 maintains the transistor 113 in a deactivated state and sets the feed line of the capacitor C 1 in a high impedance state. Then, after the clock signal ⁇ T 1 goes high, the transistor 111 is activated and the feed line of the capacitor C 1 is provided with a high voltage.
  • the timing adjustment circuit 100 receives the clock signal CLK to generate clock signals for preventing the transistors TR 1 , TR 2 from simultaneously going on.
  • the timing adjustment circuit 100 causes the control clock signal ⁇ T 2 to go low in accordance with the logic level of the clock signal CLK and generates the control clock signal CSG to instruct the buffer circuit 110 to generate the high control clock signal ⁇ T 1 .
  • the timing adjustment circuit 100 provides the control clock signal CSG, which instructs the buffer circuit 110 to generate the low control clock signal ⁇ T 1 , to the buffer circuit 110 and generates the high control clock signal ⁇ T 2 based on the control clock signal CSG.
  • the timing adjustment circuit 100 includes a first inverter 101 , which inverts the clock signal CLK, and an AND circuit 102 .
  • the AND circuit 102 provides the gate of the transistor TR 2 with an AND logic signal based on the control signal S 113 , which is provided to the gate of the transistor 113 , and an output signal of the first inverter 101 .
  • the timing adjustment circuit 100 includes a second inverter 103 , which inverts the AND logic signal provided to the gate of the transistor TR 2 , and a NAND circuit 104 .
  • the NAND circuit 104 provides the buffer circuit 110 with the control clock signal CSG, which is a NAND logic signal based on the output signal of the second inverter 103 and the clock signal CLK.
  • the buffer circuit 110 generates the control clock signal ⁇ T 1 based on the control clock signal CSG.
  • the circuit configuration of FIG. 8 does not set the value of the negative voltage as the low level voltage value of the control clock signals ⁇ T 1 , ⁇ T 2 .
  • low potential power supply terminals, which are supposed to be grounded, of the AND circuit 115 and the NOR circuit 116 may be connected to the sources of the transistors TR 1 , TR 2 .
  • the operation of the charge pump circuit 53 when configured in such manner will now be described.
  • FIG. 9 is a combined timing and waveform chart illustrating the operation of the charge pump circuit 53 .
  • the AND circuit 102 provides the gate of the transistor TR 2 with the control clock signal ⁇ T 2 at the low level ( ⁇ VDD). This deactivates the transistor TR 2 .
  • the second inverter 103 inverts the control clock signal ⁇ T 2 and provides the inverted clock signal to a first input terminal of the NAND circuit 104 .
  • the clock signal CLK received by a second input terminal of the NAND circuit 104 goes high. In this state, the NAND circuit 104 provides the buffer circuit 110 with the control clock signal CSG at a low level.
  • a first input terminal of the AND circuit 115 of the buffer circuit 110 receives the low control clock signal CSG.
  • the AND circuit 115 provides the gate of the transistor 113 with the control signal S 113 at a low level. Further, the low control signal S 113 is provided to a first input terminal of the NOR circuit 116 .
  • a second input terminal of the NOR circuit 116 receives the control clock signal CSG from the timing adjustment circuit 100 .
  • the NOR circuit 116 provides the gate of the transistor TR 1 with the high control clock signal ⁇ T 1 . This activates the transistor TR 1 .
  • the transistor 113 goes off before the gate of the transistor TR 1 receives the high control clock signal ⁇ T 1 . This prevents the flow of unnecessary current between the capacitor C 1 and the ground terminal 114 that would occur when the potential at the capacitor C 1 changes due to activation of the transistor TR 1 .
  • the inverter 117 inverts the high control clock signal ⁇ T 1 and provides the gate of the transistor 111 with the control signal S 111 at a low level.
  • the transistor 111 is activated. This fixes the potential of the capacitor C 1 at a high level. Further, the potential at node N 1 , which starts to increase at time t 4 , is fixed at the ground level.
  • the control clock signal CSG goes high. This causes the buffer circuit 110 to output the control clock signal ⁇ T 1 at a low level and deactivates the transistor TR 1 . Further, the inverter 117 inverts the control clock signal ⁇ T 1 and provides the gate of the transistor 111 with the high control signal S 111 .
  • a second input terminal of the AND circuit 115 receives the control signal S 111 .
  • the AND circuit 115 performs an AND logic operation based on the high control signal S 111 and the high control clock signal CSG and generates the control signal S 113 at a high level.
  • the AND circuit 115 provides the high control signal S 113 to the gate of the transistor 113 and a second input terminal of the AND circuit 102 .
  • the AND circuit 102 performs an AND logic operation based on the high control signal S 113 and the high clock signal CLK and generates the control clock signal ⁇ T 2 at a high level.
  • the gate of the transistor TR 2 receives the high control clock signal ⁇ T 2 . This activates the transistor TR 2 , and the transistor TR 2 outputs the node voltage Vn 1 as the output voltage Vout.
  • the charge pump circuit 53 repeats such operations and maintains the step-up efficiency in an optimal manner.
  • the charge pump circuit 53 of the third embodiment has the advantages described below.
  • the transistor TR 1 is activated after the transistor 113 of the buffer circuit 110 is deactivated. Thus, power is not consumed between the capacitor C 1 and the ground terminal 114 from when the transistor TR 1 goes on to when the capacitor clock signal ⁇ C 1 goes high.
  • the transistor 111 goes on after the transistor 113 goes off. Further, the transistor 113 goes on after the transistor 111 goes off. This prevents through current from flowing between the transistors 113 , 111 .
  • a charge pump circuit 54 according to a fourth embodiment of the present invention will now be described centering on parts differing from the charge pump circuit 52 of the second embodiment and the charge pump circuit 53 of the third embodiment.
  • FIG. 10 is a schematic circuit diagram of the charge pump circuit 54 of the fourth embodiment.
  • the charge pump circuit 54 includes four switching transistors TR 1 , TR 2 , TR 3 , TR 4 and three capacitors C 1 , C 2 , C 3 and converts the power supply voltage VDD to negative voltage ⁇ 3VDD (logic value).
  • the charge pump circuit 54 has a timing adjustment circuit 200 to prevent adjacent transistors TR 1 –TR 4 from being simultaneously activated.
  • the charge pump circuit 54 includes buffer circuits 210 , 220 in lieu of the buffer circuits B 1 –B 3 of the second embodiment to avoid the influence of a parasitic transistor.
  • the buffer circuits 210 generates control clock signals ⁇ T 1 , ⁇ T 3 and delays the control clock signals ⁇ T 1 , ⁇ T 3 by a predetermined time to generate capacitor clock signals ⁇ C 1 , ⁇ C 3 .
  • the buffer circuits 220 generates control clock signals ⁇ T 2 , ⁇ T 4 and delays the control clock signals ⁇ T 2 , ⁇ T 4 by a predetermined time to generate capacitor clock signals ⁇ C 2 , ⁇ C 4 .
  • the buffer circuits 210 , 220 prevent the consumption of power between the capacitors C 1 –C 3 and the ground.
  • the buffer circuits 210 , 220 cause control signals S 213 , S 223 to go low and deactivate transistors 213 , 223 based on signals provided from the timing adjustment circuit 200 .
  • the buffer circuits 210 , 220 cause the control clock signals ⁇ T 1 – ⁇ T 4 to go high based on the low control signals S 213 , S 223 and provide the high control clock signals ⁇ T 1 – ⁇ T 4 to the gates of the switching transistors TR 1 –TR 4 , respectively.
  • the high control clock signals ⁇ T 1 – ⁇ T 4 activate the transistors 211 , 221 . This supplies the capacitors C 1 –C 3 with power supply voltage via high potential terminals 212 , 222 .
  • the buffer circuits 210 , 220 include AND circuits 215 , 225 , NOR circuits 216 , 226 , and inverters 217 , 227 , respectively.
  • the timing adjustment circuit 200 generates clock signals to prevent two adjacent switching transistors TR 1 –TR 4 from going on simultaneously and provides the clock signals to the buffer circuits 210 , 220 .
  • the timing adjustment circuit 200 provides the buffer circuit 220 with a clock signal so that the buffer circuit 220 generates the control clock signals ⁇ T 2 , ⁇ T 4 at a high level based on the low control clock signals ⁇ T 1 , ⁇ T 3 .
  • the timing adjustment circuit 200 provides the buffer circuit 210 with a clock signal so that the buffer circuit 210 generates the control clock signals ⁇ T 1 , ⁇ T 3 at a high level based on the low control clock signals ⁇ T 2 , ⁇ T 4 .
  • the timing adjustment circuit 200 includes an inverter 201 , a first NAND circuit 202 , and a second NAND circuit 203 .
  • the first NAND circuit 202 provides the buffer circuit 210 with a NAND logic signal based on the clock signal CLK and the signal received by the gate of the transistor 223 of the buffer circuit 220 .
  • the second NAND circuit 203 provides the buffer circuit 220 with a logical NAND signal based on the clock signal CLK, which is obtained via the inverter, and the signal received by the gate of the transistor 213 of the buffer circuit 210 .
  • the negative voltage is set as the low voltage value of the control clock signals ⁇ T 1 – ⁇ T 4 .
  • FIG. 11 is a combined timing and waveform chart illustrating the operation of the charge pump circuit 54 of the fourth embodiment.
  • the charge pump circuit 54 of the fourth embodiment basically functions in the same manner as the charge pump circuit 53 of the third embodiment.
  • the timing signals are generated so that power is not consumed between the capacitors C 1 –C 3 and the ground terminals 214 , 224 during the delay period from when the switching transistors TR 1 –TR 4 go on to when the capacitor clocks ⁇ C 1 – ⁇ C 3 go high.
  • the transistors 211 , 221 go off, the transistors 213 , 223 go on. Thus, through current does not flow between the transistors 211 , 221 and 213 , 223 .
  • the buffer circuits are not limited to the configurations illustrated in FIGS. 8 and 10 . Especially, the combination of AND and NOR circuits may be changed as required.
  • the buffer circuit may be provided with a first logic circuit and a second logic circuit.
  • the first logic circuit receives an output signal of the second logic circuit and an input signal of the buffer circuit. Based on the received signals, the two logic circuits set the time period during which two transistors connected between two power sources are simultaneously deactivated and applies a predetermined potential to capacitors after the time period elapses.
  • a buffer circuit having this function may be used.
  • the timing adjustment circuit adjusts the timing of clock signals to prevent inverted clock signals from simultaneously activating different switching transistors. Accordingly, a circuit having such function may be employed in the present invention,
  • the switching transistors TR 1 –TR 4 may be configured by p-channel MOS transistors. Alternatively, the switching transistors may be configured by n-channel and p-channel MOS transistors.
  • a charge pump circuit may perform various voltage conversions, such as step-up of the power supply voltage VDD or generation of a positive voltage with the negative voltage.
  • the number of switching transistors and the number of capacitors (pumping capacitors) is not limited and may be changed to obtain the desired output voltage.
  • the capacitor clock signals ⁇ C 1 , ⁇ C 2 may be set at two different potentials like the clock signal applied to the conductive control terminals of the switching transistors. By changing the two potentials, the step-up capability of the change pump circuit is adjusted.

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US09/776,011 2000-02-04 2001-02-02 Charge pump circuit Expired - Lifetime US6970035B2 (en)

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US20050105364A1 (en) * 2003-11-19 2005-05-19 Sanyo Electric Co., Ltd. Amplifier for amplifying input signal such as video signal and outputting amplified signal
US20060082409A1 (en) * 2004-10-19 2006-04-20 Taku Kobayashi Step-down voltage output circuit
US20060152273A1 (en) * 2005-01-11 2006-07-13 Stmicroelectronics S.R.I. Single-stage and modular multi-stage clock-booster
US20070002655A1 (en) * 2005-06-29 2007-01-04 Hynix Semiconductor Inc. Voltage Pumping Device
US20070273431A1 (en) * 2006-02-22 2007-11-29 Seiko Instruments Inc. Charge pump-type booster circuit
US7518431B2 (en) 2004-09-28 2009-04-14 Panasonic Corporation Semiconductor integrated circuit for processing audio and video signals
US20090128228A1 (en) * 2007-11-16 2009-05-21 Cheng-Chung Yeh Charge Pump Capable of Enhancing Power Efficiency and Output Voltage
US20100085111A1 (en) * 2008-10-07 2010-04-08 Nec Electronics Corporation Charge pump-type voltage booster circuit and semiconductor integrated circuit device
US20100193798A1 (en) * 2003-03-26 2010-08-05 Semiconductor Energy Laboratory Co., Ltd. Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
US20130328597A1 (en) * 2012-06-08 2013-12-12 Qualcomm Incorporated Negative voltage generators
US9112406B2 (en) * 2013-10-11 2015-08-18 Dialog Semiconductor Gmbh High efficiency charge pump circuit

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US6661278B1 (en) * 2002-07-08 2003-12-09 Impinj, Inc. High voltage charge pump circuit
JP2006129127A (ja) * 2004-10-29 2006-05-18 Olympus Corp 電圧供給回路及びそれを用いた固体撮像装置
JP2006203747A (ja) * 2005-01-24 2006-08-03 Sanyo Electric Co Ltd チャージポンプ回路
JP2007129828A (ja) * 2005-11-04 2007-05-24 Sanyo Electric Co Ltd チャージポンプ回路
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US8710900B2 (en) * 2012-03-22 2014-04-29 Fairchild Semiconductor Corporation Methods and apparatus for voltage selection for a MOSFET switch device
US9491151B2 (en) * 2015-01-07 2016-11-08 Ememory Technology Inc. Memory apparatus, charge pump circuit and voltage pumping method thereof
CN107481745B (zh) * 2016-06-07 2020-08-18 中芯国际集成电路制造(上海)有限公司 一种负升压电路、半导体器件及电子装置

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US8952455B2 (en) 2003-03-26 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
US8026551B2 (en) * 2003-03-26 2011-09-27 Semiconductor Energy Laboratory Co., Ltd. Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
US20100193798A1 (en) * 2003-03-26 2010-08-05 Semiconductor Energy Laboratory Co., Ltd. Source follower circuit or bootstrap circuit, driver circuit comprising such circuit, and display device comprising such driver circuit
US7423698B2 (en) 2003-11-19 2008-09-09 Sanyo Electric Co., Ltd. Amplifier for amplifying input signal such as video signal and outputting amplified signal
US20050105364A1 (en) * 2003-11-19 2005-05-19 Sanyo Electric Co., Ltd. Amplifier for amplifying input signal such as video signal and outputting amplified signal
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US20060152273A1 (en) * 2005-01-11 2006-07-13 Stmicroelectronics S.R.I. Single-stage and modular multi-stage clock-booster
US7095268B2 (en) * 2005-01-11 2006-08-22 Stmicroelectronics S.R.L. Single-stage and modular multi-stage clock-booster
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US7427891B2 (en) * 2006-02-22 2008-09-23 Seiko Instruments Inc. Charge pump-type booster circuit
US20070273431A1 (en) * 2006-02-22 2007-11-29 Seiko Instruments Inc. Charge pump-type booster circuit
US20090128228A1 (en) * 2007-11-16 2009-05-21 Cheng-Chung Yeh Charge Pump Capable of Enhancing Power Efficiency and Output Voltage
US7626446B2 (en) * 2007-11-16 2009-12-01 Sitronix Technology Corp. Charge pump capable of enhancing power efficiency and output voltage
US20100085111A1 (en) * 2008-10-07 2010-04-08 Nec Electronics Corporation Charge pump-type voltage booster circuit and semiconductor integrated circuit device
US8072257B2 (en) * 2008-10-07 2011-12-06 Renesas Electronics Corporation Charge pump-type voltage booster circuit and semiconductor integrated circuit device
US20130328597A1 (en) * 2012-06-08 2013-12-12 Qualcomm Incorporated Negative voltage generators
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US9112406B2 (en) * 2013-10-11 2015-08-18 Dialog Semiconductor Gmbh High efficiency charge pump circuit

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KR20010078330A (ko) 2001-08-20
JP3702166B2 (ja) 2005-10-05
KR100381489B1 (ko) 2003-04-26
TW541449B (en) 2003-07-11
US20010011919A1 (en) 2001-08-09
JP2001292563A (ja) 2001-10-19

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