US6737870B2 - Capacitance measurement method - Google Patents

Capacitance measurement method Download PDF

Info

Publication number
US6737870B2
US6737870B2 US10/287,537 US28753702A US6737870B2 US 6737870 B2 US6737870 B2 US 6737870B2 US 28753702 A US28753702 A US 28753702A US 6737870 B2 US6737870 B2 US 6737870B2
Authority
US
United States
Prior art keywords
capacitance
current
gate potential
measured
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US10/287,537
Other languages
English (en)
Other versions
US20030227291A1 (en
Inventor
Takeshi Okagaki
Motoaki Tanizawa
Tatsuya Kunikiyo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUNIKIYO, TATSUYA, OKAGAKI, TAKESHI, TANIZAWA, MOTOAKI
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
Publication of US20030227291A1 publication Critical patent/US20030227291A1/en
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
Application granted granted Critical
Publication of US6737870B2 publication Critical patent/US6737870B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance

Definitions

  • the present invention relates to a capacitance measurement method using a CBCM (Charge Based Capacitance Measurement) circuit.
  • CBCM Charge Based Capacitance Measurement
  • a CBCM technique is a method for measuring capacitance values on a sub-fF level ( ⁇ 10 ⁇ 15 F) that cannot be measured with sufficient accuracy by AC measurement equipment such as an LCR meter.
  • FIG. 7 is a circuit diagram illustrating a configuration of a CBCM circuit adopting a conventional CBCM technique.
  • a PMOS transistor MP 1 and an NMOS transistor MN 1 are connected in series, and a PMOS transistor MP 2 and an NMOS transistor MN 2 are connected in series.
  • the source of the PMOS transistor MP 1 is connected to a power pad 52
  • the source of the PMOS transistor MP 2 is connected to a power pad 54
  • the sources of the NMOS transistors MN 1 and MN 2 are connected in common to ground level.
  • a PMOS gate potential Gp is applied to the gates of the PMOS transistors MP 1 and MP 2
  • an NMOS gate potential Gn is applied to the gates of the NMOS transistors MN 1 and MN 2 .
  • the purpose of the CBCM circuit shown in FIG. 7 is to measure the target capacitance C t .
  • FIG. 8 is a timing chart illustrating the operation of the CBCM circuit shown in FIG. 7 .
  • capacitance measurement by the conventional CBCM circuit will be described.
  • input voltage waveforms of the PMOS gate potential Gp and the NMOS gate potential Gn are such that at least either the NMOS transistors MN 1 , MN 2 or the PMOS transistors MP 1 , MP 2 are in the off state at any given time.
  • no short circuit current flows from the PMOS transistor MP 1 to the NMOS transistor MN 1 or from the PMOS transistor MP 2 to the NMOS transistor MN 2 .
  • the PMOS transistors MP 1 and MP 2 are turned on to supply currents I r and I t from the power pads 52 and 54 and thereby to charge the reference capacitance C ref and the test capacitance C tst .
  • the NMOS transistors MN 1 and MN 2 are both in the off state and thus, potentials at the nodes N 1 and N 2 which are connected respectively to the reference capacitance C ref and the test capacitance C tst reach a power supply potential V dd .
  • the PMOS transistors MP 1 , MP 2 and the NMOS transistors MN 1 , MN 2 are all in the off state.
  • the accumulated charges on the reference capacitance C ref and the test capacitance C tst should be stored and the nodes N 1 and N 2 should be maintained at the power supply potential V dd .
  • the reference capacitance C ref and the test capacitance C tst should be maintained at the ground potential V ss since the completion of discharge.
  • the advantage of the CBCM technique is that, as expressed in Equations (1) and (2), the dummy capacitance (parasitic capacitance) C m can be cancelled and a desired target capacitance C t can be obtained.
  • the CBCM technique allows measurement of capacitance values.
  • the amount of charging current e.g., 1% or more as a current value
  • FIG. 9 is a circuit diagram showing an equivalent circuit on the side of the test capacitance C tst , where there is no leakage current. As shown, if there is no leakage current, the circuit configuration is equivalent to that in which the test capacitance C tst and a resistance R s (such as a transistor's resistance) are connected in series.
  • R s such as a transistor's resistance
  • FIG. 10 is a circuit diagram showing an equivalent circuit on the side of the test capacitance C tst , where there is a leakage current. As shown, if there is a leakage current, the circuit configuration is such that a resistance R t is additionally connected parallel to the test capacitance C tst .
  • FIG. 11 is a circuit diagram showing an equivalent circuit of the CBCM circuit when there is a leakage current.
  • the circuit configuration shown in FIG. 10 is connected between drain and source of the NMOS transistor MN 2 , and the current I t supplied from the power pad 54 flows as a current IC t through the test capacitance C tst and flows as a current IR t through the resistance R t .
  • FIG. 12 is an explanatory diagram for indicating a problem of the leakage current. As shown, even during the period in which the PMOS transistor MP 1 is in the on state with the application of the PMOS gate potential Gp (i.e., during the period in which the NMOS transistor MN 1 should be in the off state), the current IR t will flow as a leakage current.
  • Capacitance measurement (extraction) using the conventional CBCM technique assumes that currents observed on the side of power supply potential V dd are all used for charging the MOS transistors forming the CBCM circuit, the test capacitance C tst , and the dummy capacitance C m . Thus, if there is a leakage current, even a charge which actually corresponds to a leakage current flowing through the resistance R t is treated as an accumulated charge, which causes a problem that the measured capacitance value may become larger than the actual capacitance value.
  • An object of the present invention is to provide a capacitance measurement method which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured.
  • the capacitance measurement method is for measuring a capacitance to be measured which is connected to a CBCM (Charge Based Capacitance Measurement) circuit including a charge transistor, and includes the following steps (a) to (e).
  • the step (a) is to apply to the charge transistor a first control signal for controlling turning on/off of the charge transistor in a predetermined cycle, thereby to measure an amount of first test current to be supplied through the charge transistor to the capacitance to be measured.
  • the step (b) is to apply to the charge transistor a second control signal for controlling turning on/off of the charge transistor in the predetermined cycle, thereby to measure an amount of second test current to be supplied through the charge transistor to the capacitance to be measured.
  • a period during which the second control signal indicates an on state of the charge transistor is set to be predetermined times longer than that during which the first control signal indicates an on state of the charge transistor.
  • the step (c) is to, based on the first and second test currents, eliminate a leakage current occurring incident to the capacitance to be measured and calculate an amount of capacity current used only for charging the capacitance to be measured.
  • the step (d) is to calculate a charge frequency suitable for the amount of capacity current.
  • the step (e) is to calculate a capacitance value of the capacitance to be measured based on the amount of capacity current and the charge frequency.
  • the amounts of the first and second test currents measured by the execution of the above steps (a) and (b) each are equal to the sum of the amounts of capacity current and leakage current.
  • the second test current has the same amount of capacity current as the first test current, but has a predetermined times larger amount of leakage current.
  • step (c) the amount of the first test current is increased by the predetermined times and operations such as obtaining a difference from the amount of the second test current is performed, whereby an accurate amount of capacity current used only for charging the capacitance to be measured can be calculated. Consequently, by the execution of the subsequent steps (d) and (e), it is possible to calculate an accurate capacitance value of the capacitance to be measured, from which a leakage current occurring incident to the capacitance to be measured has been eliminated.
  • FIG. 1 is a flow chart showing a sequence of processing in a capacitance measurement method according to a preferred embodiment of the present invention
  • FIG. 2 is a waveform diagram illustrating signal waveforms of PMOS gate potentials
  • FIG. 3 is a waveform diagram illustrating a detailed example of signals of the PMOS gate potentials
  • FIG. 4 is a waveform diagram illustrating simulation results of capacity current and leakage current in part of FIG. 3;
  • FIG. 5 is a waveform diagram illustrating a detailed example of signals of the PMOS gate potentials
  • FIG. 6 is a waveform diagram illustrating simulation results of leakage current in part of FIG. 5;
  • FIG. 7 is a circuit diagram illustrating a configuration of a CBCM circuit adopting a conventional CBCM technique
  • FIG. 8 is a timing chart showing the operation of the CBCM circuit shown in FIG. 7;
  • FIG. 9 is a circuit diagram showing an equivalent circuit on the side of a test capacitance, where there is no leakage current
  • FIG. 10 is a circuit diagram showing an equivalent circuit on the side of the test capacitance, where there is a leakage current
  • FIG. 11 is a circuit diagram showing an equivalent circuit of the CBCM circuit when there is a leakage current.
  • FIG. 12 is an explanatory diagram for indicating a problem of the leakage current.
  • FIG. 1 is a flow chart showing a sequence of processing in a capacitance measurement method according to a preferred embodiment of the present invention.
  • a CBCM circuit has a similar circuit configuration to those shown in FIGS. 7 and 11.
  • a test current IC norm which corresponds to the current I c in Equation (1) is measured by using a normal PMOS gate potential Gp 1 as the PMOS gate potential Gp for providing on/off control of the PMOS transistors MP 1 and MP 2 in a predetermined cycle.
  • a test current IC rat which corresponds to the current I c in Equation (1) is measured by using, as the PMOS gate potential Gp, a multiplied on-time PMOS gate potential Gp 2 , the “L” period and fall time of which are integral multiples of those of the normal PMOS gate potential Gp 1 . Accordingly, both the currents IC norm and IC rat are currents from which the current I r for charging the dummy capacitance C m has been eliminated.
  • FIG. 2 is a waveform diagram illustrating the normal PMOS gate potential Gp 1 and the multiplied on-time PMOS gate potential Gp 2 .
  • the normal PMOS gate potential Gp 1 has a normally used PMOS on time PW (“L” period”) and fall time TF (turn-on transition time).
  • L is the operating voltage of the MOS transistors in the CBCM circuit.
  • the multiplied on-time PMOS gate potential Gp 2 has the same turn-on/off cycle of the PMOS transistors MP 1 and MP 2 as the normal PMOS gate potential Gp 1 , but has a different duty cycle and slew rate.
  • the multiplied on-time PMOS gate potential Gp 2 has a PMOS on time (PW ⁇ rat) which is an integral multiple of the PMOS on time PW of the normal PMOS gate potential Gp 1 , and has a fall time (TF ⁇ rat) which is an integral multiple of the fall time TF, where rat is the integer multiplication factor.
  • PW ⁇ rat PMOS on time
  • TF ⁇ rat fall time
  • the rise times (turn-off transition times) of the normal PMOS gate potential Gp 1 and the multiplied on-time PMOS gate potential Gp 2 are set short enough as compared with the fall time TF. Thereby, an error due to discharge occurring in the target capacitance such as a gate capacitance of the PMOS transistor can be minimized.
  • FIG. 3 is a waveform diagram illustrating a detailed example of signals of the normal PMOS gate potential Gp 1 and the multiplied on-time PMOS gate potential Gp 2 .
  • FIG. 4 is a waveform diagram illustrating simulation results of the currents IC t and IR t in a region A 1 of FIG. 3 .
  • the integer multiplication factor rat is “2”.
  • the current IC t flows only momentarily for charging the test capacitance C tst and thus, no difference in the amount of charge occurs between the normal PMOS gate potential Gp 1 and the multiplied on-time PMOS gate potential Gp 2 .
  • FIG. 5 is a waveform diagram illustrating a detailed example of signals of the normal PMOS gate potential Gp 1 and the multiplied on-time PMOS gate potential Gp 2 .
  • FIG. 6 is a waveform diagram illustrating simulation results of the leakage current IR t in a region A 2 of FIG. 5, which is plotted in arbitrary units (a.u.) using the integer multiplication factor rat.
  • the integer multiplication factor rat is “2”.
  • the value of leakage current IR t for the normal PMOS gate potential Gp 1 matches that for the multiplied on-time PMOS gate potential Gp 2 .
  • the amount of leakage current IR t when the multiplied on-time PMOS gate potential Gp 2 is applied, at which time a period in which the leakage current IR t flows is rat times longer can be measured to be rat times larger than that when the normal PMOS gate potential Gp 1 is applied, where rat is the integer multiplication factor.
  • FIGS. 3 to 6 show that, for the multiplied on-time PMOS gate potential Gp 2 , as compared with the normal PMOS gate potential Gp 1 , the amount of leakage current charge IR t per unit time (i.e., the average current value with respect to time) is multiplied by the integer multiplication factor rat, but the amount of current charge IC t per unit time remains unchanged.
  • step S 3 based on the currents IC norm and IC rat , the leakage current IR t is eliminated and the amount of capacity current CIC consisting only of a capacity current component IC t is calculated, using the following equation (3).
  • the capacity current CIC obtained from Equation (3) is a current from which a leakage current component has been completely eliminated.
  • step S 4 a charge frequency f rat is calculated. Since the currents IC norm and IC rat have the same value of current IC t , the amount of current corresponding to (rat ⁇ 1) ⁇ IC t is calculated as the capacity current CIC by solving Equation (3) in step S 3 . This is equivalent to (rat ⁇ 1) charging; thus, the charge frequency f rat can be obtained from the following equation (4).
  • step S 5 based on the capacity current CIC and the charge frequency f rat , a target capacitance CC t is obtained from the following equation (5).
  • the target capacitance is obtained by the capacitance measurement method according to the preferred embodiment.
  • the resultant target capacitance CC t is 102 fF, which can fall within 2% error.
  • the target capacitance C t (CC t ), the resistance R s and the resistance R t described above are respectively a target capacitance C t and a resistance R s which are extracted from a MOSFET with an insulation film thickness of 1.6 nm (a value measured by ellipsometry) by using an already-existing two-frequency plan, and a resistance R t which is about one tenth of the extracted value (at which value the leakage current is likely to occur).
  • the target capacitance C t obtained in a similar manner by the conventional capacitance measurement method according to Equations (1) and (2) is 1.4 pF, the error of which is 1400%.
  • the capacitance measurement method can, by solving Equation (3) in step S 3 , accurately calculate the amount of capacity current CIC used only for charging the test capacitance C tst .
  • the signal waveform of the NMOS gate potential Gn is set to have a duty cycle and slew rate that are sufficient to cause discharge regardless of whether the PMOS gate potential Gp is the normal PMOS gate potential Gp 1 or the multiplied on-time PMOS gate potential Gp 2 .
  • the waveform of the NMOS gate potential Gn may be changed depending on whether the PMOS gate potential Gp is the normal PMOS gate potential Gp 1 or the multiplied on-time PMOS gate potential Gp 2 .

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
US10/287,537 2002-06-07 2002-11-05 Capacitance measurement method Expired - Fee Related US6737870B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002-166880 2002-06-07
JP2002166880A JP2004012321A (ja) 2002-06-07 2002-06-07 容量値測定方法

Publications (2)

Publication Number Publication Date
US20030227291A1 US20030227291A1 (en) 2003-12-11
US6737870B2 true US6737870B2 (en) 2004-05-18

Family

ID=29706736

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/287,537 Expired - Fee Related US6737870B2 (en) 2002-06-07 2002-11-05 Capacitance measurement method

Country Status (6)

Country Link
US (1) US6737870B2 (ja)
JP (1) JP2004012321A (ja)
KR (1) KR20030095174A (ja)
CN (1) CN1467807A (ja)
DE (1) DE10305380A1 (ja)
TW (1) TW561570B (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090102504A1 (en) * 2005-11-24 2009-04-23 Klaus Voigtlaender Circuit Assemblage and Method for Functional Checking of a Power Transistor
US9086450B2 (en) 2010-10-04 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for measuring capacitances of capacitors
US9952268B1 (en) * 2015-09-17 2018-04-24 Pdf Solutions, Inc. Method for accurate measurement of leaky capacitors using charge based capacitance measurements

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI306950B (en) * 2006-11-06 2009-03-01 Macronix Int Co Ltd Method for measuring intrinsic capacitances of a mos device
US20110157070A1 (en) * 2009-12-31 2011-06-30 Silicon Laboratories Inc. System and method for configuring capacitive sensing speed
TWI381173B (zh) * 2008-10-29 2013-01-01 Raydium Semiconductor Corp 電容量測電路及其電容量測方法
CN103472311A (zh) * 2013-09-13 2013-12-25 上海集成电路研发中心有限公司 测量小电容失配特性的测试结构和方法
CN103675468A (zh) * 2013-12-26 2014-03-26 天津市松正电动汽车技术股份有限公司 一种动态检测超级电容容值的方法
CN107991543B (zh) * 2017-12-18 2024-03-26 深圳芯能半导体技术有限公司 绝缘栅双极型晶体管的栅极电荷量测量电路及其测量方法
CN111562464B (zh) * 2020-05-12 2022-04-08 国网山东省电力公司电力科学研究院 中性点不接地系统的参数在线测试方法、存储介质及装置
CN112557862A (zh) * 2020-11-26 2021-03-26 徐州天力电子科技有限公司 一种具有检测电源电容装置的控制器
KR102610205B1 (ko) * 2021-11-09 2023-12-06 테크위드유 주식회사 Mosfet의 누설 전류 제거 회로 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001338007A (ja) 2000-05-30 2001-12-07 Ricoh Co Ltd 回路シミュレーションのためのパラメータ抽出方法及びパラメータ抽出装置、並びに回路シミュレーションシステム
US20020101252A1 (en) * 2001-01-31 2002-08-01 National Science Council Structure for capacitance measurement
US20030098695A1 (en) * 2001-11-28 2003-05-29 Hsieh Tsung Hsuan Circuit and method for measuring capacitance

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3094246B2 (ja) * 1991-08-30 2000-10-03 豊 西村 静電容量測定法
JP2561040B2 (ja) * 1994-11-28 1996-12-04 日本電気株式会社 容量型センサの容量変化検出回路およびその検出方法
KR970045241U (ko) * 1995-12-29 1997-07-31 콘덴서의 전기적특성 측정장치
JPH101129A (ja) * 1996-06-14 1998-01-06 Fuji Photo Film Co Ltd 直方体状ケース
KR100735332B1 (ko) * 2000-09-28 2007-07-04 두산중공업 주식회사 전류 펄스폭을 이용한 전기 집진기용 정전용량 측정장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001338007A (ja) 2000-05-30 2001-12-07 Ricoh Co Ltd 回路シミュレーションのためのパラメータ抽出方法及びパラメータ抽出装置、並びに回路シミュレーションシステム
US20020101252A1 (en) * 2001-01-31 2002-08-01 National Science Council Structure for capacitance measurement
US20030098695A1 (en) * 2001-11-28 2003-05-29 Hsieh Tsung Hsuan Circuit and method for measuring capacitance

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
James C. Chen, et al., "An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique", IEEE, IEDM, 1996, pp. 69-72.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090102504A1 (en) * 2005-11-24 2009-04-23 Klaus Voigtlaender Circuit Assemblage and Method for Functional Checking of a Power Transistor
US7932724B2 (en) * 2005-11-24 2011-04-26 Robert Bosch Gmbh Circuit assemblage and method for functional checking of a power transistor
US9086450B2 (en) 2010-10-04 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for measuring capacitances of capacitors
US9952268B1 (en) * 2015-09-17 2018-04-24 Pdf Solutions, Inc. Method for accurate measurement of leaky capacitors using charge based capacitance measurements

Also Published As

Publication number Publication date
CN1467807A (zh) 2004-01-14
DE10305380A1 (de) 2003-12-24
JP2004012321A (ja) 2004-01-15
TW561570B (en) 2003-11-11
KR20030095174A (ko) 2003-12-18
US20030227291A1 (en) 2003-12-11

Similar Documents

Publication Publication Date Title
US6737870B2 (en) Capacitance measurement method
US6731179B2 (en) System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)
US20220343048A1 (en) Determination of unknown bias and device parameters of integrated circuits by measurement and simulation
US6066177A (en) Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library
US8099269B2 (en) Two-step simulation methodology for aging simulations
US7791357B2 (en) On silicon interconnect capacitance extraction
US6933731B2 (en) Method and system for determining transistor degradation mechanisms
US20090160477A1 (en) Method and test system for fast determination of parameter variation statistics
WO2005072163A2 (en) Electrostatic discharge simulation
US20060261840A1 (en) System and method for determining channel mobility
US6806762B2 (en) Circuit and method to facilitate threshold voltage extraction and facilitate operation of a capacitor multiplier
US6549029B1 (en) Circuit and method for measuring capacitance
US20130227330A1 (en) Analysing timing paths for circuits formed of standard cells
JPH05203698A (ja) Ｍｅｓｆｅｔの熱抵抗測定方法
US9952268B1 (en) Method for accurate measurement of leaky capacitors using charge based capacitance measurements
US6990420B2 (en) Method of estimating a local average crosstalk voltage for a variable voltage output resistance model
US20090043558A1 (en) Delay calculation method capable of calculating delay time with small margin of error
US7486086B2 (en) Method for measuring intrinsic capacitance of a metal oxide semiconductor (MOS) device
US7298160B2 (en) Method of measuring gate capacitance by correcting dissipation factor error
US20020171431A1 (en) Transmission line pulse method for measuring electrostatic discharge voltages
US20240036101A1 (en) Correcting for load resistance when making i-v measurements with constant drain voltage on power mosfets
Brut et al. New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors
JPH0927741A (ja) 論理回路チェック装置および方法
Bisdounis et al. Modeling the dynamic behavior of series-connected MOSFETs for delay analysis of multiple-input CMOS gates
US6813578B1 (en) Process for measuring CMOS device performance from hot carrier luminescence

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OKAGAKI, TAKESHI;TANIZAWA, MOTOAKI;KUNIKIYO, TATSUYA;REEL/FRAME:013460/0538

Effective date: 20021008

AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:014502/0289

Effective date: 20030908

AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MITSUBISHI DENKI KABUSHIKI KAISHA;REEL/FRAME:015185/0122

Effective date: 20030908

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20080518