US6429705B1 - Resetting circuit independent of a transistor's threshold - Google Patents

Resetting circuit independent of a transistor's threshold Download PDF

Info

Publication number
US6429705B1
US6429705B1 US09/820,714 US82071401A US6429705B1 US 6429705 B1 US6429705 B1 US 6429705B1 US 82071401 A US82071401 A US 82071401A US 6429705 B1 US6429705 B1 US 6429705B1
Authority
US
United States
Prior art keywords
transistor
voltage
circuit
transistors
reset signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/820,714
Other languages
English (en)
Other versions
US20020043994A1 (en
Inventor
Yoshihide Bando
Toshiya Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BANDO, YOSHIHIDE, UCHIDA, TOSHIYA
Publication of US20020043994A1 publication Critical patent/US20020043994A1/en
Application granted granted Critical
Publication of US6429705B1 publication Critical patent/US6429705B1/en
Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU LIMITED
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Assigned to SOCIONEXT INC. reassignment SOCIONEXT INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU SEMICONDUCTOR LIMITED
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches

Definitions

  • the present invention relates to a semiconductor device having a resetting circuit.
  • a semiconductor device such as a DRAM, includes a resetting circuit.
  • the resetting circuit When the power supply is turned on, the resetting circuit is operated to initialize an internal circuit, so that the semiconductor device is prevented from malfunctioning.
  • FIG. 1 shows an example of the resetting circuit implemented in the semiconductor device.
  • the resetting circuit has an nMOS transistor 2 , a voltage generating circuit 4 , a load circuit 6 , and a waveform shaping circuit 8 .
  • the nMOS transistor connects a gate electrode to a node ND 01 , connects a drain electrode to a node ND 02 , and connects a source electrode to a ground line VSS.
  • the voltage generating circuit 4 is formed such that resistors R 1 and R 2 are connected in series with each other with the node ND 01 between a power supply line VCC and the ground line VSS.
  • the load circuit 6 is formed such that an end of the load circuit 6 is connected to the power supply line VCC, and the other end of the load circuit 6 is connected to a resistor R 3 connected to the node ND 02 .
  • the waveform shaping circuit 8 has two inverters that are connected in series. In the waveform shaping circuit 8 , its input is connected to the node ND 02 , and a reset signal RST is output from its output.
  • This type of resetting circuit detects that a supply voltage VCC has risen to a predetermined value by utilizing the threshold voltage of a transistor (in this example, the nMOS transistor 2 ), and inactivates the reset signal RST.
  • FIG. 2 shows the operation of the resetting circuit mentioned above.
  • the operating voltage of semiconductor devices has become low, and, accordingly, a supply voltage VCC supplied from external sources has become low.
  • the ratio of the threshold voltage of a transistor to the supply voltage VCC is high since the threshold voltage of the transistor has almost no dependence on the supply voltage VCC.
  • the detection level of the supply voltage VCC of the resetting circuit greatly varies depending on a change in the threshold voltage, and the amount (T 2 in FIG. 2) of deviation in the inactivation timing of the reset signal RST with respect to a change in the threshold voltage becomes larger than that in the case where the operating voltage is high.
  • the threshold voltage of the transistor varies with the manufacturing conditions, the position of a chip on a wafer, and the position of the wafer in a production lot, of the semiconductor device, or depends on the temperature when the semiconductor device is operating.
  • a reset period T 1 is shortened if the inactivation timing of the reset signal RST deviates to an early-timing side. This case raises a fear that the internal circuit will not be normally initialized. In the worst case, a high-level period of the reset signal RST necessary to initialize the internal circuit will disappear. On the other hand, if the inactivation timing of the reset signal RST deviates to a late-timing side, there is a fear that the reset signal RST will not be inactivated (i.e., be always at a high level).
  • the aforementioned voltage generating circuit 4 is formed of many resistors and fuses, in order to deal with the deviation of the threshold voltage of the transistor at the time a semiconductor device is manufactured.
  • some of the resistors to be connected in series are selected by trimming the fuses, and a voltage generated in the node ND 01 is adjusted according to a threshold voltage.
  • the thus constructed voltage generating circuit has a disadvantage in that the chip size increases because a large layout area is required for the resistors and the fuses. Additionally, manufacturing costs increase because a step to trim the fuses is required.
  • An object of the present invention is to generate a reset signal which is not influenced by a change in the threshold voltage of a transistor.
  • the object is to reduce fluctuations in the inactivation timings of reset signals generated by a resetting circuit.
  • Another object of the present invention is to reliably initialize an internal circuit of a semiconductor device by the reset signal, and thereby prevent malfunctioning of the semiconductor device.
  • the resetting circuit includes a first transistor that receives a first voltage at a gate electrode and a second transistor that receives a second voltage at the gate electrode.
  • the second transistor is formed such that the ratio W/L (transistor size) of a gate width W to a channel length L is larger than the ratio W/L of the first transistor.
  • the first voltage rises in accordance with the rise of a supply voltage.
  • the second voltage rises in accordance with the rise of the supply voltage, and is lower than the first voltage.
  • the gate voltage (accurately, gate-to-source voltage) of the second transistor is always lower than the gate voltage of the first transistor.
  • the transistor size of the second transistor is larger than that of the first transistor. Therefore, the drain-to-source current (i.e., subthreshold current) of the second transistor is larger than the drain-to-source current of the first transistor for a while after the supply voltage is applied (i.e., while the supply voltage is low).
  • the drain-to-source current of the first transistor is equalized with the drain-to-source current of the second transistor at a predetermined supply voltage, and thereafter the drain-to-source current of the first transistor becomes larger than that of the second transistor. That is, an inversion occurs between the drain-to-source currents of the first and second transistors by the predetermined supply voltage.
  • the control circuit Since the control circuit generates the reset signal when the values of the drain-to-source currents cross, the reset signal can always be generated at the predetermined supply voltage, independent from the threshold voltage of the transistor.
  • the reset signal may be generated by, for example, the direct detection of a current value, and may be generated by utilizing a voltage generated in the drain electrode of the transistor.
  • the two transistors since the channel lengths L of the first and second transistors are equalized with each other, the two transistors maintain predetermined relative relations with each parameter in subthreshold characteristic during changes in each of the parameters. This results in a desired V-l characteristic to be easily realized.
  • the resetting circuit includes a load circuit.
  • the load circuit is connected to the drain electrode of the first transistor and to the drain electrode of the second transistor, and supplies an electric current to the first transistor and the second transistor.
  • the reset signal is generated in accordance with a change in voltages of at least one of the drain electrode of the first transistor and the drain electrode of the second transistor. That is, the reset signal can easily be generated by generating a voltage based on the drain-to-source currents of the first and second transistors by the load circuit.
  • a predetermined circuit can reliably be initialized by the reset signal generated in response to a change in the voltage.
  • the resetting circuit includes an earth circuit.
  • the earth circuit is connected to the source electrode of the first transistor and to the source electrode of the second transistor, and adjusts an electric current running through the first and second transistors. Therefore, the reset signal can be generated with minimum electric current consumed by the resetting circuit.
  • the first voltage and the second voltage are reliably generated by a voltage generating circuit.
  • FIG. 1 is a circuit diagram showing an example of a conventional resetting circuit
  • FIG. 2 is an explanatory drawing showing the operation of the conventional resetting circuit
  • FIG. 3 is a block diagram showing the basic principle of the present invention.
  • FIG. 4 is an l-V characteristic diagram of an nMOS transistor
  • FIG. 5 is a characteristic diagram showing the operation of a resetting circuit of FIG. 3;
  • FIG. 6 is a circuit diagram showing a first embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing a second embodiment of the present invention.
  • FIG. 8 is a circuit diagram showing a third embodiment of the present invention.
  • FIG. 9 is a characteristic diagram showing the operation of a resetting circuit of FIG. 8.
  • FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention.
  • FIG. 3 shows the basic principle of a resetting circuit and a semiconductor device having the resetting circuit of the present invention.
  • the semiconductor device is formed as, for example, a SDRAM (Synchronous DRAM) on a silicon substrate by using a CMOS process.
  • SDRAM Synchronous DRAM
  • the SDRAM includes a resetting circuit 10 and internal circuits 12 initialized by a reset signal RST generated by the resetting circuit 10 .
  • the resetting circuit 10 includes a first transistor 14 and a second transistor 16 of nMOS transistors, a voltage generating circuit 18 , a load circuit 20 , an earth circuit 22 , and a waveform shaping circuit 24 .
  • the voltage generating circuit 18 , the load circuit 20 , the earth circuit 22 , and the waveform shaping circuit 24 are a control circuit for generating the reset signal.
  • the SDRAM further includes an I/O circuit, a memory core, and a control circuit for controlling the memory core in addition to those shown in the figure.
  • the ratio W/L of a gate width W to a channel length L of the second transistor 16 is designed to be greater than the ratio W/L of a gate width W to a channel length L of the first transistor 14 .
  • the size of the second transistor 16 is shown to be larger than that of the first transistor 14 .
  • their. source electrodes are connected to each other.
  • the source electrodes are connected to the earth 15 circuit 22 .
  • the gate of the first transistor 14 is connected to the voltage generating circuit 18 through a node ND 04 .
  • the gate of the second transistor 16 is connected to the voltage generating circuit 18 through a node ND 05 .
  • the drain electrodes of the first and second transistors 14 and 16 are connected to the load circuit 20 through nodes ND 06 and ND 07 , respectively. At least one of the drain electrodes of the first and second transistors 14 and 16 is connected to the waveform shaping circuit 24 .
  • the waveform shaping circuit 24 outputs a reset signal RST.
  • the reset signal RST is activated (i.e., at a high level) for a predetermined period of time, and thereafter is inactivated, for example.
  • a power supply line VCC and a ground line VSS are connected to the voltage generating circuit 18 .
  • a voltage supplied to the power supply line VCC is designated as a supply voltage VCC
  • a voltage supplied to the ground line VSS is designated as a ground voltage VSS.
  • the voltage generating circuit 18 generates a first voltage V 1 in the node ND 04 in accordance with a rise in the supply voltage VCC, and generates a second voltage V 2 lower than the first voltage V 1 in the node ND 05 .
  • the first transistor 14 receives the first voltage V 1 , which is raised in accordance with a rise in the supply voltage VCC, through the gate electrode
  • the second transistor 16 receives the second voltage V 2 (lower than the first voltage V 1 ), which is raised in accordance with a rise in the supply voltage VCC, through the gate electrode.
  • the load circuit 20 connected to the power supply line VCC supplies an electric current to the first and second transistors 14 , 16 , and causes the drain electrodes of the first and second transistors 14 , 16 to generate a voltage.
  • the earth circuit 22 adjusts an electric current running through the first and second transistors 14 , 16 . Therefore, a reset signal RST can be generated in a state in which the current consumed in the resetting circuit 10 is minimized. If the load circuit 20 can adjust the current running through the first and second transistors 14 , 16 , the earth circuit 22 is unnecessary.
  • the waveform shaping circuit 24 shapes a voltage waveform generated in the drain electrodes of the first and second transistors 14 , 16 , and outputs it as a reset signal RST.
  • FIG. 4 shows how a drain-to-source current IDS varies in relation to the gate-to-source voltages VGS of the first and second transistors 14 and 16 in a subthreshold area.
  • the characteristic of the first transistor 14 is shown by the solid line, and the characteristic of the second transistor 16 is shown by the broken line.
  • the IDS characteristic is calculated according to the following equation:
  • IDS ( W/L ) ⁇ ( VGS ⁇ Vth ) 2
  • IDS is a drain-to-source current
  • W and L are a gate width of the transistor and a gate length thereof, respectively
  • ⁇ is a constant proper to the transistor
  • VGS is a gate-to-source voltage
  • Vth is a threshold voltage of the transistor.
  • the upper solid and broken lines in the figure each indicate a case where the threshold voltage of the transistor is lowest in specifications, and the lower ones each indicate a case where the threshold voltage of the transistor is highest therein.
  • the resetting circuit 10 shown in FIG. 3 keeps the reset signal RST at a high level (i.e., a resetting period) until the supply voltage VCC reaches, for example, 1.2V, and changes the reset signal RST to a low level when the supply voltage VCC exceeds 1.2V, as described later.
  • the reset signal RST changes to the low level when the voltages of the nodes ND 04 and NDOS (i.e., gate voltages of the first and second transistors 14 , 16 ) reach about 0.35V and 0.3V, respectively.
  • the first and second transistors 14 , 16 are almost the same in the rate of change in the current to a change in the voltage. Therefore, in these voltages, the drain-to-source current IDS of each of the first and second transistors 14 , 16 become equal independently of the threshold voltage.
  • FIG. 5 shows the operation of the resetting circuit 10 described above.
  • the upper part of the figure shows the respective changes of the first voltage V 1 , the second voltage V 2 , and the reset signal RST in relation to the supply voltage VCC.
  • the lower part thereof shows the respective changes of the drain-to-source currents IDS of the first and second transistors 14 , 16 in relation to the supply voltage VCC.
  • the first and second voltages V 1 , V 2 rise in accordance with the supply voltage VCC (FIG. 5 ( a )).
  • the first voltage V 1 is always higher than the second voltage V 2 .
  • the current IDS 2 of the second transistor 16 is larger than the current IDS 1 of the first transistor 14 (FIG. 5 ( b)).
  • the voltage of the node ND 06 shown in FIG. 3 is higher than that of the node ND 07 at this time, and the reset signal RST is at a high level (FIG. 5 ( c )).
  • the internal circuit of the SDRAM is initialized at the point where the supply voltage VCC rises and exceeds a predetermined value, in response to the activation of the reset signal RST.
  • the respective currents IDS 1 and IDS 2 of the first and second transistors 14 , 16 increase, and both the currents IDS 1 and IDS 2 are equalized with each other (FIG. 5 ( e )).
  • the voltage of the node ND 06 is equal to that of the node ND 07 at this time.
  • the reset signal RST changes to a low level (FIG. 5 ( f )). That is, the present invention generates the reset signal RST by the use of the characteristic of the subthreshold area of the transistor and the characteristic obtained when the inversion layer is formed.
  • the current IDS 1 of the first transistor 14 becomes larger than the current IDS 2 of the second transistor 16 (FIG. 5 ( g )). Accordingly, the voltage of the node ND 06 becomes lower than that of the node ND 07 .
  • the internal circuit of the SDRAM shown in FIG. 3 releases the initialized state and reaches a normally operable state, in response to the inactivation (low-level) of the reset signal RST.
  • the threshold voltages of the first and second transistors 14 , 16 both change to the same side.
  • the currents IDS of the first and second transistors 14 , 16 are the same even when the threshold voltage changes within the range of a voltage VGS of 0.3V to 0.35V.
  • the intersection of the currents IDS 1 and IDS 2 of the transistors 14 , 16 changes only in the directions of the currents (i.e., vertically in the figure) even when the threshold voltage changes.
  • the reset., signal RST is always inactivated by a predetermined supply voltage VCC,(in this example, about 1.2V) even when the threshold voltages of the first and second transistors 14 , 16 change.
  • the two nMOS transistors 14 , 16 are formed in the resetting circuit 10 , and the gate electrode of the large size nMOS transistor 16 is always supplied with a voltage lower than the gate electrode of the small size nMOS transistor 14 when the supply voltage rises. Since the reset signal RST is generated when the values of the drain-to-source currents IDS of the first and second transistors 14 , 16 cross, the reset signal RST can be always generated by a predetermined supply voltage VCC independently of the threshold voltages of the transistors 14 , 16 .
  • this resetting circuit 10 is formed in the SDRAM, the internal circuit 12 of the SDRAM can be always initialized by the predetermined supply voltage.
  • a reset signal RST can be easily generated corresponding to a change in at least one voltage of the drain electrodes of the first and second transistors 14 , 16 .
  • the earth circuit 22 is connected to the source electrodes of the first and second transistors 14 , 16 , the electric current running through the first and second transistors 14 , 16 can be adjusted. Therefore, a reset signal RST can be generated while minimizing the electric current consumed by the resetting circuit 10 .
  • the voltage generating circuit 18 that generates the first voltage V 1 and the second voltage V 2 based on the supply voltage VCC is formed, the first and second voltages V 1 , V 2 can be reliably generated.
  • FIG. 6 shows a first embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention.
  • the same reference characters as in the above-mentioned basic principle are given to constituent elements, respectively, in this embodiment that are identical to those in the above-mentioned basic principle, and a detailed description of them is omitted.
  • the resetting circuit is formed in a SDRAM, and an internal circuit of the SDRAM is initialized in this embodiment.
  • the resetting circuit includes a first transistor 14 , a second transistor 16 , voltage generating circuits 26 and 28 , a load circuit 30 , an earth circuit 32 , and a waveform shaping circuit 34 of an inverter.
  • the voltage generating circuits 26 and 28 , the load circuit 30 , the earth circuit 32 , and the waveform shaping circuit 34 of an inverter are a control circuit for generating a reset signal.
  • the ratio W/L of the gate width W to the channel length L of the second transistor 16 is 20 times as large as the ratio W/L of the gate width W to the channel length L of the first transistor 14 .
  • the channel length L of the second transistor 16 is equalized with that of the first transistor 14
  • the gate width W of the second transistor 16 is designed to be 20 times as large as that of the first transistor 14 .
  • the source electrodes of the first and second transistors 14 , 16 are connected to each other. These source electrodes are each connected to the earth circuit 32 .
  • the gate of the first transistor 14 is connected to the voltage generating circuit 26 through a node ND 04 (first voltage V 1 ).
  • The, gate of the second transistor 16 is connected to the voltage generating circuit 28 through a node ND 05 (second voltage V 2 ).
  • the drain electrodes of the first and second transistors 14 , 16 are connected to 12 ) the load circuit 30 through nodes ND 06 and ND 07 , respectively.
  • the drain electrode (node ND 07 ) of the second transistor 16 is connected to the waveform shaping circuit 34 .
  • the waveform shaping circuit- 24 outputs a reset signal RST.
  • the voltage generating circuit 26 is constructed such that resistors R 4 and RS are connected in series with each other with the node ND 04 (first voltage V 1 ) between a power supply line VCC and a ground line VSS.
  • the voltage generating circuit 28 is constructed such that resistors R 6 and R 7 are connected in series with each other with the node ND 05 (second voltage V 2 ) between a power supply line VCC and a ground line VSS.
  • the load circuit 30 is formed of resistors R 8 and R 9 each end of which is connected to a power supply line VCC, and the other ends are connected to the node ND 06 and the node ND 07 , respectively.
  • the earth circuit 32 is constructed by a resistor R 10 an end of which is connected to a ground line VSS, and the other end is connected to the source electrodes of the first and second transistors 14 , 16 .
  • the resistors R 4 to R 10 are formed by the use of diffusion layers (diffusion resistances).
  • the voltage generating circuit 26 generates the first voltage V 1 in accordance with the supply voltage VCC.
  • the voltage generating circuit 28 generates the second voltage V 2 which is lower than the first voltage V 1 in accordance with the supply voltage VCC.
  • FIG. 7 shows a second embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention.
  • the same reference characters as in the above-mentioned basic principle and the first embodiment are given to constituent elements, respectively, in this embodiment that are identical to those in the basic principle and the first embodiment, and a detailed description of them is omitted.
  • the resetting circuit is formed in a SDRAM, and an internal circuit of the SDRAM is initialized in this embodiment in the same way as above.
  • the resetting circuit includes a first transistor 14 , a second transistor 16 , a voltage generating circuit 36 , a load circuit 38 , an earth circuit 40 , and a waveform shaping circuit 34 .
  • the voltage generating circuit 36 , the load circuit 38 , the earth circuit 40 , and the waveform shaping circuit 34 are a controlling circuit for generating a reset signal.
  • the ratio W/L of a gate width W to a channel length L of the second transistor 16 is 20 times as large as the ratio W/L of a gate width W to a channel length L of the first transistor 14 .
  • the source electrodes of the first and second transistors 14 , 16 are connected to each other. The source electrodes are connected to the earth circuit 40 .
  • the gate of the first transistor 14 is connected to the voltage generating circuit 36 through a node ND 04 .
  • the gate of the second transistor 16 is connected to the voltage generating circuit 36 through a node ND 05 .
  • the drain electrodes of the first and second transistors 14 , 16 are connected to the load circuit 38 through nodes ND 06 and ND 07 , respectively.
  • the drain electrode (node ND 07 ) of the second transistor 16 is connected to the waveform shaping circuit 34 .
  • the waveform shaping circuit 34 outputs a reset signal RST.
  • the voltage generating circuit 36 is constructed such that resistors R 11 , R 12 , and R 13 are connected in series with each other with nodes ND 04 and ND 05 between a power supply line VCC and a ground line VSS.
  • the load circuit 38 has a current mirror. circuit that is formed of two pMOS transistors. In the pMOS transistor, its source electrode is connected to a power supply line VCC, its gate electrode is connected to the node ND 06 , and its drain electrode is connected to the nodes ND 06 and ND 07 .
  • the earth circuit 40 is constructed by an nMOS transistor in which its gate electrode is connected to a power supply line VCC, its source electrode is connected to a ground line VSS, and its drain electrode is connected to the source electrodes of the first and second transistors 14 , 16 .
  • the same effect as in the above-mentioned first embodiment can be obtained in this embodiment. Furthermore, in this embodiment, since both the first voltage V 1 and the second voltage V 2 are generated by the single voltage generating circuit 36 , the relationship between the first voltage V 1 and the second voltage V 2 can be more easily maintained than in the first embodiment. Furthermore, the layout area of the voltage generating circuit can be reduced. Furthermore, since the load circuit 38 is constructed with the current mirror circuit, the ability of the reset signal RST to follow a change in the first and second voltages V 1 , V 2 can be more greatly improved compared with the first embodiment. Furthermore, since the earth circuit 40 is constructed with the nMOS transistor, the layout area can be made smaller than in the first embodiment, compared with a case where the earth circuit is constructed with a diffusion resistance.
  • FIG. 8 shows a third embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention.
  • the same reference characters as in the above-mentioned embodiments are given to constituent elements, respectively, in this embodiment that are identical to those in the above-mentioned embodiments, and a detailed description of them is omitted.
  • the resetting circuit is formed in a SDRAM, and an internal circuit of the SDRAM is initialized in this embodiment in the same way as above.
  • the resetting circuit includes a first transistor 14 , a second transistor 16 , a voltage generating circuit 36 , load circuits 42 and 44 , and a waveform shaping circuit 46 .
  • the voltage generating circuit 36 , load circuits 42 and 44 , and the waveform shaping circuit 46 are a controlling circuit for generating a reset signal.
  • the ratio W/L of a gate width W to a channel length L of the second transistor 16 is 20 times as large as the ratio W/L of a gate width W to a channel length L of the first transistor 14 .
  • their source electrodes are connected to a ground line VSS.
  • the gate of the first transistor 14 is connected to the voltage generating circuit 36 through a node ND 04 (first voltage V 1 ).
  • the gate of the second transistor 16 is connected to the voltage generating circuit 36 through a node ND 05 (second voltage V 2 ).
  • the drain electrodes of the first and second transistors 14 , 16 are connected to the load circuits 42 , 44 through nodes ND 06 (voltage V 3 ) and ND 07 (voltage V 4 ), respectively.
  • the drain electrodes (nodes ND 06 and ND 07 ) of the first and second transistors 14 , 16 are connected to the waveform shaping circuit 46 .
  • the waveform shaping circuit 46 outputs a reset signal RST.
  • the load circuits 42 , 44 are each constructed with a diode-connected nMOS transistor. That is, the gate electrode and the drain electrode of the nMOS transistor of each of the load circuits 42 , 44 are connected to a power supply line VCC, and the source electrodes thereof are connected to the nodes ND 06 and ND 07 , respectively.
  • the waveform shaping circuit 46 includes a current mirror circuit and an inverter 46 e .
  • the current mirror circuit is made of nMOS transistors 46 a , 46 b and pMOS transistors 46 c , 46 d .
  • the inverter 46 e outputs a reset signal RST.
  • nMOS transistor 46 a its source electrode is connected to a ground line VSS, its gate electrode is connected to a node ND 09 , and its drain electrode is connected to a node ND 08 .
  • nMOS transistor 46 b its source electrode is connected to a ground line VSS, and its gate electrode and drain electrode are connected to the node ND 09 .
  • the pMOS transistor 46 c its source electrode is connected to a power supply line VCC, its gate electrode is connected to the n ode ND 06 , and its drain electrode is connected to the node ND 08 .
  • the pMOS transistor 46 d its source electrode is connected to a power supply line VCC, its gate electrode is connected to the node ND 07 , and its drain electrode is connected to the node ND 09 .
  • the inverter 46 e its input is connected to the node ND 08 .
  • FIG. 9 shows the operation of the resetting circuit in FIG. 8 .
  • the first voltage V 1 and the second voltage V 2 rise in accordance with the voltage VCC (FIG. 9 ( a )).
  • the voltage V 4 becomes low in the subthreshold area since the electric current IDS 2 of the transistor 16 is large as shown in FIG. 4 (FIG. 9 ( b )).
  • the waveform shaping circuit 46 shown in FIG. 8 receives the voltage V 3 and the voltage V 4 which is lower than the voltage V 3 in the current mirror circuit, and outputs a high-level reset signal RST (FIG. 9 ( c )).
  • the voltages V 3 and V 4 are equalized with each other (FIG. 9 ( d )). Thereafter, the voltage V 3 becomes lower than the voltage V 4 due to the fact that the current IDS 1 of the transistor 14 shown in FIG. 4 exceeds the current IDS 2 of the transistor 16 (FIG. 9 ( e )).
  • the waveform shaping circuit 46 receives the voltage V 3 and the voltage V 4 which is higher than the voltage V 3 in the current mirror circuit, and lowers the level of the reset signal RST (FIG. 9 ( f )).
  • the on-resistances of the transistors 14 , 16 decrease, and the voltages V 3 , V 4 fall. Since the on-resistance of the transistor 16 that is larger in size than the transistor 14 becomes lower than that of the transistor 14 at this time, the voltage V 4 of the node ND 07 connected to the transistor 16 again becomes lower than the voltage V 3 ((g) of FIG. 9 ).
  • the current mirror circuit of the waveform shaping circuit 46 is situated out of the operating range of differential amplification when the supply voltage exceeds about 2V, and both the pMOS transistors 46 c , 46 d are turned on. For this reason, the reset signal RST never again changes to the high level.
  • FIG. 10 shows a fourth embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention.
  • the same reference characters as in the above-mentioned embodiments are given to constituent elements, respectively, in this embodiment that are identical to those in the above-mentioned embodiments, and a detailed description of them is omitted.
  • a voltage generating circuit 48 is used instead of the voltage generating circuit 36 described in the third embodiment.
  • the other structures are substantially the same as in the third embodiment.
  • the voltage generating circuit 48 is formed of a diode-connected nMOS transistor 48 a and resistors R 14 , R 15 , and R 16 that are connected in series between a power supply line VCC and a ground line VSS.
  • the gate electrode and the drain electrode of the hMOS transistor 48 a are connected to the power supply line VCC, and the source electrode and the substrate thereof are connected to an end of the resistor R 14 .
  • the connection node of the resistors R 14 , R 15 is connected to the node NDO 4 .
  • the connection node of the resistors R 15 , R 16 is connected to the node ND 05 .
  • the gradient of the I-V characteristic shown in FIG. 4 can be sharpened in the vicinity of the intersection of the current IDS 1 of the first transistor 14 and the current IDS 2 of the second transistor 16 shown in FIG. 5 .
  • the ability of the reset signal RST to follow a change in the first and second voltages V 1 , V 2 can be improved even more.
  • the resetting circuit is formed by the use of the nMOS transistors 14 , 16 was described in the above-mentioned embodiments.
  • the present invention is not limited to this example.
  • the resetting circuit may be formed by the use of two pMOS transistors.
  • the present invention is applied to a SDRAM was described in the above embodiments.
  • the invention is not limited to this example.
  • the present invention may be applied to a FCRAM (Fast Cycle RAM).
  • the present invention may be applied to a microcomputer, a logic LSI, and a system LSI.

Landscapes

  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
US09/820,714 2000-10-18 2001-03-30 Resetting circuit independent of a transistor's threshold Expired - Lifetime US6429705B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000317748A JP3703706B2 (ja) 2000-10-18 2000-10-18 リセット回路およびリセット回路を有する半導体装置
JP2000-317748 2000-10-18

Publications (2)

Publication Number Publication Date
US20020043994A1 US20020043994A1 (en) 2002-04-18
US6429705B1 true US6429705B1 (en) 2002-08-06

Family

ID=18796485

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/820,714 Expired - Lifetime US6429705B1 (en) 2000-10-18 2001-03-30 Resetting circuit independent of a transistor's threshold

Country Status (2)

Country Link
US (1) US6429705B1 (ja)
JP (1) JP3703706B2 (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030174002A1 (en) * 2002-03-12 2003-09-18 Slamowitz Mark N. Power-on reset circuit for use in low power supply voltage applications
US20030227306A1 (en) * 2002-06-07 2003-12-11 Di Iorio Ercole Rosario Low voltage Vcc detector
US20040189356A1 (en) * 2003-03-31 2004-09-30 Masaharu Wada Power-on detector, and power-on reset circuit using the same
US20040232957A1 (en) * 2003-05-21 2004-11-25 Chang Ho Do Internal voltage generator for semiconductor device
US20050093529A1 (en) * 2003-10-31 2005-05-05 Young-Do Hur Power-up signal generating apparatus
US20050184771A1 (en) * 2003-12-26 2005-08-25 Kiyotaka Uchigane Semiconductor apparatus
US20050184770A1 (en) * 2004-02-19 2005-08-25 Hynix Semiconductor Inc. Internal circuit protection device
US20080111593A1 (en) * 2006-11-15 2008-05-15 Samsung Electronics Co., Ltd. Power-up reset circuits and semiconductor devices including the same
US20090085619A1 (en) * 2007-10-01 2009-04-02 Silicon Laboratories Inc. Power supply voltage monitors
US10771051B2 (en) * 2018-06-21 2020-09-08 Lapis Semiconductor Co., Ltd. Semiconductor device and method of generating power on reset signal

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4021283B2 (ja) 2002-08-28 2007-12-12 富士通株式会社 半導体装置
FR2844118B1 (fr) * 2002-08-29 2005-02-18 St Microelectronics Sa Circuit de detection de potentiel
JP4047689B2 (ja) * 2002-10-03 2008-02-13 沖電気工業株式会社 パワーオンリセット回路
EP1501192B1 (en) * 2003-07-21 2014-02-26 Broadcom Corporation Power-on reset circuit for use in low power supply voltage applications
KR100562636B1 (ko) * 2003-12-30 2006-03-20 주식회사 하이닉스반도체 반도체 메모리 소자의 파워업 회로
US8253452B2 (en) * 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
JP2010147979A (ja) * 2008-12-22 2010-07-01 Elpida Memory Inc 半導体装置およびパワーオンリセット回路の調整方法
JP6224994B2 (ja) * 2013-11-01 2017-11-01 キヤノン株式会社 情報処理装置およびその制御方法
CN103746681B (zh) * 2013-12-24 2017-06-30 北京时代民芯科技有限公司 一种cmos器件电源上下电输出三态控制电路

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446381A (en) * 1982-04-22 1984-05-01 Zilog, Inc. Circuit and technique for initializing the state of bistable elements in an integrated electronic circuit
US4634905A (en) * 1985-09-23 1987-01-06 Motorola, Inc. Power-on-reset circuit having a differential comparator with intrinsic offset voltage
US5115146A (en) * 1990-08-17 1992-05-19 Sgs-Thomson Microelectronics, Inc. Power-on reset circuit for controlling test mode entry
US5144159A (en) * 1990-11-26 1992-09-01 Delco Electronics Corporation Power-on-reset (POR) circuit having power supply rise time independence
US5359233A (en) * 1990-09-28 1994-10-25 Dallas Semiconductor Corporation Reset monitor for detection of power failure and external reset
US5530395A (en) * 1995-04-03 1996-06-25 Etron Technology Inc. Supply voltage level control using reference voltage generator and comparator circuits
US6346834B1 (en) * 1996-11-13 2002-02-12 Samsung Electronics Co., Ltd. Power on reset circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4446381A (en) * 1982-04-22 1984-05-01 Zilog, Inc. Circuit and technique for initializing the state of bistable elements in an integrated electronic circuit
US4634905A (en) * 1985-09-23 1987-01-06 Motorola, Inc. Power-on-reset circuit having a differential comparator with intrinsic offset voltage
US5115146A (en) * 1990-08-17 1992-05-19 Sgs-Thomson Microelectronics, Inc. Power-on reset circuit for controlling test mode entry
US5359233A (en) * 1990-09-28 1994-10-25 Dallas Semiconductor Corporation Reset monitor for detection of power failure and external reset
US5144159A (en) * 1990-11-26 1992-09-01 Delco Electronics Corporation Power-on-reset (POR) circuit having power supply rise time independence
US5530395A (en) * 1995-04-03 1996-06-25 Etron Technology Inc. Supply voltage level control using reference voltage generator and comparator circuits
US6346834B1 (en) * 1996-11-13 2002-02-12 Samsung Electronics Co., Ltd. Power on reset circuit

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030174002A1 (en) * 2002-03-12 2003-09-18 Slamowitz Mark N. Power-on reset circuit for use in low power supply voltage applications
US6943596B2 (en) * 2002-03-12 2005-09-13 Broadcom Corporation Power-on reset circuit for use in low power supply voltage applications
US20030227306A1 (en) * 2002-06-07 2003-12-11 Di Iorio Ercole Rosario Low voltage Vcc detector
US6888384B2 (en) * 2003-03-31 2005-05-03 Kabushiki Kaisha Toshiba Power-on detector, and power-on reset circuit using the same
US20040189356A1 (en) * 2003-03-31 2004-09-30 Masaharu Wada Power-on detector, and power-on reset circuit using the same
US20040232957A1 (en) * 2003-05-21 2004-11-25 Chang Ho Do Internal voltage generator for semiconductor device
US20050093529A1 (en) * 2003-10-31 2005-05-05 Young-Do Hur Power-up signal generating apparatus
US7212046B2 (en) * 2003-10-31 2007-05-01 Hynix Semiconductor Inc. Power-up signal generating apparatus
US20050184771A1 (en) * 2003-12-26 2005-08-25 Kiyotaka Uchigane Semiconductor apparatus
US20050184770A1 (en) * 2004-02-19 2005-08-25 Hynix Semiconductor Inc. Internal circuit protection device
US20080111593A1 (en) * 2006-11-15 2008-05-15 Samsung Electronics Co., Ltd. Power-up reset circuits and semiconductor devices including the same
US20090085619A1 (en) * 2007-10-01 2009-04-02 Silicon Laboratories Inc. Power supply voltage monitors
US20090089605A1 (en) * 2007-10-01 2009-04-02 Silicon Laboratories Inc. Power supply voltage monitors
US7873856B2 (en) * 2007-10-01 2011-01-18 Silicon Laboratories Inc. Microcontroller unit having power supply voltage monitor
US7873854B2 (en) * 2007-10-01 2011-01-18 Silicon Laboratories Inc. System for monitoring power supply voltage
US10771051B2 (en) * 2018-06-21 2020-09-08 Lapis Semiconductor Co., Ltd. Semiconductor device and method of generating power on reset signal

Also Published As

Publication number Publication date
JP2002124861A (ja) 2002-04-26
JP3703706B2 (ja) 2005-10-05
US20020043994A1 (en) 2002-04-18

Similar Documents

Publication Publication Date Title
US6429705B1 (en) Resetting circuit independent of a transistor's threshold
JP4648346B2 (ja) 調整可能なトランジスタボディバイアス回路網
JP3026474B2 (ja) 半導体集積回路
US5640122A (en) Circuit for providing a bias voltage compensated for p-channel transistor variations
US7199623B2 (en) Method and apparatus for providing a power-on reset signal
US7099223B2 (en) Semiconductor memory device
US7212046B2 (en) Power-up signal generating apparatus
KR100566302B1 (ko) 파워업 신호 발생 장치
US8183914B2 (en) Constant Gm circuit and methods
KR100815184B1 (ko) 반도체 소자의 파워 업 신호 생성장치
US8970257B2 (en) Semiconductor device for offset compensation of reference current
US8106689B2 (en) Circuit for generating power-up signal of semiconductor memory apparatus
US7576575B2 (en) Reset signal generator in semiconductor device
JP3868131B2 (ja) バックバイアス回路
JP2002015599A (ja) 半導体記憶装置
KR0172436B1 (ko) 반도체 장치의 기준전압 발생회로
KR100550795B1 (ko) 파워 업 회로
KR0152957B1 (ko) 반도체 메모리장치
KR100772711B1 (ko) 내부전원 생성장치
KR100554840B1 (ko) 파워 업 신호 발생 회로
KR0172342B1 (ko) 기준전압 발생회로
US11720127B2 (en) Amplifier and voltage generation circuit including the same
KR100543909B1 (ko) 반도체 메모리 장치의 위들러형 기준전압 발생 장치
KR102214629B1 (ko) 오프 칩 드라이버
KR20090047700A (ko) 기준전압 발생회로

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BANDO, YOSHIHIDE;UCHIDA, TOSHIYA;REEL/FRAME:011665/0386

Effective date: 20010316

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: FUJITSU MICROELECTRONICS LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021998/0645

Effective date: 20081104

Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021998/0645

Effective date: 20081104

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024982/0245

Effective date: 20100401

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: SOCIONEXT INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:035507/0612

Effective date: 20150302