US20020043994A1 - Resetting circuit and semiconductor device having the same - Google Patents
Resetting circuit and semiconductor device having the same Download PDFInfo
- Publication number
- US20020043994A1 US20020043994A1 US09/820,714 US82071401A US2002043994A1 US 20020043994 A1 US20020043994 A1 US 20020043994A1 US 82071401 A US82071401 A US 82071401A US 2002043994 A1 US2002043994 A1 US 2002043994A1
- Authority
- US
- United States
- Prior art keywords
- voltage
- transistor
- circuit
- transistors
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
Landscapes
- Electronic Switches (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device having a resetting circuit.
- 2. Description of the Related Art
- Generally, a semiconductor device, such as a DRAM, includes a resetting circuit. When the power supply is turned on, the resetting circuit is operated to initialize an internal circuit, so that the semiconductor device is prevented from malfunctioning.
- FIG. 1 shows an example of the resetting circuit implemented in the semiconductor device.
- The resetting circuit has an nMOS transistor2, a voltage generating circuit 4, a
load circuit 6, and awaveform shaping circuit 8. The nMOS transistor 2 connects a gate electrode to a node ND01, connects a drain electrode to a node ND02, and connects a source electrode to a ground line VSS. The voltage generating circuit 4 is formed such that resistors RI and R2 are connected in series with each other with the node ND01 between a power supply line VCC and the ground line VSS. Theload circuit 6 is formed such that an end of theload circuit 6 is connected to the power supply line VCC, and the other end of theload circuit 6 is connected to a resistor R3 connected to the node ND02. Thewaveform shaping circuit 8 is has two inverters that are connected in series. In thewaveform shaping circuit 8, its input is connected to the node ND02, and a reset signal RST is output from its output. - This type of resetting circuit detects that a supply voltage VCC has risen to a predetermined value by utilizing the threshold voltage of a transistor (in this example, the nMOS transistor10), and inactivates the reset signal RST.
- FIG. 2 shows the operation of the resetting circuit mentioned above. When an external supply voltage VCC starts to be supplied to the semiconductor device, the level of the reset signal RST rises in accordance with the external supply voltage VCC for a predetermined period of time, and then becomes low (inactivated). After the supply voltage VCC reaches a predetermined value, the internal circuit that needs to be initialized in the semiconductor device is initialized during a period T1 during which the reset signal RST is inactivated. When the reset signal RST is inactivated, the reset operation is completed, so that the internal circuit begins to perform a normal operation.
- Recently, the operating voltage of semiconductor devices has become low, and, accordingly, a supply voltage VCC supplied from external sources has become low. The ratio of the threshold voltage of a transistor to the supply voltage VCC is high since the threshold voltage of the transistor has almost no dependence on the supply voltage VCC. As a result, the detection level of the supply voltage VCC of the resetting circuit greatly varies depending on a change in the threshold voltage, and the amount (T2 in FIG. 2) of deviation in the inactivation timing of the reset signal RST with respect to a change in the threshold voltage becomes larger than that in the case where the operating voltage is high. The threshold voltage of the transistor varies with the manufacturing conditions, the position of a chip on a wafer, and the position of the wafer in a production lot, of the semiconductor device, or depends on the temperature when the semiconductor device is operating.
- For example, a reset period Ti is shortened if the inactivation timing of the reset signal RST deviates to an early-timing side. This case raises a fear that the internal circuit will not be normally initialized. In the worst case, a high-level period of the reset signal RST necessary to initialize the internal circuit will disappear. On the other hand, if the inactivation timing of the reset signal RST deviates to a late-timing side, there is a fear that the reset signal RST will not be inactivated (i.e., be always at a high level).
- There is a case in which, for example, the aforementioned voltage generating circuit4 is formed of many resistors and fuses, in order to deal with the deviation of the threshold voltage of the transistor at the time a semiconductor device is manufactured. In this case, some of the resistors to be connected in series are selected by trimming the fuses, and a voltage generated in the node ND01 is adjusted according to a threshold voltage. However, the thus constructed voltage generating circuit has a disadvantage in that the chip size increases because a large layout area is required for the resistors and the fuses. Additionally, manufacturing costs increase because a step to trim the fuses is required.
- An object of the present invention is to generate a reset signal which is not influenced by a change in the threshold voltage of a transistor. In other words, the object is to reduce fluctuations in the inactivation timings of reset signals generated by a resetting circuit.
- Another object of the present invention is to reliably initialize an internal circuit of a semiconductor device by the reset signal, and thereby prevent malfunctioning of the semiconductor device.
- According to one of the aspects of the present invention, the resetting circuit includes a first transistor that receives a first voltage at a gate electrode and a second transistor that receives a second voltage at the gate electrode. The second transistor is formed such that the ratio W/L (transistor size) of a gate width W to a channel length L is larger than the ratio W/L of the first transistor. The first voltage rises in accordance with the rise of a supply voltage. The second voltage rises in accordance with the rise of the supply voltage, and is lower than the first voltage.
- The gate voltage (accurately, gate-to-source voltage) of the second transistor is always lower than the gate voltage of the first transistor. The transistor size of the second transistor is larger than that of the first transistor. Therefore, the drain-to-source current (i.e., subthreshold current) of the second transistor is larger than the drain-to-source current of the first transistor for a while after the supply voltage is applied (i.e., while the supply voltage is low).
- Since the first voltage is always higher than the second voltage, an increase in the drain-to-source current of the first transistor is larger than an increase in the drain-to-source current of the second transistor. In other words, an inversion layer is formed in the first transistor earlier than in the second transistor. As a result, the drain-to-source current of the first transistor is equalized with the drain-to-source current of the second transistor at a predetermined supply voltage, and thereafter the drain-to-source current of the first transistor becomes larger than that of the second transistor. That is, an inversion occurs between the drain-to-source currents of the first and second transistors by the predetermined supply voltage.
- If the threshold voltages of the first and second transistors are both high, both the drain-to-source currents thereof become large. Therefore, the supply voltage in which the electric current is inverted is substantially the same as when the threshold voltage is at its average level. The same applies to the case in which the threshold voltages of the first and second transistors are both low. That is, the supply voltage in which the electric current is inverted is substantially the same as when the threshold voltage is at its average level. Since the control circuit generates the reset signal when the values of the drain-to-source currents cross, the reset signal can always be generated at the predetermined supply voltage, independent from the threshold voltage of the transistor.
- Therefore, in the case when the resetting circuit is formed in a semiconductor device, an internal circuit of the semiconductor device is initialized whenever the supply voltage reaches a predetermined value, without being influenced by a change in the threshold voltage. The reset signal may be generated by, for example, the direct detection of a current value, and may be generated by utilizing a voltage generated in the drain electrode of the transistor.
- According to another aspect of the resetting circuit in the present invention, since the channel lengths L of the first and second transistors are equalized with each other, the two transistors maintain predetermined relative relations with each parameter in subthreshold characteristic during changes in each of the parameters. This results in a desired V-I characteristic to be easily realized.
- According to still another aspect of the resetting circuit in the present invention, the resetting circuit includes a load circuit. The load circuit is connected to the drain electrode of the first transistor and to the drain electrode of the second transistor, and supplies an electric current to the first transistor and the second transistor. The reset signal is generated in accordance with a change in voltages of at least one of the drain electrode of the first transistor and the drain electrode of the second transistor. That is, the reset signal can easily be generated by generating a voltage based on the drain-to-source currents of the first and second transistors by the load circuit. A predetermined circuit can reliably be initialized by the reset signal generated in response to a change in the voltage.
- According to still another aspect of the resetting circuit in the present invention, the resetting circuit includes an earth circuit. The earth circuit is connected to the source electrode of the first transistor and to the source electrode of the second transistor, and adjusts an electric current running through the first and second transistors. Therefore, the reset signal can be generated with minimum electric current consumed by the resetting circuit.
- According to still another aspect of the resetting circuit in the present invention, the first voltage and the second voltage are reliably generated by a voltage generating circuit.
- The nature, principle, and utility of the invention will become more apparent form the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by identical reference numbers, in which:
- FIG. 1 is a circuit diagram showing an example of a conventional resetting circuit;
- FIG. 2 is an explanatory drawing showing the operation of the conventional resetting circuit;
- FIG. 3 is a block diagram showing the basic principle of the present invention;
- FIG. 4 is an I-V characteristic diagram of an nMOS transistor;
- FIG. 5 is a characteristic diagram showing the operation of a resetting circuit of FIG. 3;
- FIG. 6 is a circuit diagram showing a first embodiment of the present invention;
- FIG. 7 is a circuit diagram showing a second embodiment of the present invention;
- FIG. 8 is a circuit diagram showing a third embodiment of the present invention;
- FIG. 9 is a characteristic diagram showing the operation of a resetting circuit of FIG. 8; and
- FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention.
- Embodiments of the present invention will be described hereinafter with reference to the attached drawings.
- FIG. 3 shows the basic principle of a resetting circuit and a semiconductor device having the resetting circuit of the present invention.
- The semiconductor device is formed as, for example, a SDRAM (Synchronous DRAM) on a silicon substrate by using a CMOS process.
- The SDRAM includes a resetting
circuit 10 andinternal circuits 12 initialized by a reset signal RST generated by the resettingcircuit 10. The resettingcircuit 10 includes afirst transistor 14 and asecond transistor 16 of nMOS transistors, avoltage generating circuit 18, aload circuit 20, anearth circuit 22, and awaveform shaping circuit 24. Thevoltage generating circuit 18, theload circuit 20, theearth circuit 22, and thewaveform shaping circuit 24 are a control circuit for generating the reset signal. The SDRAM further includes an I/O circuit, a memory core, and a control circuit for controlling the memory core in addition to those shown in the figure. - The ratio W/L of a gate width W to a channel length L of the
second transistor 16 is designed to be greater than the ratio W/L of a gate width W to a channel length L of thefirst transistor 14. In the figure, the size of thesecond transistor 16 is shown to be larger than that of thefirst transistor 14. In the first andsecond transistors earth circuit 22. The gate of thefirst transistor 14 is connected to thevoltage generating circuit 18 through a node ND04. The gate of thesecond transistor 16 is connected to thevoltage generating circuit 18 through a node ND05. The drain electrodes of the first andsecond transistors load circuit 20 through nodes ND06 and ND07, respectively. At least one of the drain electrodes of the first andsecond transistors waveform shaping circuit 24. - The
waveform shaping circuit 24 outputs a reset signal RST. When a power supply is on, the reset signal RST is activated (i.e., at a high level) for a predetermined period of time, and thereafter is inactivated, for example. - A power supply line VCC and a ground line VSS are connected to the
voltage generating circuit 18. In the following description, a voltage supplied to the power supply line VCC is designated as a supply voltage VCC, and a voltage supplied to the ground line VSS is designated as a ground voltage VSS. Thevoltage generating circuit 18 generates a first voltage V1 in the node ND04 in accordance with a rise in the supply voltage VCC, and generates a second voltage V2 lower than the first voltage V1 in the node ND05. That is, thefirst transistor 14 receives the first voltage V1, which is raised in accordance with a rise in the supply voltage VCC, through the gate electrode, and thesecond transistor 16 receives the second voltage V2 (lower than the first voltage V1), which is raised in accordance with a rise in the supply voltage VCC, through the gate electrode. - The
load circuit 20 connected to the power supply line VCC supplies an electric current to the first andsecond transistors second transistors earth circuit 22 adjusts an electric current running through the first andsecond transistors circuit 10 is minimized. If theload circuit 20 can adjust the current running through the first andsecond transistors earth circuit 22 is unnecessary. - The
waveform shaping circuit 24 shapes a voltage waveform generated in the drain electrodes of the first andsecond transistors - FIG. 4 shows how a drain-to-source current IDS varies in relation to the gate-to-source voltages VGS of the first and
second transistors first transistor 14 is shown by the solid line, and the characteristic of thesecond transistor 16 is shown by the broken line. In other words, the first andsecond transistors - IDS=(W/L)×8×(VGS−Vth)2
- where IDS is a drain-to-source current, W and L are a gate width of the transistor and a gate length thereof, respectively, β is a constant proper to the transistor, VGS is a gate-to-source voltage, and Vth is a threshold voltage of the transistor.
- Referring to the solid and broken lines, the upper solid and broken lines in the figure each indicate a case where the threshold voltage of the transistor is lowest in specifications, and the lower ones each indicate a case where the threshold voltage of the transistor is highest therein. The resetting
circuit 10 shown in FIG. 3 keeps the reset signal RST at a high level (i.e., a resetting period) until the supply voltage VCC reaches, for example, 1.2V, and changes the reset signal RST to a low level when the supply voltage VCC exceeds 1.2V, as described later. - In this example, the reset signal RST changes to the low level when the voltages of the nodes ND04 and ND05 (i.e., gate voltages of the first and
second transistors 14, 16) reach about 0.35V and 0.3V, respectively. In the vicinity of these voltages, the first andsecond transistors second transistors - FIG. 5 shows the operation of the resetting
circuit 10 described above. The upper part of the figure shows the respective changes of the first voltage V1, the second voltage V2, and the reset signal RST in relation to the supply voltage VCC. The lower part thereof shows the respective changes of the drain-to-source currents IDS of the first andsecond transistors - When the power supply of the system mounted with a SDRAM is turned on, and the supply voltage VCC rises, the first and second voltages V1, V2 rise in accordance with the supply voltage VCC (FIG. 5(a)). The first voltage V1 is always higher than the second voltage V2. In the subthreshold area of the transistor, the current IDS2 of the
second transistor 16, the ratio W/L of which is large, is larger than the current IDS1 of the first transistor 14 (FIG. 5(b)). - The voltage of the node ND06 shown in FIG. 3 is higher than that of the node ND07 at this time, and the reset signal RST is at a high level (FIG. 5(c)). The internal circuit of the SDRAM is initialized at the point where the supply voltage VCC rises and exceeds a predetermined value, in response to the activation of the reset signal RST.
- Since the first voltage V1 is always higher than the second voltage V2, an increase in the electric current IDS1 of the
first transistor 14 becomes larger than an increase in the electric current IDS2 of the second transistor 16 (FIG. 5(d)). In other words, the inversion layer of a channel in thefirst transistor 14 is formed earlier than that of a channel in thesecond transistor 16. - Thereafter, the respective currents IDS1 and IDS2 of the first and
second transistors second transistors - Thereafter, the
current IDS 1 of thefirst transistor 14 becomes larger than the current IDS2 of the second transistor 16 (FIG. 5(g)). Accordingly, the voltage of the node ND06 becomes lower than that of the node ND07. - The internal circuit of the SDRAM shown in FIG. 3 releases the initialized state and reaches a normally operable state, in response to the inactivation (low-level) of the reset signal RST.
- According to the manufacturing conditions of the SDRAM, the threshold voltages of the first and
second transistors second transistors transistors second transistors - As described above, in this embodiment, the two
nMOS transistors circuit 10, and the gate electrode of the largesize nMOS transistor 16 is always supplied with a voltage lower than the gate electrode of the smallsize nMOS transistor 14 when the supply voltage rises. Since the reset signal RST is generated when the values of the drain-to-source currents IDS of the first andsecond transistors transistors - Since this resetting
circuit 10 is formed in the SDRAM, theinternal circuit 12 of the SDRAM can be always initialized by the predetermined supply voltage. - Since a voltage is generated by the
load circuit 20 in the drain electrodes of the first andsecond transistors second transistors - Since the
earth circuit 22 is connected to the source electrodes of the first andsecond transistors second transistors circuit 10. - Since the
voltage generating circuit 18 that generates the first voltage V1 and the second voltage V2 based on the supply voltage VCC is formed, the first and second voltages V1, V2 can be reliably generated. - FIG. 6 shows a first embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention. The same reference characters as in the above-mentioned basic principle are given to constituent elements, respectively, in this embodiment that are identical to those in the above-mentioned basic principle, and a detailed description of them is omitted. As in the above-mentioned basic principle, the resetting circuit is formed in a SDRAM, and an internal circuit of the SDRAM is initialized in this embodiment.
- The resetting circuit includes a
first transistor 14, asecond transistor 16,voltage generating circuits load circuit 30, anearth circuit 32, and awaveform shaping circuit 34 of an inverter. Thevoltage generating circuits load circuit 30, theearth circuit 32, and thewaveform shaping circuit 34 of an inverter are a control circuit for generating a reset signal. - The ratio W/L of the gate width W to the channel length L of the
second transistor 16 is 20 times as large as the ratio W/L of the gate width W to the channel length L of thefirst transistor 14. Especially, the channel length L of thesecond transistor 16 is equalized with that of thefirst transistor 14, and the gate width W of thesecond transistor 16 is designed to be 20 times as large as that of thefirst transistor 14. The source electrodes of the first andsecond transistors earth circuit 32. The gate of thefirst transistor 14 is connected to thevoltage generating circuit 26 through a node ND04 (first voltage V1). The gate of thesecond transistor 16 is connected to thevoltage generating circuit 28 through a node ND05 (second voltage V2). The drain electrodes of the first andsecond transistors load circuit 30 through nodes ND06 and ND07, respectively. The drain electrode (node ND07) of thesecond transistor 16 is connected to thewaveform shaping circuit 34. Thewaveform shaping circuit 24 outputs a reset signal RST. Thevoltage generating circuit 26 is constructed such that resistors R4 and R5 are connected in series with each other with the node ND04 (first voltage V1) between a power supply line VCC and a ground line VSS. Thevoltage generating circuit 28 is constructed such that resistors R6 and R7 are connected in series with each other with the node ND05 (second voltage V2) between a power supply line VCC and a ground line VSS. Theload circuit 30 is formed of resistors R8 and R9 each end of which is connected to a power supply line VCC, and the other ends are connected to the node ND06 and the node ND07, respectively. Theearth circuit 32 is constructed by a resistor R10 an end of which is connected to a ground line VSS, and the other end is connected to the source electrodes of the first andsecond transistors - In the resetting circuit of this embodiment, the
voltage generating circuit 26 generates the first voltage V1 in accordance with the supply voltage VCC. Thevoltage generating circuit 28 generates the second voltage V2 which is lower than the first voltage V1 in accordance with the supply voltage VCC. When the drain-to-source current IDS of thefirst transistor 14 is equalized with the drain-to-source current IDS of thesecond transistor 16, the reset signal RST is inactivated, and the internal circuit of the SDRAM is released from an initialized state. The operation of the resetting circuit is the same as in FIG. 5. - The same effect as in the embodiment shown in FIG. 3 can be obtained in this embodiment.
- FIG. 7 shows a second embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention. The same reference characters as in the above-mentioned basic principle and the first embodiment are given to constituent elements, respectively, in this embodiment that are identical to those in the basic principle and the first embodiment, and a detailed description of them is omitted. The resetting circuit is formed in a SDRAM, and an internal circuit of the SDRAM is initialized in this embodiment in the same way as above.
- The resetting circuit includes a
first transistor 14, asecond transistor 16, avoltage generating circuit 36, aload circuit 38, anearth circuit 40, and awaveform shaping circuit 34. Thevoltage generating circuit 36, theload circuit 38, theearth circuit 40, and thewaveform shaping circuit 34 are a controlling circuit for generating a reset signal. - The ratio W/L of a gate width W to a channel length L of the
second transistor 16 is 20 times as large as the ratio W/L of a gate width W to a channel length L of thefirst transistor 14. The source electrodes of the first andsecond transistors earth circuit 40. The gate of thefirst transistor 14 is connected to thevoltage generating circuit 36 through a node ND04. The gate of thesecond transistor 16 is connected to thevoltage generating circuit 36 through a node ND05. The drain electrodes of the first andsecond transistors load circuit 30 through nodes ND06 and ND07, respectively. The drain electrode (node ND07) of thesecond transistor 16 is connected to thewaveform shaping circuit 34. Thewaveform shaping circuit 34 outputs a reset signal RST. Thevoltage generating circuit 36 is constructed such that resistors R11, R12, and R13 are connected in series with each other with nodes ND04 and ND05 between a power supply line VCC and a ground line VSS. Theload circuit 38 has a current mirror circuit that is formed of two pMOS transistors. In the pMOS transistor, its source electrode is connected to a power supply line VCC, its gate electrode is connected to the node ND06, and its drain electrode is connected to the nodes ND06 and ND07. Theearth circuit 40 is constructed by an nMOS transistor in which its gate electrode is connected to a power supply line VCC, its source electrode is connected to a ground line VSS, and its drain electrode is connected to the source electrodes of the first andsecond transistors - The same effect as in the above-mentioned first embodiment can be obtained in this embodiment. Furthermore, in this embodiment, since both the first voltage V1 and the second voltage V2 are generated by the single
voltage generating circuit 36, the relationship between the first voltage V1 and the second voltage V2 can be more easily maintained than in the first embodiment. Furthermore, the layout area of the voltage generating circuit can be reduced. Furthermore, since theload circuit 38 is constructed with the current mirror circuit, the ability of the reset signal RST to follow a change in the first and second voltages V1, V2 can be more greatly improved compared with the first embodiment. Furthermore, since theearth circuit 40 is constructed with the nMOS transistor, the layout area can be made smaller than in the first embodiment, compared with a case where the earth circuit is constructed with a diffusion resistance. - FIG. 8 shows a third embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention. The same reference characters as in the above-mentioned embodiments are given to constituent elements, respectively, in this embodiment that are identical to those in the above-mentioned embodiments, and a detailed description of them is omitted. The resetting circuit is formed in a SDRAM, and an internal circuit of the SDRAM is initialized in this embodiment in the same way as above.
- The resetting circuit includes a
first transistor 14, asecond transistor 16, avoltage generating circuit 36,load circuits waveform shaping circuit 46. Thevoltage generating circuit 36,load circuits waveform shaping circuit 46 are a controlling circuit for generating a reset signal. - The ratio W/L of a gate width W to a channel length L of the
second transistor 16 is 20 times as large as the ratio W/L of a gate width W to a channel length L of thefirst transistor 14. In the first andsecond transistors first transistor 14 is connected to thevoltage generating circuit 36 through a node ND04 (first voltage V1). The gate of thesecond transistor 16 is connected to thevoltage generating circuit 36 through a node ND05 (second voltage V2). The drain electrodes of the first andsecond transistors load circuits second transistors waveform shaping circuit 46. Thewaveform shaping circuit 46 outputs a reset signal RST. Theload circuits load circuits - The
waveform shaping circuit 46 includes a current mirror circuit and aninverter 46 e. The current mirror circuit is made ofnMOS transistors pMOS transistors inverter 46 e outputs a reset signal RST. In thenMOS transistor 46 a, its source electrode is connected to a ground line VSS, its gate electrode is connected to a node ND09, and its drain electrode is connected to a node ND08. In thenMOS transistor 46 b, its source electrode is connected to a ground line VSS, and its gate electrode and drain electrode are connected to the node ND09. In thepMOS transistor 46 c, its source electrode is connected to a power supply line VCC, its gate electrode is connected to the node ND06, and its drain electrode is connected to the node ND08. In thepMOS transistor 46 d, its source electrode is connected to a power supply line VCC, its gate electrode is connected to the node ND07, and its drain electrode is connected to the node ND09. In theinverter 46 e, its input is connected to the node ND08. - FIG. 9 shows the operation of the resetting circuit in FIG. 8.
- When the power supply of the system mounted with the SDRAM is turned on, and the supply voltage VCC rises, the first voltage V1 and the second voltage V2 rise in accordance with the voltage VCC (FIG. 9(a)). In the voltages V3 and V4 of the nodes ND06 and ND07 shown in FIG. 8, the voltage V4 becomes low in the subthreshold area since the electric current IDS2 of the
transistor 16 is large as shown in FIG. 4 (FIG. 9(b)). Thewaveform shaping circuit 46 shown in FIG. 8 receives the voltage V3 and the voltage V4 which is lower than the voltage V3 in the current mirror circuit, and outputs a high-level reset signal RST (FIG. 9(c)). - With the rise of the supply voltage VCC, the voltages V3 and V4 are equalized with each other (FIG. 9(d)). Thereafter, the voltage V3 becomes lower than the voltage V4 due to the fact that the current IDS1 of the
transistor 14 shown in FIG. 4 exceeds the current IDS2 of the transistor 16 (FIG. 9(e)). Thewaveform shaping circuit 46 receives the voltage V3 and the voltage V4 which is higher than the voltage V3 in the current mirror circuit, and lowers the level of the reset signal RST (FIG. 9(f)). - When the supply voltage VCC further rises, and the first and second voltages V1, V2 rise, the on-resistances of the
transistors transistor 16 that is larger in size than thetransistor 14 becomes lower than that of thetransistor 14 at this time, the voltage V4 of the node ND07 connected to thetransistor 16 again becomes lower than the voltage V3 ((g) of FIG. 9). However, the current mirror circuit of thewaveform shaping circuit 46 is situated out of the operating range of differential amplification when the supply voltage exceeds about 2V, and both thepMOS transistors - The same effect as in the above-mentioned second embodiment can be obtained in this embodiment. Additionally, since the voltages V3, V4 generated in the drain electrodes of the
transistors waveform shaping circuit 46 in this embodiment, the ability of the reset signal RST to follow a change in the first and second voltages V1, V2 can be improved even more than in the second embodiment. - FIG. 10 shows a fourth embodiment of a resetting circuit and a semiconductor device having the resetting circuit of the present invention. The same reference characters as in the above-mentioned embodiments are given to constituent elements, respectively, in this embodiment that are identical to those in the above-mentioned embodiments, and a detailed description of them is omitted. In this embodiment, a
voltage generating circuit 48 is used instead of thevoltage generating circuit 36 described in the third embodiment. The other structures are substantially the same as in the third embodiment. - The
voltage generating circuit 48 is formed of a diode-connectednMOS transistor 48 a and resistors R14, R15, and R16 that are connected in series between a power supply line VCC and a ground line VSS. The gate electrode and the drain electrode of thenMOS transistor 48 a are connected to the power supply line VCC, and the source electrode and the substrate thereof are connected to an end of the resistor R14. The connection node of the resistors R14, R15 is connected to the node ND04. The connection node of the resistors R15, R16 is connected to the node ND05. - The same effect as in the above-mentioned third embodiment can be obtained in this embodiment. Additionally, in this embodiment, the gradient of the I-V characteristic shown in FIG. 4 can be sharpened in the vicinity of the intersection of the current IDS1 of the
first transistor 14 and the current IDS2 of thesecond transistor 16 shown in FIG. 5. As a result, the ability of the reset signal RST to follow a change in the first and second voltages V1, V2 can be improved even more. - An example in which the resetting circuit is formed by the use of the
nMOS transistors - An example in which the present invention is applied to a SDRAM was described in the above embodiments. However, the invention is not limited to this example. For example, the present invention may be applied to a FCRAM (Fast Cycle RAM). Alternatively, the present invention may be applied to a microcomputer, a logic LSI, and a system LSI.
- This invention as a whole is also not limited to the above embodiments and various modifications may be made without departing from the spirit and scope of the invention. Any improvement may be made in part or all of the components.
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000317748A JP3703706B2 (en) | 2000-10-18 | 2000-10-18 | Reset circuit and semiconductor device having reset circuit |
JP2000-317748 | 2000-10-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020043994A1 true US20020043994A1 (en) | 2002-04-18 |
US6429705B1 US6429705B1 (en) | 2002-08-06 |
Family
ID=18796485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/820,714 Expired - Lifetime US6429705B1 (en) | 2000-10-18 | 2001-03-30 | Resetting circuit independent of a transistor's threshold |
Country Status (2)
Country | Link |
---|---|
US (1) | US6429705B1 (en) |
JP (1) | JP3703706B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2844118A1 (en) * | 2002-08-29 | 2004-03-05 | St Microelectronics Sa | An electronic circuit for detecting a supply potential as having a sufficient value after switching on, for use in integrated circuit devices such as chip cards |
US20040066218A1 (en) * | 2002-10-03 | 2004-04-08 | Koji Suzuki | Power-on reset circuit |
EP1501192A1 (en) * | 2003-07-21 | 2005-01-26 | Broadcom Corporation | Power-on reset circuit for use in low power supply voltage applications |
US20050140405A1 (en) * | 2003-12-30 | 2005-06-30 | Chang-Ho Do | Power-up circuit semiconductor memory device |
US20100156479A1 (en) * | 2008-12-22 | 2010-06-24 | Elpida Memory, Inc. | Power-on reset circuit and adjusting method therefor |
US8253452B2 (en) * | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US20150123719A1 (en) * | 2013-11-01 | 2015-05-07 | Canon Kabushiki Kaisha | Semiconductor device and method of controlling the same |
JP2019220884A (en) * | 2018-06-21 | 2019-12-26 | ラピスセミコンダクタ株式会社 | Semiconductor device and generation method for power-on reset signal |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6943596B2 (en) * | 2002-03-12 | 2005-09-13 | Broadcom Corporation | Power-on reset circuit for use in low power supply voltage applications |
ITRM20020322A1 (en) * | 2002-06-07 | 2003-12-09 | Micron Technology Inc | LOW VOLTAGE POWER DETECTOR. |
JP4021283B2 (en) | 2002-08-28 | 2007-12-12 | 富士通株式会社 | Semiconductor device |
JP2004304632A (en) * | 2003-03-31 | 2004-10-28 | Toshiba Corp | Power-on detector, and power-on reset circuit using the power-on detector |
KR100548557B1 (en) * | 2003-05-21 | 2006-02-02 | 주식회사 하이닉스반도체 | Internal voltage generator for semiconductor device |
KR100605594B1 (en) * | 2003-10-31 | 2006-07-28 | 주식회사 하이닉스반도체 | Power-up signal generation device |
JP4025286B2 (en) * | 2003-12-26 | 2007-12-19 | 東芝マイクロエレクトロニクス株式会社 | Semiconductor device |
KR100650816B1 (en) * | 2004-02-19 | 2006-11-27 | 주식회사 하이닉스반도체 | Internal circuit protection device |
KR100791075B1 (en) * | 2006-11-15 | 2008-01-03 | 삼성전자주식회사 | Power up reset circuit and semiconductor device comprising the same |
US7873854B2 (en) * | 2007-10-01 | 2011-01-18 | Silicon Laboratories Inc. | System for monitoring power supply voltage |
CN103746681B (en) * | 2013-12-24 | 2017-06-30 | 北京时代民芯科技有限公司 | A kind of upper and lower electricity output tri-state control circuit of cmos device power supply |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4446381A (en) * | 1982-04-22 | 1984-05-01 | Zilog, Inc. | Circuit and technique for initializing the state of bistable elements in an integrated electronic circuit |
US4634905A (en) * | 1985-09-23 | 1987-01-06 | Motorola, Inc. | Power-on-reset circuit having a differential comparator with intrinsic offset voltage |
US5115146A (en) * | 1990-08-17 | 1992-05-19 | Sgs-Thomson Microelectronics, Inc. | Power-on reset circuit for controlling test mode entry |
US5359233A (en) * | 1990-09-28 | 1994-10-25 | Dallas Semiconductor Corporation | Reset monitor for detection of power failure and external reset |
US5144159A (en) * | 1990-11-26 | 1992-09-01 | Delco Electronics Corporation | Power-on-reset (POR) circuit having power supply rise time independence |
US5530395A (en) * | 1995-04-03 | 1996-06-25 | Etron Technology Inc. | Supply voltage level control using reference voltage generator and comparator circuits |
KR100219501B1 (en) * | 1996-11-13 | 1999-09-01 | 윤종용 | Power-on-reset circuit |
-
2000
- 2000-10-18 JP JP2000317748A patent/JP3703706B2/en not_active Expired - Fee Related
-
2001
- 2001-03-30 US US09/820,714 patent/US6429705B1/en not_active Expired - Lifetime
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2844118A1 (en) * | 2002-08-29 | 2004-03-05 | St Microelectronics Sa | An electronic circuit for detecting a supply potential as having a sufficient value after switching on, for use in integrated circuit devices such as chip cards |
US20040066218A1 (en) * | 2002-10-03 | 2004-04-08 | Koji Suzuki | Power-on reset circuit |
US7482847B2 (en) * | 2002-10-03 | 2009-01-27 | Oki Electric Industry Co., Ltd. | Power-on reset circuit |
EP1501192A1 (en) * | 2003-07-21 | 2005-01-26 | Broadcom Corporation | Power-on reset circuit for use in low power supply voltage applications |
US20050140405A1 (en) * | 2003-12-30 | 2005-06-30 | Chang-Ho Do | Power-up circuit semiconductor memory device |
US8253452B2 (en) * | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US20100156479A1 (en) * | 2008-12-22 | 2010-06-24 | Elpida Memory, Inc. | Power-on reset circuit and adjusting method therefor |
US20150123719A1 (en) * | 2013-11-01 | 2015-05-07 | Canon Kabushiki Kaisha | Semiconductor device and method of controlling the same |
US9537484B2 (en) * | 2013-11-01 | 2017-01-03 | Canon Kabushiki Kaisha | Semiconductor device and method of controlling the same |
JP2019220884A (en) * | 2018-06-21 | 2019-12-26 | ラピスセミコンダクタ株式会社 | Semiconductor device and generation method for power-on reset signal |
JP7251929B2 (en) | 2018-06-21 | 2023-04-04 | ラピスセミコンダクタ株式会社 | Semiconductor device and power-on reset signal generation method |
Also Published As
Publication number | Publication date |
---|---|
JP3703706B2 (en) | 2005-10-05 |
JP2002124861A (en) | 2002-04-26 |
US6429705B1 (en) | 2002-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6429705B1 (en) | Resetting circuit independent of a transistor's threshold | |
US5640122A (en) | Circuit for providing a bias voltage compensated for p-channel transistor variations | |
JP3026474B2 (en) | Semiconductor integrated circuit | |
US7199623B2 (en) | Method and apparatus for providing a power-on reset signal | |
JP2007243178A (en) | Adjustable transistor body bias circuit network | |
US5757175A (en) | Constant current generating circuit | |
US7099223B2 (en) | Semiconductor memory device | |
US7212046B2 (en) | Power-up signal generating apparatus | |
US8183914B2 (en) | Constant Gm circuit and methods | |
KR20050041595A (en) | Device for generating power-up signal | |
KR100815184B1 (en) | Power up signal generator of semiconductor device | |
US20020003449A1 (en) | Semiconductor device enabling high-speed generation of internal power-supply potential at the time of power on | |
US8106689B2 (en) | Circuit for generating power-up signal of semiconductor memory apparatus | |
US20140375371A1 (en) | Semiconductor device for offset compensation of reference current | |
JP3868131B2 (en) | Back bias circuit | |
US20020017688A1 (en) | Semiconductor memory circuit | |
US7576575B2 (en) | Reset signal generator in semiconductor device | |
KR0152957B1 (en) | Ic memory device | |
US20090256598A1 (en) | Power-up signal generator of semiconductor memory apparatus and method for controlling the same | |
KR0172436B1 (en) | Reference voltage circuit for semiconductor device | |
US11720127B2 (en) | Amplifier and voltage generation circuit including the same | |
KR100554840B1 (en) | Circuit for generating a power up signal | |
JP2014134862A (en) | Semiconductor device | |
US20080094136A1 (en) | Amplifier circuit and method of generating bias voltage in amplifier circuit | |
KR100511906B1 (en) | Cmos inverter circuit with variable output signal transition level using floating gate transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FUJITSU LIMITED, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BANDO, YOSHIHIDE;UCHIDA, TOSHIYA;REEL/FRAME:011665/0386 Effective date: 20010316 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: FUJITSU MICROELECTRONICS LIMITED, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021998/0645 Effective date: 20081104 Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021998/0645 Effective date: 20081104 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024982/0245 Effective date: 20100401 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: SOCIONEXT INC., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:035507/0612 Effective date: 20150302 |