US6215339B1 - Input buffer circuit - Google Patents

Input buffer circuit Download PDF

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Publication number
US6215339B1
US6215339B1 US09/367,637 US36763799A US6215339B1 US 6215339 B1 US6215339 B1 US 6215339B1 US 36763799 A US36763799 A US 36763799A US 6215339 B1 US6215339 B1 US 6215339B1
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Prior art keywords
input
transistor
output
section
transistors
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US09/367,637
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English (en)
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Mats Hedberg
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Unwired Planet LLC
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Telefonaktiebolaget LM Ericsson AB
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Assigned to TELEFONAKTIEBOLAGET LM ERICSSON reassignment TELEFONAKTIEBOLAGET LM ERICSSON SEE RECORDING AT REEL 010405, FRAME 0737. Assignors: HEDBERG, MATS
Assigned to TELEFONAKTIEBOLAGET LM ERICSSON reassignment TELEFONAKTIEBOLAGET LM ERICSSON ASSIGNMENT OF ASSIGNOR'S INTEREST (RE-RECORD TO CORRECT THE RECORDATION DATE OF 8/17/99 TO 8/18/99 PREVIOUSLY RECORDED AT REEL 10297, FRAME 0269) Assignors: HEDBERG, MATS
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Assigned to CLUSTER LLC reassignment CLUSTER LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Definitions

  • the present invention relates to an input buffer circuit for receiving digital data signals from a transmission line according to the preamble of claim 1 .
  • An input buffer circuit of this kind is known from EP-A-0 504 060.
  • Digital circuits and technology are the key for systems with an ever increasing performance and functionality. This goes together with a continuously increasing scale of integration and an increase in the complexity of digital systems. Different sections of such systems communicate via impedance matched transmission lines which constitute an inexpensive and convenient means for carrying data rates in the order of several hundred Mbit/s over short and medium distances within a digital system.
  • a line driver circuit is required at the transmitting side of the transmission line in order to provide low impedance data signals.
  • the amplitude of these data signals is low, in order to keep the power transmitted over the transmission line with a given characteristic impedance, reasonably small.
  • an input buffer circuit is provided, for receiving the digital data signals and for outputting a corresponding digital signal to subsequent sections.
  • each input buffer circuit is provided which will consume operating power.
  • each input buffer could be individually connected to the power supply or disconnected from the power supply. This, however, would require special elements like jumpers or switches for allowing individual settings. Additional space would be required and the overall system reliability would be lower, and additional costs would arise in the process of manufacture.
  • an object of the present invention to provide an input buffer circuit for receiving digital data signals from a transmission line, wherein the circuit is very power efficient even if it is not currently being used in a specific system configuration.
  • this object is solved as defined in claim 1 .
  • the input buffer circuit monitors, whether data signals are present at its inputs. If data are detected, the input buffer circuit is switched into an operating state in order to receive the transmitted data and output the same. If no data are detected at the input of the buffer circuit, at least the portions not required for monitoring the presence of absence of input data and significantly contributing to the overall power consumption of the input buffer circuit, are switched into a standby mode with reduced power consumption or no power consumption at all.
  • means are provided for applying a predetermined potential to the output terminal of the input buffer circuit when in the standby state, in order to avoid unpredictable or undefined states in the subsequent digital circuitry.
  • the monitor section comprises an analogue multiplier circuit having first and second differential inputs and an output, as defined in claim 1 .
  • the operating or standby mode of the input buffer circuit is controlled by the output buffer connected to the transmitting side of the transmission line. If temporarily there are no data for the output buffer to be transmitted, the output buffer sets its outputs to equal potential, e.g. by means of switching off the power supply to the output buffer or by means of switching the outputs of the output buffer into a high impedance mode or disconnecting the outputs from the transmission line or by means of applying equal potential to the output terminals of the output buffer. At the receiving end of the transmission line, the input buffer will then switch into the low power standby mode, without the need to provide a separate signalling channel for power control.
  • FIG. 1 shows a block diagram of an embodiment of an input buffer circuit according to the present invention
  • FIG. 2 shows a schematic diagram of an embodiment of the monitor section of FIG. 1;
  • FIG. 3 shows a schematic diagram of an embodiment of the amplifier section and the power control section of the embodiment of FIG. 1 .
  • FIG. 1 shows a block diagram of an embodiment of an input buffer circuit according to the present invention.
  • reference numeral 1 denotes a monitor section for monitoring the availability of data to be received by the input buffer circuit.
  • Monitor section 1 comprises input terminals 11 and 12 and an output terminal MOUT for outputting the detection result.
  • Reference numeral 2 denotes an input amplifier section having a noninverting input terminal INP and an inverting input terminal INN for connection to a data transmission line.
  • Input amplifier section 2 receives the data signals transmitted via the transmission line and outputs a digital signal in correspondence with the received digital data signal at its output terminal OUT.
  • Reference numeral 4 denotes an optional termination impedance providing for proper termination of the characteristic impedance of the transmission line at the input terminals INP and INN.
  • Reference numeral 3 denotes a power control section provided in the input amplifier section 2 .
  • the power control section 3 receives the output signal MOUT from the monitor section 1 at a power control terminal PEN. In accordance with this signal, power control section 3 causes the amplifier section 2 to be either in an operating state when data are available at the input terminals INP, INN of the input amplifier 2 or causes the input amplifier 2 , to be in a low power standby state when no input data are available at INP, INN.
  • VCC and GND denote the power supply terminals of the input buffer circuit.
  • the monitor section 1 and the power control section 3 are immediately connected to VCC and GND.
  • the input amplifier section 2 receives its operating power through the power control section 3 .
  • the control signal MOUT output by the monitor section 1 may directly control constituent elements of the amplifier section 2 , e.g. switch on or off the current sources included in some or all of the signal amplification stages of the amplifier section 2 .
  • a preamplifier section (not shown) may be provided e.g. for increasing the common mode input range of the input buffer. Then, the inputs of the preamplifier are connected to the transmission line and the outputs of the preamplifier provide the signals INP, INN of FIG. 1 . In this case, the line termination impedance 4 , if provided, would not be provided across INP, INN but across the inputs of the preamplifier section.
  • FIG. 2 shows a schematic diagram of an embodiment of the monitor section of FIG. 1 .
  • reference numerals 11 and 12 denote the input terminals of the monitor section 1 .
  • This section comprises transistors T 1 to T 6 which are connected, to function as as an analogue multiplier circuit. Specifically, the sources of transistors T 5 and T 6 are connected together and to a current Source IS 1 .
  • This current source can e.g. be of cascode type and provides for the sum of the source currents of T 5 and T 6 being equal to I.
  • the gates of transistors T 5 and T 6 constitute a first differential input with input terminals 121 and 111 .
  • the sources of transistors T 1 and T 2 are connected together and to the drain of transistor T 5 .
  • the sources of transistors T 3 and T 4 are connected together and to the drain of transistor T 6 .
  • the drains of transistors T 1 and T 4 are connected together and via a first load circuit to VCC.
  • the drains of transistors T 2 and T 3 are connected together and via a second load circuit to VCC.
  • the first and the second load circuit respectively, is constituted by a transistor T 7 and T 8 , respectively, with a conductivity type opposite to the conductivity type of transistors T 1 to T 6 .
  • the gates of transistors T 7 and T 8 receive a reference voltage VREF which can be generated in a number of different ways, each of which is well known in the art.
  • the gates of transistors T 1 and T 3 are connected together and constitute a first input terminal 122 of a second differential input 122 , 112 of the analogue multiplier circuit.
  • the gates of transistors T 2 and T 4 are connected together and constitute the second input 112 of the second differential input 122 , 112 .
  • the first and the second differential input of the analogue multiplier circuit are connected such that the analogue multiplier circuit outputs a signal that depends on the absolute voltage difference across the inputs 11 , 12 of the monitor section 1 .
  • one input 111 of the first differential input 111 , 121 is connected with one input 112 of the second differential input 112 , 122 , thus constituting the first input 11 of the monitor section 1
  • the other input 121 of the first differential input is connected with the other input 122 of the second differential input 112 , 122 , thus constituting the second input terminal 12 of the monitor section 1 .
  • Reference numerals QA and QB denote output nodes of the analogue multiplier circuit. QA is connected to the drains of transistors T 7 , T 1 and T 4 whereas QB is connected to the drains of transistors T 8 , T 2 and T 3 . These out put nodes are connected with the inverting input and the noninverting input, respectively, of a comparator circuit OP.
  • This comparator circuit can be implemented in a large number of different ways, each of which is well known in the art.
  • C 1 and C 2 denote optional capacitances for smoothing the signals at the noninverting input and the inverting input, respectively, of the comparator circuit OP.
  • These capacitances can e.g. be implemented by means of exploiting the gate capacitance of MOS transistors, such that drain and source of a transistor element connected together, constitute one electrode of the capacitor, whereas the gate constitutes the other capacitor electrode. Of course, other implementations of these capacitances are feasible.
  • C 3 denotes an optional capacitor for absorbing transient voltage spikes resulting from the operation of this circuit.
  • the current I provided by current source IS 1 is split up among the first triple transistor group T 1 , T 2 , T 5 connected in a Y-configuration, and the second triple transistor group T 3 , T 4 , T 6 connected in a Y-configuration.
  • the split-up ratio depends on the voltage difference across the inputs 111 and 121 .
  • Each of the upper transistor pairs T 1 , T 2 and T 3 , T 4 respectively, splits up the current through the lower transistors T 5 and T 6 , respectively, of the respective triple transistor group depending on the voltage difference across the second differential input 112 , 122 .
  • the currents through the load elements T 7 and T 8 will be symmetrical if the voltage across the inputs 11 , 12 of the monitor section 1 is zero, i.e. if no data are available.
  • the current through load element T 7 will be larger than the current through load element T 8 , regardless the polarity of the voltage difference across the inputs 11 and 12 .
  • This difference in the currents through elements T 7 and T 8 results in a voltage difference across the nodes QA, QB. If this voltage difference exceeds a given threshold, the comparator circuit OP switches its output to indicate that data are present across the input terminals 11 , 12 .
  • Setting of the predetermined threshold can be performed in a number of different ways.
  • One possibility is, to provide the comparator circuit with a predetermined input offset voltage such that switching of the output MOUT takes place if the voltage difference across QA, QB reaches a predetermined value.
  • the circuit including the transistors T 1 to T 8 can be designed symmetrical with regard to the electrical characteristics of the components involved.
  • the comparator circuit OP is designed such that the output MOUT of the comparator switches if the voltage difference across its inputs crosses zero.
  • a predetermined threshold for switching the output signal at MOUT can be provided by means of designing the first triple transistor group T 1 , T 2 , T 5 and the second triple transistor group T 3 , T 4 , T 6 such that the electrical characteristics of the transistors within at least one triple group are nonsymmetric, or such that the electrical characteristics of transistors T 7 , T 8 are nonsymmetric or both.
  • the predetermined threshold can be adjusted by means of appropriately setting the ratio of the channel width or length of transistors T 1 and T 2 or by means of setting the ratio of the channel width or length of transistors T 3 and T 4 or both.
  • the current through load element T 7 will be smaller than the current through load element T 8 , given the voltage difference between terminals 11 and 12 is zero. In this way it can be achieved that the potential difference across the nodes QA and QB crosses zero only if the absolute voltage difference across input terminals 11 and 12 of the monitor section 1 reaches a predetermined threshold value.
  • the channel geometries of transistors T 7 , T 8 can be made different from each other in order to achieve that the potential difference across the nodes QA and QB crosses zero when the absolute voltage difference between input terminals 11 and 12 of the monitor section 1 reaches a predetermined threshold value. If the channel width of T 7 is provided larger than the channel width of T 8 , the potential of QA will be higher than the potential of QB, if the voltage difference across the inputs 11 , 12 is zero, even if both triple transistor groups comprising the transistors T 1 to T 6 are symmetric.
  • a further possibility for providing said threshold is to connect a shunt from QB to GND or to the source of T 6 or from QA to VCC.
  • a shunt may be implemented by means of a resistor or transistor (not shown).
  • Capacitors C 1 , C 2 , C 3 are optional and serve to suppress transient potential changes at the nodes QA, QB due to polarity changes across the input terminals 11 , 12 .
  • the signalling voltage difference across the input terminals of amplifier section 2 will change its sign in accordance with the transmitted stream of bits. Changing sign involves zero crossings of the voltage difference across terminals 11 and 12 of the monitor circuit 1 , this in turn resulting in transients in the potential difference between QA and QB. Since these transients are short, they can be suppressed by means of designing the comparator OP to have a sufficiently slow response time. In this specific embodiment, this is achieved by means of providing the capacitors C 1 to C 3 . In this way, the output signal MOUT of the comparator OP will remain stable also during the zero crossings of the data signal across the input terminals 11 , 12 of the monitor section 1 .
  • FIG. 3 shows a schematic diagram of an embodiment of the amplifier section and the power control section of the embodiment of FIG. 1 .
  • T 9 and T 10 denote transistors constituting a differential input stage of the amplifier section 2 .
  • the sources of transistors T 9 and T 10 are connected together and to a constant current source IS 2 .
  • the other terminal of the constant current IS 2 is connected to ground GND.
  • Each of the transistors T 9 and T 10 has its drain connected with a current source IS 3 and IS 4 , respectively.
  • the terminals of IS 3 and IS 4 not connected to transistors T 9 , T 10 are connected to the power supply potential VCC.
  • the current sources IS 3 and IS 4 can be implemented by means of a current mirror.
  • a first MOS transistor (not shown) with a conducting type opposite to transistor T 9 , is provided in the drain path of transistor T 9
  • a second transistor (not shown) with a conducting type opposite to transistor T 10 , is provided in the drain path of transistor T 10 .
  • the gates of these first and second transistors are connected together and with the drain of T 9 .
  • Transistors T 11 , T 12 constitute an inverting driver stage.
  • T 11 has a conductivity type opposite to T 12 .
  • the gates of transistors T 11 and T 12 are both connected with the drain of transistor T 10 .
  • the source of transistor T 11 is connected to VCC and the drain of transistor T 11 is connected to the drain of transistor T 12 .
  • Transistors T 13 and T 14 constitute the output stage of the amplifier section 2 .
  • T 13 has a conductivity type opposite to T 14 .
  • the gates of these transistors T 13 , T 14 are both connected to a node between the drain of transistor T 11 and the drain of transistor T 12 .
  • the source of transistor T 13 is connected to VCC while the drain of transistor T 13 is connected to the drain of transistor T 14 .
  • the drain of transistor T 13 and the drain of transistor T 14 constitute the output node of the amplifier section 2 which is connected with the output terminal OUT.
  • Transistors T 15 and T 16 constitute the power control section 3 of the amplifier section 2 .
  • the drain of transistor T 16 is connected to the source of transistor T 12 and to the source of transistor T 14 .
  • the source of transistor T 16 is connected to ground.
  • Transistor T 15 has a conductivity type opposite to the conductivity type of transistor T 16 .
  • the drain of transistor T 15 is connected to the output terminal OUT whereas the source of transistor T 15 is connected to VCC.
  • the gate of transistor T 15 and the gate of transistor T 16 are connected together and to the power control input terminal PEN of the power control section 3 . As shown in FIG. 1, this power control input terminal PEN is connected with the power control output terminal MOUT of the monitor section 1 .
  • the input stage constituted by transistors T 9 and T 10 , together with the constant current sources IS 2 , IS 3 and IS 4 , provides a differential input amplifier. Due to the provision of the constant current sources IS 3 , IS 4 in the drain paths of the transistors T 9 , T 10 , this input stage has a high voltage amplification and provides a digital signal at the drain of transistor T 10 depending on whether the input voltage difference across the input terminals INP, INN is positive or negative.
  • the drain voltage signal of transistor T 10 is amplified and inverted by the driver stage consisting of transistors T 11 , T 12 , provided that the power control input signal PEN is at high potential and renders transistor T 16 conducting.
  • the drain of transistor T 12 and the drain of transistor T 11 provide a low impedance signal suitable for driving the gates of transistors T 13 and T 14 . Then a high speed digital signal with a sufficiently high slew rate is provided at the drain of T 14 and at the drain of T 13 . Due to PEN being at high potential, transistor T 15 is switched off.
  • the monitor section If the monitor section now detects, that no data are available at its input, the output MOUT of the monitor section 1 , and accordingly the power control input PEN of power control section 3 changes to a low potential. This results in transistor T 16 switching off and transistor T 15 switching on. As a consequence, neither the driving stage consisting of transistors T 11 , T 12 nor the output stage comprising the transistors T 13 , T 14 , receives operating power but enters a low power standby state. At the same time, transistor T 15 pulls the output terminal OUT up to high potential, in order to keep the potential of the output terminal OUT well defined.
  • the stages of the amplifier section 2 and current sources IS 2 , IS 3 and IS 4 can be implemented in different ways each of which is well known in the art.
  • the power control signal PEN may enable or disable any or all of the current sources IS 2 to IS 4 of the amplifier section 2 .
  • transistor T 15 may be replaced by a transistor (not shown) of the same conductivity type as transistor T 12 .
  • the source of this transistor (not shown) would then be connected to ground and its drain would then be connected to the output terminal OUT.
  • Transistor T 16 would then be provided with opposite conductivity type and in the source paths of transistors T 11 , T 13 .
  • the sources of transistors T 12 , T 14 would then be connected to ground GND, and the power control signal PEN would be inverted.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
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US09/367,637 1997-02-21 1998-02-19 Input buffer circuit Expired - Lifetime US6215339B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19706985A DE19706985B4 (de) 1997-02-21 1997-02-21 Eingangspufferschaltkreis
DE19706985 1997-02-21
PCT/EP1998/000954 WO1998037632A1 (en) 1997-02-21 1998-02-19 Input buffer circuit

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US (1) US6215339B1 (de)
EP (1) EP0960476B1 (de)
JP (1) JP3967386B2 (de)
AT (1) ATE218768T1 (de)
AU (1) AU6721898A (de)
DE (2) DE19706985B4 (de)
TW (1) TW370753B (de)
WO (1) WO1998037632A1 (de)

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US6300816B1 (en) * 2000-10-24 2001-10-09 Rosun Technologies, Inc. Feedforward-controlled sense amplifier
US6437604B1 (en) * 2001-03-15 2002-08-20 Micron Technology, Inc. Clocked differential cascode voltage switch with pass gate logic
US6445218B1 (en) * 2000-07-20 2002-09-03 Hyundai Electronics Industries Co., Ltd. Comparator with offset voltage
US6504404B2 (en) * 2001-04-18 2003-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US6717440B2 (en) 2001-01-22 2004-04-06 Micron Technology, Inc. System and method for improving signal propagation
US20040268167A1 (en) * 2003-06-30 2004-12-30 Harry Muljono Low power differential link interface methods and apparatuses
US20050218980A1 (en) * 2004-03-31 2005-10-06 Analog Devices, Inc. Differential stage voltage offset trim circuitry
US20050237835A1 (en) * 2004-04-23 2005-10-27 Macronix International Co., Ltd. Circuit and method for high speed sensing
US20050285671A1 (en) * 2004-06-23 2005-12-29 Chun-Hung Chang Amplifier circuit with reduced power-off transients and method thereof
US20060012405A1 (en) * 2004-07-19 2006-01-19 Martins Marcus M Dual polarity, high input voltage swing comparator using MOS input transistors
CN100571025C (zh) * 2004-03-31 2009-12-16 模拟设备股份有限公司 差分级电压偏置微调电路
US20120007655A1 (en) * 2009-09-29 2012-01-12 Sanyo Semiconductor Co., Ltd. Input/output circuit
US20130175861A1 (en) * 2012-01-06 2013-07-11 Analog Devices, Inc. Control option combining a power-down signal with an analog input signal
US20180337642A1 (en) * 2017-05-19 2018-11-22 Novatek Microelectronics Corp. Operational amplifier circuit capable of improving linearity relation between loading current and input voltage difference
US10224886B2 (en) 2017-05-19 2019-03-05 Novatek Microelectronics Corp. Operational amplifier circuit using variable bias control

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US9331654B2 (en) * 2012-03-26 2016-05-03 Marvell World Trade Ltd. Dual squelch detectors and methods for low power states
JP6471619B2 (ja) * 2015-06-12 2019-02-20 株式会社デンソー 電子装置
CN112702320A (zh) * 2020-12-10 2021-04-23 成都新赢科技有限公司 一种监控数据传输筛分系统及其使用方法

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EP0960476A1 (de) 1999-12-01
DE19706985A1 (de) 1998-09-03
WO1998037632A1 (en) 1998-08-27
ATE218768T1 (de) 2002-06-15
JP3967386B2 (ja) 2007-08-29
TW370753B (en) 1999-09-21
DE19706985B4 (de) 2004-03-18
AU6721898A (en) 1998-09-09
JP2001511987A (ja) 2001-08-14
DE69805759D1 (de) 2002-07-11
EP0960476B1 (de) 2002-06-05

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