US5416748A - Semiconductor memory device having dual word line structure - Google Patents

Semiconductor memory device having dual word line structure Download PDF

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Publication number
US5416748A
US5416748A US08/132,343 US13234393A US5416748A US 5416748 A US5416748 A US 5416748A US 13234393 A US13234393 A US 13234393A US 5416748 A US5416748 A US 5416748A
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sub
word
word line
node
power
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Mamoru Fujita
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Renesas Electronics Corp
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NEC Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the present invention relates to a semiconductor memory device and, more particularly, to an improvement in a dynamic random access memory device having a dual word line structure including main-word and sub-word lines.
  • a semiconductor memory device having a plurality of word lines, one of which is selected and energized to an active level.
  • each of the word lines is inevitably prolonged to have a relatively large stray resistance.
  • the word line is thereby required to be made of a metal to reduce its resistance.
  • a pitch for the word line is reduced. This means that the pitch for metal wiring is considerably made small, so that the increase in memory capacity is restricted. In other words, it is difficult to construct a memory device having a large memory capacity such as 64-Mb or 256-Mb with a conventional word line structure.
  • Such a memory device having a dual word line structure was proposed in "1992 SYMPOSIUM ON VLSI CIRCUITS", Digest of Technical Papers, pp. 112-113, entitled “A Boosted Dual Word-line Decoding Scheme for 256 Mb DRAMs”.
  • the memory device proposed therein has a plurality of main-word lines each made of a metal and a plurality of sub-word lines each made of polysilicon and serving also as gates of memory transistors connected thereto. One of the main-word lines is selected and driven by a row decoder in response to a part of row address signals.
  • Each of the sub-word lines is connected to an output node of an associated one of sub-word drivers each further including an input node connected to an associated main-word line and a power node.
  • the sub-word drivers arranged in the same column are connected at the power nodes thereof in common to an associated one of word drive decoders.
  • Each of the word drive decoders responding to another part of row address signals to output and supply an energizing voltage to the power nodes of associated ones of the sub-word drivers. Accordingly, the sub-word driver drives the associated sub-word line to an active level in response to a selection level of the associated main-word line and to the energizing voltage from the associated word drive decoder.
  • a memory device having a lager memory capacity such as 64-Mb or 256-Mb can be constructed without increase in chip area.
  • each word drive decoder has a remarkably large stray capacitance and is required to charge and discharge such a large capacitance in each data reading or writing cycle. The power consumption is thus made large and an operation speed is lowered.
  • a semiconductor memory device comprises a plurality of memory array blocks, each of the memory array blocks including at least one main-word line, a plurality of sub-word lines, a plurality of sub-word drivers each having an input node connected to the main-word line, an output node connected to an associated one of the sub-word lines and a power node and responding to an active level of the main-word line to drive the associated sub-word line with a power voltage supplied to the power node thereof, and a decoding unit for, when activated, supplying the power voltage to the power nodes of the sub-word drivers, and the decoding unit in one of the memory array blocks being activated in response to address information.
  • FIG. 1 is a block diagram illustrative of a memory device according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram illustrative of a sub-word driver shown in FIG. 1;
  • FIG. 3 is a circuit diagram illustrative of a word drive decoder shown in FIG. 1;
  • FIG. 4 is a circuit diagram illustrative of a block decoder shown in FIG. 1;
  • FIG. 5 is a circuit diagram illustrative of a sub-word drive decoder shown in FIG. 1;
  • FIG. 6 is a block diagram illustrative of a memory device according to another embodiment of the present invention.
  • a semiconductor memory device is constructed as a dynamic random access memory and includes a plurality of memory array blocks 1--1 to l-j. Since each of the memory array blocks has the same construction as one another, only the memory array block 1--1 is shown in the drawing and will be explained in detail below.
  • the memory array block 1--1 includes a plurality of main-word lines MWL-1 to MWL-n arranged in a plurality of rows which are in turn connected to a row decoder 10.
  • This decoder 10 responds to a part of row address signal information ADI and selects and drives one of the main-word lines MWL to an active high level.
  • SWD sub-word drivers
  • Each of the sub-word drivers 20 has an input node IN connected to an associated one of the main-word lines MWL, an output node ON connected to an associated sub-word line SWL and a power node PN.
  • the sub-word driver (SWD) 20 includes an inverter 21 having an input connected to the input node IN and P-channel and N-channel MOS transistors 22 and 23 having a gate connected to the output of the inverter 21.
  • the transistors 22 and 23 are connected in series between the power node PN and a ground terminal GND, the connection point thereof is lead out as the output node ON which is in turn connected to the sub-word line SWL.
  • each of the sub-word drivers SWD may have the same construction as that disclosed in the above mentioned reference.
  • the memory array block 1 further includes a plurality of bit line pairs BL and BL intersecting the sub-word lines SWL.
  • a plurality of memory cells MC consisting of one transistor and one capacitor are disposed at different ones of the intersections of the sub-word lines and the bit line pair.
  • Each bit line pair are connected to an associated one of sense amplifiers (SA) 30 in a manner as well known in the art.
  • SA sense amplifier
  • the memory array block further includes a plurality of word drive decoders (WDD) 50 provided correspondingly to each column of the sub-word driver (SWD) array.
  • Each of the word drive decoders 50 has a first power output node PO1 connected in common to the power nodes PN of the odd-numbered ones of the sub-word drivers arranged in the same associated column, a second power output node PO2 connected in common to the power nodes PN of the even-numbered ones thereof.
  • the word drive decoder 50 further has first, second and third address input nodes AI1, AI2 and AI3.
  • each of the word drive decoder (WDD) 50 includes two NAND gates 51 and 511, two inverters 52 and 521, six P-channel MOS transistors 54-56 and 541-561 and six N-channel MOS transistors 57-59 and 571-591 which are connected as shown. Therefore, when the address input node AI1 takes an active high level and the address input node AI2 (or AI3) takes the active high level, the output node PO1 (or PO2) takes a potential level substantially equal to a power voltage V applied to the transistor 56 (561). In the case of the address input node AI1 taking the inactive low level, on the other hand, both of the output nodes PO1 and PO2 takes the ground level irrespective of the contents of the remaining address input nodes AI2 and AI3.
  • the memory array block 1 further includes a block decoder (BD) 40 having an address output node AO1 connected in common to the first address input node AI1 of the word drive decoder 50.
  • the block decoder 40 responds to another part of the address information ADII and changes the its output node AO1 to the active high level.
  • the memory device shown FIG. 1 further includes a plurality of sub-word driver decoders (SDD) 60 provided correspondingly to associated one of the word drive decoders 50 in each of the memory array blocks.
  • SDD sub-word driver decoders
  • Each of the sub-word drive decoders 60 includes first and second address output nodes AO2 and AO3 which are in turn connected respectively to the address input nodes AI2 and AI3 of the associated word drive decoder 50.
  • the sub-word drive decoder 50 responds to still another part of the address information ADIII to change one of the its output nodes AO2 and AO3.
  • the block decoder 40 includes a NAND gate 41 and an inverter 42 which are connected as shown. Accordingly, if all the address inputs takes the high level, the output node AO1 takes the active high level.
  • each of the sub-word drive decoders 60 includes two NAND gates 61 and 63 and two inverters 62 and 64 to produce the address outputs AO2 and AO3.
  • the row decoder 10 in each memory array block selects and drives one of the main-word lines MWD in response to the address information ADI which is derived from a set of row address signals (not shown). Further derived from the set of row address signals are the address information ADII and ADIII.
  • the address information ADII is supplied to the block decoder 40 in each memory array block, so that only one block decoder 40 changes the its output node AO1 to the active high level.
  • all the sub-word drive decoders 60 changes one of its output nodes AO2 and AO3 to the active high level in response to the address information ADIII.
  • each of the word drive decoders 50 in the memory array block 1--1 drives and charges the line between the power output node PO1 and power input node PN to the power voltage V and drives and discharges the other line between the power output node PO2 and power input node PN to the ground level.
  • the charging and discharging current are relatively small to suppress the power consumption.
  • the time required to charge and discharge the power line is also made small to perform a high speed operation.
  • the sub-word drivers arranged in the first column drive the corresponding sub-word lines SWL to the power voltage V.
  • the memory cells connected to the sub-word lines SWL thus selected are subjected to a data read operation or a data write operation.
  • the memory device has a large memory capacity and operates at a high speed with low power consumption.
  • each of the memory array blocks 1--1 to 1-j includes a block and sub-word drive decoder (BSDD) 700 in place of the block decoder 40 in FIG. 1.
  • the sub-word drive decoders 60 of FIG. 1 are further omitted in the present embodiment.
  • the block and sub-word drive decoder 700 performs the functions of the block decoder and sub-word drive decoder.
  • the address information containing the address information ADII and AD III is supplied to the decoder 700.
  • the required chip area is further reduced because of the absence of the decoders 60.
  • the present invention is not limited to the above embodiments but may be modified and changed without departing from the scope and spirit of the invention.
  • the number of sub-word lines provided between the adjacent two word lines and arranged in the same column may be increased to four or more.
  • the word drive decoder and the block decoder (block and sub-word drive decoder) can be proved every main-word line.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
US08/132,343 1992-10-06 1993-10-06 Semiconductor memory device having dual word line structure Expired - Lifetime US5416748A (en)

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JP4-266961 1992-10-06
JP4266961A JP2812099B2 (ja) 1992-10-06 1992-10-06 半導体メモリ

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KR (1) KR970000883B1 (ko)
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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587959A (en) * 1995-01-10 1996-12-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US5587960A (en) * 1994-11-15 1996-12-24 Sgs-Thomson Microelectronics Limited Integrated circuit memory device with voltage boost
US5663923A (en) * 1995-04-28 1997-09-02 Intel Corporation Nonvolatile memory blocking architecture
US5706245A (en) * 1994-12-15 1998-01-06 Samsung Electronics Co., Ltd. Word line decoding circuit of a semiconductor memory device
US5708620A (en) * 1996-04-04 1998-01-13 Lg Semicon Co., Ltd Memory device having a plurality of bitlines between adjacent columns of sub-wordline drivers
US5734614A (en) * 1995-06-08 1998-03-31 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device using sense amplifier as cache memory
US5761148A (en) * 1996-12-16 1998-06-02 Cypress Semiconductor Corp. Sub-word line driver circuit for memory blocks of a semiconductor memory device
US5764585A (en) * 1995-06-07 1998-06-09 Nec Corporation Semiconductor memory device having main word lines and sub word lines
US5815457A (en) * 1995-06-26 1998-09-29 Sgs-Thomson Microelectronics S.R.L. Bit line selection decoder for an electronic memory
US5835439A (en) * 1995-12-08 1998-11-10 Hyundai Electronics Industries Co., Ltd. Sub word line driving circuit and a semiconductor memory device using the same
US5862098A (en) * 1996-09-17 1999-01-19 Lg Semicon Co., Ltd. Word line driver circuit for semiconductor memory device
US5867721A (en) * 1995-02-07 1999-02-02 Intel Corporation Selecting an integrated circuit from different integrated circuit array configurations
US5999480A (en) * 1995-04-05 1999-12-07 Micron Technology, Inc. Dynamic random-access memory having a hierarchical data path
US6084808A (en) * 1997-11-25 2000-07-04 Samsung Electronics Co., Ltd. Circuits and methods for burn-in of integrated circuits using potential differences between adjacent main word lines
US6104630A (en) * 1995-06-08 2000-08-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor storage device having spare and dummy word lines
US6118722A (en) * 1995-12-04 2000-09-12 Samsung Electronics, Co., Ltd. Integrated circuit memory device
US6188628B1 (en) * 1999-04-13 2001-02-13 Matsushita Electric Industrial Co., Ltd. Semiconductor storage device
US6246631B1 (en) 1999-06-29 2001-06-12 Hyundai Electronics Industries Co., Ltd. Semiconductor memory device
US6259642B1 (en) * 1999-08-09 2001-07-10 Samsung Electronics Co., Ltd. Semiconductor memory device with reduced sensing noise and sensing current
US6469947B2 (en) 1999-06-29 2002-10-22 Hyundai Electronics Co., Ltd. Semiconductor memory device having regions with independent word lines alternately selected for refresh operation
US6545923B2 (en) 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
US20040190362A1 (en) * 2001-03-29 2004-09-30 Kohji Hosokawa Dram and access method
US20080112253A1 (en) * 2006-11-09 2008-05-15 Jae-Youn Youn Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
US10332586B1 (en) * 2017-12-19 2019-06-25 Micron Technology, Inc. Apparatuses and methods for subrow addressing
KR20210018144A (ko) 2019-08-09 2021-02-17 도쿄엘렉트론가부시키가이샤 배치대 및 기판 처리 장치

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KR100204542B1 (ko) * 1995-11-09 1999-06-15 윤종용 멀티 서브워드라인 드라이버를 갖는 반도체 메모리장치
US5640338A (en) * 1995-12-07 1997-06-17 Hyundai Electronics Industries Co. Ltd. Semiconductor memory device
GB2348724B (en) * 1995-12-08 2000-11-22 Hyundai Electronics Ind A semiconductor memory device
KR100253277B1 (ko) * 1997-02-19 2000-05-01 김영환 계층적워드라인구조
US6452858B1 (en) * 1999-11-05 2002-09-17 Hitachi, Ltd. Semiconductor device
JP4757373B2 (ja) * 2000-07-24 2011-08-24 エルピーダメモリ株式会社 半導体記憶装置及びそのメモリセルアクセス方法
DE10128254B4 (de) * 2001-06-11 2016-09-01 Polaris Innovations Ltd. Integrierter Speicher mit einem Speicherzellenfeld mit mehreren Segmenten und Verfahren zu seinem Betrieb
KR100704039B1 (ko) * 2006-01-20 2007-04-04 삼성전자주식회사 디코딩 신호가 워드라인 방향으로 버싱되는 반도체 메모리장치

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Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587960A (en) * 1994-11-15 1996-12-24 Sgs-Thomson Microelectronics Limited Integrated circuit memory device with voltage boost
US5706245A (en) * 1994-12-15 1998-01-06 Samsung Electronics Co., Ltd. Word line decoding circuit of a semiconductor memory device
US5587959A (en) * 1995-01-10 1996-12-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US5867721A (en) * 1995-02-07 1999-02-02 Intel Corporation Selecting an integrated circuit from different integrated circuit array configurations
US5999480A (en) * 1995-04-05 1999-12-07 Micron Technology, Inc. Dynamic random-access memory having a hierarchical data path
US5663923A (en) * 1995-04-28 1997-09-02 Intel Corporation Nonvolatile memory blocking architecture
US5764585A (en) * 1995-06-07 1998-06-09 Nec Corporation Semiconductor memory device having main word lines and sub word lines
US5734614A (en) * 1995-06-08 1998-03-31 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device using sense amplifier as cache memory
US6404661B2 (en) 1995-06-08 2002-06-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor storage device having arrangement for controlling activation of sense amplifiers
US6104630A (en) * 1995-06-08 2000-08-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor storage device having spare and dummy word lines
US5815457A (en) * 1995-06-26 1998-09-29 Sgs-Thomson Microelectronics S.R.L. Bit line selection decoder for an electronic memory
DE19650303B4 (de) * 1995-12-04 2005-09-15 Samsung Electronics Co., Ltd., Suwon Integrierte Speicherschaltung
US6118722A (en) * 1995-12-04 2000-09-12 Samsung Electronics, Co., Ltd. Integrated circuit memory device
DE19655409B4 (de) * 1995-12-08 2009-11-12 Hynix Semiconductor Inc., Icheon Halbleiterspeichervorrichtung
US5835439A (en) * 1995-12-08 1998-11-10 Hyundai Electronics Industries Co., Ltd. Sub word line driving circuit and a semiconductor memory device using the same
DE19650715B4 (de) * 1995-12-08 2007-06-06 Hynix Semiconductor Inc., Ichon Unterwortleitungstreiberschaltung und diese verwendende Halbleiterspeichervorrichtung
US5708620A (en) * 1996-04-04 1998-01-13 Lg Semicon Co., Ltd Memory device having a plurality of bitlines between adjacent columns of sub-wordline drivers
DE19733396B4 (de) * 1996-09-17 2007-05-03 Lg Semicon Co. Ltd., Cheongju Wortleitungstreiberschaltung für Halbleiterspeicherbauelement
US5862098A (en) * 1996-09-17 1999-01-19 Lg Semicon Co., Ltd. Word line driver circuit for semiconductor memory device
US5761148A (en) * 1996-12-16 1998-06-02 Cypress Semiconductor Corp. Sub-word line driver circuit for memory blocks of a semiconductor memory device
US6084808A (en) * 1997-11-25 2000-07-04 Samsung Electronics Co., Ltd. Circuits and methods for burn-in of integrated circuits using potential differences between adjacent main word lines
US6188628B1 (en) * 1999-04-13 2001-02-13 Matsushita Electric Industrial Co., Ltd. Semiconductor storage device
US6246631B1 (en) 1999-06-29 2001-06-12 Hyundai Electronics Industries Co., Ltd. Semiconductor memory device
US6469947B2 (en) 1999-06-29 2002-10-22 Hyundai Electronics Co., Ltd. Semiconductor memory device having regions with independent word lines alternately selected for refresh operation
US6259642B1 (en) * 1999-08-09 2001-07-10 Samsung Electronics Co., Ltd. Semiconductor memory device with reduced sensing noise and sensing current
US20040190362A1 (en) * 2001-03-29 2004-09-30 Kohji Hosokawa Dram and access method
US6925028B2 (en) 2001-03-29 2005-08-02 International Business Machines Corporation DRAM with multiple virtual bank architecture for random row access
US6545923B2 (en) 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
US20080112253A1 (en) * 2006-11-09 2008-05-15 Jae-Youn Youn Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
US7729195B2 (en) 2006-11-09 2010-06-01 Samsung Electronics Co., Ltd. Semiconductor memory device having split word line driver circuit with layout patterns that provide increased integration density
US10332586B1 (en) * 2017-12-19 2019-06-25 Micron Technology, Inc. Apparatuses and methods for subrow addressing
US10438653B2 (en) 2017-12-19 2019-10-08 Micron Technology, Inc. Apparatuses and methods for subrow addressing
US10839890B2 (en) 2017-12-19 2020-11-17 Micron Technology, Inc. Apparatuses and methods for subrow addressing
KR20210018144A (ko) 2019-08-09 2021-02-17 도쿄엘렉트론가부시키가이샤 배치대 및 기판 처리 장치

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KR940010103A (ko) 1994-05-24
DE69326310D1 (de) 1999-10-14
JP2812099B2 (ja) 1998-10-15
EP0600184A2 (en) 1994-06-08
JPH06119781A (ja) 1994-04-28
EP0600184A3 (en) 1995-05-31
KR970000883B1 (ko) 1997-01-20
DE69326310T2 (de) 2000-02-03
EP0600184B1 (en) 1999-09-08

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