US5229331A - Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology - Google Patents

Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology Download PDF

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US5229331A
US5229331A US07/837,453 US83745392A US5229331A US 5229331 A US5229331 A US 5229331A US 83745392 A US83745392 A US 83745392A US 5229331 A US5229331 A US 5229331A
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Prior art keywords
cathode
layer
tip
gate
depositing
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Expired - Lifetime
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US07/837,453
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English (en)
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Trung T. Doan
J. Brett Rolfson
Tyler A. Lowrey
David A. Cathey
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Micron Technology Inc
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Micron Technology Inc
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Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CATHEY, DAVID A., DOAN, TRUNG T., LOWREY, TYLER A., ROLFSON, J. BRETT
Priority to DE4304103A priority patent/DE4304103C2/de
Priority to JP4716293A priority patent/JP2836802B2/ja
Priority to US08/053,794 priority patent/US5372973A/en
Publication of US5229331A publication Critical patent/US5229331A/en
Application granted granted Critical
Priority to US08/300,616 priority patent/US5696028A/en
Priority to US08/918,766 priority patent/US5831378A/en
Priority to US08/949,931 priority patent/US6066507A/en
Priority to JP1069298A priority patent/JP3098483B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/304—Field emission cathodes
    • H01J2201/30403—Field emission cathodes characterised by the emitter shape
    • H01J2201/30426—Coatings on the emitter surface, e.g. with low work function materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/319—Circuit elements associated with the emitters by direct integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2209/00—Apparatus and processes for manufacture of discharge tubes
    • H01J2209/02—Manufacture of cathodes
    • H01J2209/022—Cold cathodes
    • H01J2209/0223—Field emission cathodes
    • H01J2209/0226—Sharpening or resharpening of emitting point or edge

Definitions

  • This invention relates to field emission devices, and more particularly to processes for creating gate structures which are self-aligned to the emitter tips using chemical mechanical planarization (CMP).
  • CMP chemical mechanical planarization
  • Cathode ray tube (CRT) displays such as those commonly used in desk-top computer screens, function as a result of a scanning electron beam from an electron gun, impinging on phosphors on a relatively distant screen.
  • the electrons increase the energy level of the phosphors.
  • the phosphors return to their normal energy level, they release the energy from the electrons as a photon of light, which is transmitted through the glass screen of the display to the viewer.
  • a display panel comprising a transparent gas-tight envelope, two main planar electrodes which are arranged within the gas-tight envelope parallel with each other, and a cathodeluminescent panel.
  • One of the two main electrodes is a cold cathode, and the other is a low potential anode, gate, or grid.
  • the cathode luminescent panel may consist of a transparent glass plate, a transparent electrode formed on the transparent glass plate, and a phosphor layer coated on the transparent electrode.
  • the phosphor layer is made of, for example, zinc oxide which can be excited with low energy electrons.
  • a potential source is provided with its positive terminal connected to the gate, or grid, and its negative terminal connected to the emitter electrode (cathode conductor substrate).
  • the potential source may be made variable for the purpose of controlling the electron emission current.
  • An array of points in registry with holes in low potential anode grids are adaptable to the production of cathodes subdivided into areas containing one or more tips from which areas emissions can be drawn separately by the application of the appropriate potentials thereto.
  • the clarity, or resolution, of a field emission display is a function of a number of factors, including emitter tip sharpness, alignment and spacing of the gates, or grid openings, which surround the tips, pixel size, as well as cathode-to-gate and cathode-to-screen voltages. These factors are also interrelated.
  • the voltage required for electron emission from the emitter tips is a function of both cathode-to-gate spacing and tip sharpness.
  • One advantage of the disclosed process is that very narrow cathode-to-gate spacing is possible, which permits the use of threshold voltages that are at least an order of magnitude lower than those previously reported. Since emitted current is proportional to the difference of the applied emitter-to-gate voltage and the emission threshold voltage, for any given emitter-to-gate voltage, a lowered threshold voltage will result in greater current.
  • the object of the present invention is create an improved self-aligned process for fabricating field emission displays.
  • the disclosed process utilizes multiple, selectively etchable dielectric layers in combination with chemical mechanical planarization to create ultra-fine gate-to-tip spacing which results in emission threshold voltages that are at least an order of magnitude lower than those previously reported in the literature. Since emitted current is proportional to the difference of the applied emitter-to-gate voltage and the emission threshold voltage, for any given emitter-to-gate voltage, a lowered threshold voltage will result in greater current.
  • FIG. 1 is a cross-sectional schematic drawing of a flat panel display showing an electron emission tip, or field emission cathode, surrounded by the self-aligned gate structures formed using the process of the present invention.
  • FIG. 2 shows an electron emitter tip having a conformal insulating layer and a flowable insulating layer deposited thereon, according to the present invention.
  • FIG. 3 shows the electron emitting tip of FIG. 2 following the reflow heating of the flowable insulating layer, at approximately 1000° C., according to the present invention.
  • FIG. 4 shows the electron emitting tip of FIG. 3 after the conductive gate layer has been deposited thereon, according to the present invention.
  • FIG. 5 shows the electron emitter tip of FIG. 4 after a chemical mechanical planarization (CMP) step has been performed, according to the present invention.
  • CMP chemical mechanical planarization
  • FIGS. 6A and 6B show the electron emitting tip of FIG. 5 after the insulating layer has undergone a wet etching process to expose the emitter tip, according to the present invention.
  • FIG. 6A shows the result if the insulating layer is an oxide.
  • FIG. 6B shows the result if the insulating layer is a nitride.
  • FIG. 7 is a flow diagram of the steps involved in a gate formation process in accordance with the present invention.
  • the substrate 11 can be comprised of glass, for example, or any of a variety of other suitable materials.
  • a single crystal silicon layer serves as a substrate 11 onto which a conductive material layer 12, such as doped polycrystalline silicon has been deposited.
  • a conical micro-cathode 13 has been constructed on top of the substrate 11.
  • a voltage differential, through source 20 is applied between the cathode 13 and the gate 15, a stream of electrons 17 is emitted toward a phosphor coated screen 16.
  • Screen 16 is an anode.
  • the electron emission tip 13 is integral with the single crystal semiconductor substrate 11, and serves as a cathode conductor.
  • Gate 15 serves as a low potential anode or grid structure for its respective cathode 13.
  • a dielectric insulating layer 14 is deposited on the conductive cathode layer 12. The insulator 14 also has an opening at the field emission site location.
  • FIGS. 2-7 of the drawings depict the initial, intermediate and final structures produced by a series of manufacturing steps according to the invention.
  • a single crystal P-type silicon wafer having formed therein (by suitable known doping pretreatment) a series of elongated, parallel extending opposite N-type conductivity regions, or wells.
  • Each N-type conductivity strip has a width of approximately 10 microns, and a depth of approximately 3 microns. The spacing of the strips is arbitrary and can be adjusted to accommodate a desired number of field emission cathode sites to be formed on a given size silicon wafer substrate.
  • Processing of the substrate to provide the P-type and N-type conductivity regions may be by may well-known semiconductor processing techniques, such as diffusion and/or epitaxial growth.) If desired the P-type and N-type regions, of course, can be reversed through the use of a suitable starting substrate and appropriate dopants.
  • a field emission cathode microstructure can be manufactured using an underlying single crystal, semiconductor substrate.
  • the semiconductor substrate may be either P or N-type and is selectively masked on one of its surfaces where it is desired to form field emission cathode sites.
  • the masking is done in a manner such that the masked areas define islands on the surface of the underlying semiconductor substrate.
  • selective sidewise removal of the underlying peripheral surrounding regions of the semiconductor substrate beneath the edges of the masked island areas results in the production of a centrally disposed, raised, single crystal semiconductor field emitter tip in the region immediately under each masked island area defining a field emission cathode site.
  • the removal of underlying peripheral surrounding regions of the semiconductor substrate be closely controlled by oxidation of the surface of the semiconductor substrate surrounding the masked island areas with the oxidation phase being conducted sufficiently long to produce sideways growth of the resulting oxide layer beneath the peripheral edges of the masked areas to an extent required to leave only a non-oxidized tip of underlying, single crystal substrate beneath the island mask.
  • the oxide layer is differentially etched away at least in the regions immediately surrounding the masked island areas to result in the production of a centrally disposed, raised, single crystal semiconductor field emitter tip integral with the underlying single, crystal semiconductor substrate at each desired field emission cathode site.
  • the tip of the electron emitter may be sharpened through an oxidation process (FIG. 7).
  • the surface of the silicon wafer (Si) 11 and the emitter tip 13 are oxidized to produce an oxide layer of SiO 2 , which is then etched to sharpen the tip.
  • Any conventional, known oxidation process may be employed in forming the SiO 2 , and etching the tip.
  • a selectively etchable material layer is deposited.
  • a conformally deposited silicon nitride layer is used.
  • other materials which are selectively etchable with respect to the flowable insulative layer may be used, (e.g., SiO 2 , and silicon oxynitride)
  • a nitride layer is particularly effective against oxygen diffusion and, therefore, can be used for layers as thin as 1000 ⁇ , but preferably greater than 1000 ⁇ . This is particularly advantageous, since small gate 15 to cathode 13 distances result in lower emitter drive voltages.
  • the thickness of the insulating dielectric layer 18 will determine the gate 15 to cathode 13 spacing.
  • the nitride insulating layer 18, as shown in FIG. 2, is a conformal insulating layer.
  • the nitride layer is deposited on the emitter tip 13 in a manner such that the nitride layer conforms to the conical shape of the cathode emitter tip 13.
  • the next step is the deposition of the flowable insulating layer 14, as shown in FIG. 2.
  • the flowable insulating layer 14 may be comprised of spin-on-glass (SOG), borophosphosilicate glass (BPSG), or a polyimide, or other suitable material, including, but not limited to, other spin on dielectrics or flowable dielectrics. Under certain conditions, such materials flow easily over the surface of the wafer, resulting in a densified planarized layer.
  • the thickness of the flowable insulating layer 14, together with the conformal insulating layer 18 will determine the gate 15 to substrate 11 spacing; the conformal insulating layer 18 alone substantially determines the gate 15 to cathode 13 spacing.
  • the preferred embodiment uses BPSG.
  • the BPSG layer may be initially deposited by a technique such as chemical vapor deposition (CVD) using a phosphorous source such as phosphine (PH 3 ) gas.
  • the wafer surface may also be exposed to a boron source such as diborane (B 2H 6) gas.
  • B 2H 6 diborane
  • the resultant BPSG layer 14 initially may cover the cathode tip 13, and it may then be reflowed.
  • the BPSG reflow is performed at a temperature in the range of 700° C. to 1050° C. In practice, the upper limit of the reflow temperature will be controlled by the effects of the reflow on the substrate and other related structures.
  • the BPSG layer is heated to a temperature of approximately 1000° C. to cause a slight flow of the flowable insulating material, preferably, to a substantially uniform level below the emitter tip 13, as shown in FIG. 3.
  • a technique described in U.S. Pat. No. 4,732,658, describes the use of a CVD method.
  • a silicate glass such as BPSG is deposited over a region of a semiconductor wafer as an approximately uniform thickness layer.
  • the glass is deposited by CVD in an atmospheric system.
  • a review of suitable atmospheric systems is given in W. Kern, G. L. Schnable, RCA Review, Vol. 43, pgs. 423-457, Sept. 1982.
  • PECVD plasma-enhanced CVD
  • another insulating nitride material layer may optionally be deposited at this stage on top of the flowable insulating material 14 to further adjust the spacing between the gate 15 and the tip 13.
  • deposition of the conformal insulating dielectric layer may be delayed until this stage in the gate forming process, i.e., after the deposition and reflow of the flowable insulating material layer 14.
  • the flowable insulating layer 14 may be deposited first, followed by the deposition of the conformal insulating layer. After the reflow step, the emitter tip 13 would be exposed, thereby providing an opportunity to deposit a conformal insulating layer prior to the deposition of the conductive gate material layer 15.
  • the next step in the process is the deposition of the conductive gate material 15.
  • the gate 15 is formed from a conductive layer.
  • the conductive material layer may comprise a metal such as chromium or molybdenum, but the preferred material for this process is deemed to be doped polysilicon.
  • a buffer material may be deposited to prevent the undesired etching of the lower-lying portions of the conductive gate material layer during the chemical mechanical polishing (CMP) step which follows.
  • CMP chemical mechanical polishing
  • a buffering layer is an optional step.
  • a suitable buffering material is a thin layer of Si 3 N 4 .
  • the nitride buffer layer has the effect of protecting the tip 13, which is one advantage of performing this optional step.
  • the buffering layer substantially impedes the progress of the CMP into the layer on which the buffering material is deposited.
  • the next step in the gate formation process is the chemical mechanical planarization (CMP), also referred to in the art as chemical mechanical polishing (CMP).
  • CMP chemical mechanical planarization
  • the buffer material as well as any other layers e.g. the conductive material layer, the conformal insulating layer
  • the buffer material are "polished" away.
  • CMP involves holding or rotating a wafer of semiconductor material against a wetted polishing surface under controlled chemical slurry, pressure, and temperature conditions.
  • a chemical slurry containing a polishing agent such as alumina or silica may be utilized as the abrasive medium. Additionally, the chemical slurry may contain chemical etchants. This procedure may be used to produce a surface with a desired endpoint or thickness, which also has a polished and planarized surface.
  • Such apparatus for polishing are disclosed in U.S. Pat. Nos. 4,193,226 and 4,811,522. Another such apparatus is manufactured by Westech Engineering and is designated as a Model 372 Polisher.
  • CMP will be performed substantially over the entire wafer surface, and at a high pressure. Initially, CMP will proceed at a very fast rate, as the peaks are being removed, then the rate will slow dramatically after the peaks have been substantially removed.
  • the removal rate of the CMP is proportionally related to the pressure and the hardness of the surface being planarized.
  • FIG. 5 illustrates the intermediate step in the gate formation process following the chemical mechanical planarization CMP. A substantially planar surface is achieved, and the conformal insulating layer 18 is thereby exposed.
  • FIG. 5 shows the means by which the conformal insulating layer 18 defines the gate 15 to cathode 13 spacing, as well as the means by which the gate 15 becomes self-aligned.
  • the next process step is a wet etching of the selectively-etchable material layer 18 to expose the emitter tip 13.
  • the insulating layer 18 is selectively etchable with respect to the flowable material layer 14.
  • FIGS. 6A and 6B illustrate the field emitter device after the insulating cavity has been so etched.
  • FIG. 6A depicts the resultant structure when the insulating layer 18 is an oxide
  • FIG. 6B depicts the resultant structure when the insulating layer 18 is a nitride.
  • the cathode tip 13 may, optionally, be coated with a low work-function material (FIG. 7).
  • Low work function materials include, but are not limited to cermet (Cr 3 Si+ SiO 2 ), cesium, rubidium, tantalum nitride, barium, chromium silicide, titanium carbide, molybdenum, and niobium. Coating of the emitter tips may be accomplished in one of many ways.
  • the low work-function material or its precursor may be deposited through sputtering or other suitable means on the tips 13. Certain metals (e.g., titanium or chromium) may be reacted with the silicon of the tips to form silicide during a rapid thermal processing (RTP) step.
  • RTP rapid thermal processing
  • any unreacted metal is removed from the tip 13.
  • deposited tantalum may be converted during RTP to tantalum nitride, a material having a particularly low work function.
  • the coating process variations are almost endless. This results in an emitter tip 13 that may not only be sharper than a plain silicon tip, but that also has greater resistance to erosion and a lower work function.
  • the silicide is formed by the reaction of the refractory metal with the underlying polysilicon by an anneal step.

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US07/837,453 1992-02-14 1992-02-14 Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology Expired - Lifetime US5229331A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US07/837,453 US5229331A (en) 1992-02-14 1992-02-14 Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology
DE4304103A DE4304103C2 (de) 1992-02-14 1993-02-11 Verfahren zum Bilden selbstausgerichteter Gatestrukturen
JP4716293A JP2836802B2 (ja) 1992-02-14 1993-02-15 化学・機械研磨法を用いた冷陰極エミッタ先端部の周囲にセルフアライン型のゲート構造体を形成する方法
US08/053,794 US5372973A (en) 1992-02-14 1993-04-27 Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology
US08/300,616 US5696028A (en) 1992-02-14 1994-09-02 Method to form an insulative barrier useful in field emission displays for reducing surface leakage
US08/918,766 US5831378A (en) 1992-02-14 1997-08-25 Insulative barrier useful in field emission displays for reducing surface leakage
US08/949,931 US6066507A (en) 1992-02-14 1997-10-14 Method to form an insulative barrier useful in field emission displays for reducing surface leakage
JP1069298A JP3098483B2 (ja) 1992-02-14 1998-01-22 化学・機械研磨法を用いた冷陰極エミッタ先端部の周囲にセルフアライン型のゲート構造体を形成する方法

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JP2836802B2 (ja) 1998-12-14
US5372973A (en) 1994-12-13
JPH10188784A (ja) 1998-07-21

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