US4928163A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US4928163A
US4928163A US07/315,196 US31519689A US4928163A US 4928163 A US4928163 A US 4928163A US 31519689 A US31519689 A US 31519689A US 4928163 A US4928163 A US 4928163A
Authority
US
United States
Prior art keywords
impurity region
impurity
semiconductor device
conductivity type
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/315,196
Other languages
English (en)
Inventor
Toshihiko Yoshida
Toru Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of US4928163A publication Critical patent/US4928163A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/913—Active solid-state devices, e.g. transistors, solid-state diodes with means to absorb or localize unwanted impurities or defects from semiconductors, e.g. heavy metal gettering

Definitions

  • the present invention relates to a semiconductor device. More particularly, it relates to a semiconductor device wherein source and drain regions having three regions formed by three different types of impurity doping steps are formed to prevent the occurrence of hot electrons which otherwise cause deterioration of the device performance.
  • the length of the gate electrode of a MIS FET has been shortened.
  • the supply voltage is generally maintained at 5 V, and does not have a lowering tendency.
  • This causes the problem that particularly in an n channel MIS transistor, the drain electric field is greater than in a conventional device, and a portion of the electrons accelerated by the increased electric field are injected into a gate insulating film: this is well known as a channel hot electron phenomenon. Further, a portion of the electrons generated by the impact ionization are injected to the gate insulating film and changes the characteristic of the MIS transistor; this is well known as an avalanche hot electron phenomenon.
  • DDD double diffused drain
  • LDD lightly doped drain
  • the LDD structure has an effect on the channel hot electron phenomenon, it has little effect on the avalanche hot electron phenomenon, in which electrons generated at a deeper portion of the substrate due to the high electric field strength are accelerated so that the electrons are moved to the gate electrode through the gate insulating film.
  • the LDD structure deterioration of the mutual conductance also occurs.
  • an object of the present invention is to provide a semiconductor device, particularly MIS FET, wherein the occurrence of the channel hot electron phenomenon and the avalanche hot electron phenomenon are decreased.
  • Another object of the present invention is to provide a semiconductor device, wherein the mutual conductance (g m ) thereof is improved.
  • a semiconductor device formed in a semiconductor substrate and having a gate electrode formed on said semiconductor substrate, and source and drain regions formed in said semiconductor substrate wherein the source and drain regions comprise: a first impurity region doped with impurities of an opposite conductivity type to that of the semiconductor substrate formed at portions adjacent to the edge of the gate electrode; a second impurity region doped with impurities an opposite conductivity type to the semiconductor substrate formed at portions under the first impurity region, the impurities of the second impurity region having larger diffusion coefficient than that of the impurities of the first impurity region; a third impurity region doped with impurities of an opposite conductivity type to the semiconductor substrate formed at portions spaced apart from the edge of the gate electrode, the third impurity region having a higher concentration than that of first and second impurity regions and the impurities of the third impurity region having a diffusion coefficient smaller than that of the second inpurity region.
  • FIG. 1A is a cross-sectional view of a conventional DDD structure
  • FIG. 1B is an equivalent circuit view of FIG. 1A;
  • FIG. 2 is a cross-sectional view of a conventional LDD structure
  • FIG. 3 is a cross-sectional view of another conventional example
  • FIG. 4 is a cross-sectional view of still another conventional example
  • FIG. 5A is a cross-sectional view of an example of an n channel MIS FET according to the present invention.
  • FIG. 5B is an equivalent circuit view of FIG. 5A.
  • FIGS. 6A to 6D and FIGS. 7A to 7D are cross-sectional views explaining two production processes according to the present invention.
  • FIG. 1A is a cross-sectional view of a conventional DDD structure.
  • an insulating film 2 and a gate electrode 3 are provided on a p-type semiconductor substrate 1.
  • an n + region 4 and an n - region 5 are formed by doping, for example, an arsenic ion (As + ) and a phosphorus ion (P + ), followed by annealing. Since the diffusion coefficient of phosphorus is remarkably larger than that of arsenic, a double diffused drain (DDD) region, i.e., n + region (As + ) and n - region (P + ), is formed.
  • the structure formed before the DDD structure is formed has only the n + region 4, wherein As + is diffused, so that a step-junction is formed.
  • an electric field was concentrated at a portion 6 in the n + region 4 where the step-junction is formed, and this led to the problem of the occurrence of the above-mentioned hot electron phenomenon.
  • n - region (P + ) 5 of the DDD structure in such a manner that the n - region (P + ) 5 is underneath the n + region 4, a graded junction formed by the diffusion of a P + electric field is shifted to a portion 7 in the n - region. Consequently, the concentration of an electric field in the portion 7 is considerably decreased compared to that in the portion 6.
  • the DDD structure has an effective channel length (C2) shorter than that (C1) of one prior structure not having an n - region, as shown in FIG. 1A. Consequently in the DDD structure, a punch through phenomenon often occurs between the source and drain region. Further, in the DDD structure, the properties of an FET are determined by the concentration of P + in the n - type region 5. When the concentration of P + is low, a parasitic series resistance is generated, as shown by a reference number 8 in FIG. 1A. Further, the mutual conductance (g m ) of the device cannot be increased. On the other hand, when the concentration of P + is high, the breakdown voltage is lowered.
  • FIG. 1B An equivalent circuit of the device shown in FIG. 1A is shown in FIG. 1B.
  • a lightly doped drain (LDD) structure in which a gate insulating film 2, a gate electrode 3, and a side wall 10 are formed on a p-type semiconductor substrate 1.
  • an n - region 5 and an n + region 4 is formed by doping As + and then performing an annealing process.
  • As + having a low concentration is doped into the subtrate 1 to form the n - region 5
  • As + having a high concentration is doped therein to form an n + region 4.
  • the diffusion depth (x j ) of the doped impurities is determined by the root of the concentration (C) thereof, i.e., ⁇ C ⁇ x j .
  • the LDD structure can prevent occurrence of channel hot electrons at a portion 11 in FIG. 2.
  • the LDD structure cannot prevent the occurrence of avalanche hot electrons which are generated at a deeper portion 12 of the substrate 1, due to the high electric field strength, and accelerated to move into the gate electrode 3 through the gate insulating film 2.
  • the deterioration of the mutual conductance (g m ) occurs as in the DDD structure.
  • FIG. 3 shows a semiconductor device as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 60-136376.
  • This device (Hitachi structure) has an n + region 4, an n 1 - region 5a and an n 2 - region 5b in the source and drain regions.
  • Each region is produced by a process wherein P + is doped to a dosage of 1 ⁇ 10 12 cm -2 using a polycrystalline layer of a gate electrode 3 formed on a gate insulating film 2 as a mask, side walls of SiO 2 are formed so that the gate electrode 3 is sandwiched, therebetween, P + is doped to a dosage of 1 ⁇ 10 14 cm -2 using the gae electrode 3 and the side walls 10 as a mask, P + doped portions are annealed while the doped P + is diffused so that the n 1 - region 5a (P + doped to a dosage of 1 ⁇ 10 12 cm - 2) and n 2 - region 5b (P + doped to a dosage of 1 ⁇ 10 14 cm -2 ) are formed, As + is doped to a dosage of 5 ⁇ 10 15 cm -2 using the gate electrode 3 and the side walls 10 as a mask, and the n + region 4 is formed by annealing the As + doped portion.
  • the n 1 - region 5a is formed by doping P + , which has a large diffusion coefficient, into the substrate 1, the distance C3 between the edges of the n 1 - regions 5a, i.e., channel length, becomes short and the above-mentioned punch through phenomenon occurs. Further, as explained for the DDD structure, the Hitachi structure is subjected to a resistance due to the diffused n 1 - region 5a, so that the mutual conductance (g m ) is lowered. These disadvantages in the Hitachi structure become greater as the semiconductor device become smaller.
  • FIG. 4 shows a semiconductor device disclosed at a Symposium on VLSI Technology, 14 to 16 May, 1985.
  • This device (Toshiba structure) also has three regions, i.e., n 1 - , n 2 - , and n + regions.
  • Each region is produced by a process wherein P + and As + are doped using a gate electrode 3 as a mask, the P + and As + doped portions are annealed to form the n 2 - region 5b and n 1 - region 5a, respectively, side walls 10 are formed, As + is doped using the gate electrode 3 and the side walls 10 as a mask, and the second As + doped portion is annealed to form the n + region 4. Since the n 2 - region is formed by annealing the P + doped portion, as explained for the Hitachi structure, the Toshiba structure also has the disadvantage of the occurrence of a punch through phenomenon and the mutual conductance (g m ) becomes small.
  • FIG. 5A shows a cross-sectional view explaining an example of an n channel MIS FET according to the present invention.
  • a source (S) and a drain (D) region in a P-type semiconductor substrate or p-type well 11 each consist of an n 1 - region 15a, an n 2 - region 15b, and an n + region 14.
  • An insulating film 2 of, for example, SiO 2 , a gate electrode 3 of polycrystalline silicon, and side walls 10 of an insulating material are provided on the semiconductor substrate 11.
  • the n 1 - region 15a is formed by doping impurities having a low concentration on outside edge A of the gate electrode 3.
  • the n 2 - region 15b and the n + region 14 are formed by doping impurities having a low and a high concentration, respectively, an outside the edge B of the side walls 10.
  • the distance between the N + region 14 and the gate electrode 3 is preferably equal to the width of one of the sidewalls 10.
  • the diffusion coefficient of impurities doped in the n 2 - region is larger than that of impurities doped in the n 1 - and n + regions.
  • Resistance in the structure is shown in FIG. 5B. Namely, the resistance in, for example, a source region, which is generated by the n 1 - and n 2 - regions is equivalent to total resistance of n 1 - and n 2 - regions connected in parallel to each other (not in series) and is reduced, thus allowing an increase in the mutual conductance (g m ).
  • p type channel cut regions 16, a field insulating film 12 of, for example, SiO 2 , and a gate insulating film 2 of, for example, SiO 2 are formed on a p type semiconductor substrate 11 which has an impurity concentration of 10 15 -10 16 cm -3 , and then a gate electrode 3 having a thickness of 2000 to 5000 ⁇ is formed.
  • the gate electrode 3 is made of polycrystalline silicon, a high melting point metal or high melting point metalsilicide, etc.
  • As + is doped to a dosage of 1 ⁇ 10 13 to 1 ⁇ 10 15 cm -2 at an accelerating energy of 60 to 120 KeV so that the first lightly doped n - regions, i.e., n 1 - regions, 15a are formed.
  • an insulating layer 17 having a thickness of 500 to 5000 ⁇ is formed on the obtained structure.
  • the insulating layer is made of SiO 2 or Si 3 N 4 obtained by a chemical vapour deposition (CVD) process, etc.
  • the insulating layer 17 of, for example, CVD-SiO 2 is entirely removed by a reactive ion etching (RIE) process using CHF 3 gas or a mixed gas of CHF 3 and CF 4 under a pressure of 0.1 to 0.2 torr so that side walls 10a are formed in such a manner that they sandwich the gate electrode 3.
  • RIE reactive ion etching
  • P + having a larger diffusion coefficient than As + is doped to a dosage of 1 ⁇ 10 13 to 1 ⁇ 10 15 cm -2 at an accelerating energy of 60 to 80 KeV to form a second lightly doped n - region, i.e., n 2 - region 15b, and As + is doped to a dosage of 3 ⁇ 10 15 to 5 ⁇ 10 15 cm -2 at an accelerating energy of 60 to 120 KeV to form a heavily doped or high concentration n + region 14.
  • the obtained structure is then annealed at a temperature of 900° C. to 1100° C. in an inert gas atmosphere.
  • the n 2 - region has a graded junction formed between the n 2 - region and the substrate 11.
  • the graded junction surface formed between the n 2 - region 15b and the substrate 11 forms a surface substantially tangential with a junction surface formed between the n 1 - region 15a and the substrate 11.
  • PSG phospho-silicate glass
  • BSG boron silicate glass
  • P type channel cut regions 16, a field insulating film 12, and a gate insulating film 2 are formed on a p type semiconductor substrate 11.
  • a gate electrode 3 having a thickness of 2000 to 5000 ⁇ and a width longer than the width of the first embodiment explained above is formed using a mask 22 of CVD SiO 2 having a thickness of 500 to 2000 ⁇ .
  • the material of the gate electrode is the same as that used in the first embodiment.
  • P + is doped to a dosage of 1 ⁇ 10 13 to 1 ⁇ 10 15 cm -2 at an accelerating energy of 60 to 80 KeV to form a lightly doped n 2 - region 15b.
  • As + is doped to a dosage of 3 ⁇ 10 15 to 5 ⁇ 10 15 cm -2 at an accelerating energy of 60 to 120 KeV to form a heavily doped or high concentration n + region 14.
  • both sides of the gate electrode 3 are removed by a side plasma etching process using a mixed gas of CF 4 and O 2 (5%) in a polycrystalline silicon gate electrode so that a width of 1000 to 4000 ⁇ is removed from each side thereof.
  • the mask 22 of CVD SiO 2 is removed and As + is doped to a dosage of 1 ⁇ 10 13 to 1 ⁇ 10 15 cm -2 at an accelerating energy of 60 to 120 KeV to form lightly doped n 1 - region 15a.
  • an annealing process is carried out at a temperature of 900° C. to 1100° C. in an inert gas atmosphere.
  • an insulating layer 20 and aluminum electrodes 21a, 21b, and 21c are formed as described in the first embodiment, thus, producing a second embodiment of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US07/315,196 1985-03-20 1989-02-27 Semiconductor device Expired - Lifetime US4928163A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60-57416 1985-03-20
JP60057416A JPS61216364A (ja) 1985-03-20 1985-03-20 半導体装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US06839525 Continuation 1986-03-14

Publications (1)

Publication Number Publication Date
US4928163A true US4928163A (en) 1990-05-22

Family

ID=13055042

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/315,196 Expired - Lifetime US4928163A (en) 1985-03-20 1989-02-27 Semiconductor device

Country Status (7)

Country Link
US (1) US4928163A (fr)
EP (1) EP0195607B1 (fr)
JP (1) JPS61216364A (fr)
KR (1) KR890004981B1 (fr)
CA (1) CA1246758A (fr)
DE (1) DE3667879D1 (fr)
IE (1) IE57400B1 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121175A (en) * 1987-11-14 1992-06-09 Fujitsu Limited Semiconductor device having a side wall film
US5164801A (en) * 1986-08-29 1992-11-17 Kabushiki Kaisha Toshiba A p channel mis type semiconductor device
US5281841A (en) * 1990-04-06 1994-01-25 U.S. Philips Corporation ESD protection element for CMOS integrated circuit
US5292674A (en) * 1990-11-30 1994-03-08 Nec Corporation Method of making a metal-oxide semiconductor field-effect transistor
US5426326A (en) * 1992-08-07 1995-06-20 Hitachi, Ltd. Semiconductor device including arrangement for reducing junction degradation
US5496742A (en) * 1993-02-22 1996-03-05 Nec Corporation Method for manufacturing semiconductor device enabling gettering effect
US5716861A (en) * 1991-06-26 1998-02-10 Texas Instruments Incorporated Insulated-gate field-effect transistor structure and method
US5893742A (en) * 1995-01-17 1999-04-13 National Semiconductor Corporation Co-implantation of arsenic and phosphorus in extended drain region for improved performance of high voltage NMOS device
US5912493A (en) * 1997-11-14 1999-06-15 Gardner; Mark I. Enhanced oxidation for spacer formation integrated with LDD implantation
US5945710A (en) * 1996-03-07 1999-08-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with doped contact impurity regions having particular doping levels
US6162668A (en) * 1996-03-07 2000-12-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having a lightly doped contact impurity region surrounding a highly doped contact impurity region
US6597038B1 (en) * 1998-02-24 2003-07-22 Nec Corporation MOS transistor with double drain structure for suppressing short channel effect
US20050104138A1 (en) * 2003-10-09 2005-05-19 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20050130372A1 (en) * 2003-12-15 2005-06-16 Hynix Semiconductor Inc. Method for manufacturing flash memory device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835740A (en) * 1986-12-26 1989-05-30 Kabushiki Kaisha Toshiba Floating gate type semiconductor memory device
GB2215515A (en) * 1988-03-14 1989-09-20 Philips Electronic Associated A lateral insulated gate field effect transistor and a method of manufacture
JPH0783122B2 (ja) * 1988-12-01 1995-09-06 富士電機株式会社 半導体装置の製造方法
US5012306A (en) * 1989-09-22 1991-04-30 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron MISFET device
JPH0442579A (ja) * 1990-06-08 1992-02-13 Seiko Epson Corp 薄膜トランジスタ及び製造方法
US5234850A (en) * 1990-09-04 1993-08-10 Industrial Technology Research Institute Method of fabricating a nitride capped MOSFET for integrated circuits
US5424234A (en) * 1991-06-13 1995-06-13 Goldstar Electron Co., Ltd. Method of making oxide semiconductor field effect transistor
WO1994027325A1 (fr) * 1993-05-07 1994-11-24 Vlsi Technology, Inc. Structure de circuit integre et son procede
WO1998032176A1 (fr) * 1997-01-21 1998-07-23 Advanced Micro Devices, Inc. JONCTION A ZONES nLDD HYBRIDES As/P AVEC FONCTIONNEMENT A TENSION D'ALIMENTATION MOYENNE POUR MICROPROCESSEURS A GRANDE VITESSE
JP3530410B2 (ja) 1999-02-09 2004-05-24 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4172260A (en) * 1976-12-01 1979-10-23 Hitachi, Ltd. Insulated gate field effect transistor with source field shield extending over multiple region channel
JPS60136376A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置の製造方法
JPS60198780A (ja) * 1984-03-21 1985-10-08 Seiko Instr & Electronics Ltd Ｍｏｓトランジスタ装置
JPS60234367A (ja) * 1984-05-07 1985-11-21 Hitachi Ltd Ｍｉｓ型電界効果トランジスタ
US4560582A (en) * 1980-11-20 1985-12-24 Kabushiki Kaisha Suwa Seikosha Method of preparing a semiconductor device
US4680603A (en) * 1985-04-12 1987-07-14 General Electric Company Graded extended drain concept for reduced hot electron effect

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4172260A (en) * 1976-12-01 1979-10-23 Hitachi, Ltd. Insulated gate field effect transistor with source field shield extending over multiple region channel
US4560582A (en) * 1980-11-20 1985-12-24 Kabushiki Kaisha Suwa Seikosha Method of preparing a semiconductor device
JPS60136376A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置の製造方法
JPS60198780A (ja) * 1984-03-21 1985-10-08 Seiko Instr & Electronics Ltd Ｍｏｓトランジスタ装置
JPS60234367A (ja) * 1984-05-07 1985-11-21 Hitachi Ltd Ｍｉｓ型電界効果トランジスタ
US4680603A (en) * 1985-04-12 1987-07-14 General Electric Company Graded extended drain concept for reduced hot electron effect

Non-Patent Citations (18)

* Cited by examiner, † Cited by third party
Title
Balasubramanyam, K., et al., "Characterization of As-P Double Diffused Drain Structure" IEDM 84, pp. 782-785, Dec. 1984.
Balasubramanyam, K., et al., Characterization of As P Double Diffused Drain Structure IEDM 84, pp. 782 785, Dec. 1984. *
European Search Report, The Hague, 9 11 86. *
European Search Report, The Hague, 9-11-86.
Hsia, S., et al., "Polysilicon Oxidation Self-Aligned MOS(POSA MOS) . . . " IEEE Elec. Dev. Lett. vol. EDL-3, No. 2, Feb. 1982, pp. 40-42.
Hsia, S., et al., Polysilicon Oxidation Self Aligned MOS(POSA MOS) . . . IEEE Elec. Dev. Lett. vol. EDL 3, No. 2, Feb. 1982, pp. 40 42. *
IEEE Transactions on Electron Devices, vol. Ed 29, No. 4, Apr. 1982, pp. 590 596, New York, TSANG et al.: Fabrication of High Performance LDDFET S With Oxide Sidewall Spacer Technology . *
IEEE Transactions On Electron Devices, vol. ED 30, No. 6, Jun. 1983, pp. 652 657, New York, E. Takeda et al.: An AS P(n n ) Double Diffused Drain MOSFET for VLSI s . *
IEEE Transactions On Electron Devices, vol. ED 32, No. 3, Mar. 1985, pp. 562 570, New York, M. Koyanagi et al.: Optimum Design of n n Double Diffused Drain MOSFET to Reduce Hot Carrier Emission . *
IEEE Transactions on Electron Devices, vol. Ed-29, No. 4, Apr. 1982, pp. 590-596, New York, TSANG et al.: "Fabrication of High-Performance LDDFET'S With Oxide Sidewall-Spacer Technology".
IEEE Transactions On Electron Devices, vol. ED-30, No. 6, Jun. 1983, pp. 652-657, New York, E. Takeda et al.: "An AS-P(n+-n-) Double Diffused Drain MOSFET for VLSI's".
IEEE Transactions On Electron Devices, vol. ED-32, No. 3, Mar. 1985, pp. 562-570, New York, M. Koyanagi et al.: "Optimum Design of n+-n-Double-Diffused Drain MOSFET to Reduce Hot-Carrier Emission".
Patents Abstracts of Japan, vol. 10, No. 42 (E 382) 2099 , 19th Feb., 1986 & JP A 60 198 780 (Seiko Denshi Kogyo K.K.) 08 10 1985. *
Patents Abstracts of Japan, vol. 10, No. 42 (E-382) [2099], 19th Feb., 1986 & JP-A-60 198 780 (Seiko Denshi Kogyo K.K.) 08-10-1985.
Patents Abstracts Of Japan, vol. 10, No. 91 (E 394) 2148 , Apr. 9, 1986; & JP A 60 234 367 (Hitachi Seisakusho K.K.) 21 11 1985. *
Patents Abstracts Of Japan, vol. 10, No. 91 (E-394) [2148], Apr. 9, 1986; & JP-A-60 234 367 (Hitachi Seisakusho K.K.) 21-11-1985.
Patents Abstracts Of Japan, vol. 9, No. 298 (E 361) 2021 , 26 Nov. 1985; & JP A 60 136 376 (Hitachi Seisakusho K.K.) 19 07 1985. *
Patents Abstracts Of Japan, vol. 9, No. 298 (E-361) [2021], 26 Nov. 1985; & JP-A-60 136 376 (Hitachi Seisakusho K.K.) 19-07-1985.

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164801A (en) * 1986-08-29 1992-11-17 Kabushiki Kaisha Toshiba A p channel mis type semiconductor device
US5424237A (en) * 1987-11-14 1995-06-13 Fujitsu Limited Method of producing semiconductor device having a side wall film
US5121175A (en) * 1987-11-14 1992-06-09 Fujitsu Limited Semiconductor device having a side wall film
US5281841A (en) * 1990-04-06 1994-01-25 U.S. Philips Corporation ESD protection element for CMOS integrated circuit
US5292674A (en) * 1990-11-30 1994-03-08 Nec Corporation Method of making a metal-oxide semiconductor field-effect transistor
US5949105A (en) * 1991-06-26 1999-09-07 Texas Instruments Incorporated Insulated-gate field-effect transistor structure and method
US5716861A (en) * 1991-06-26 1998-02-10 Texas Instruments Incorporated Insulated-gate field-effect transistor structure and method
US5426326A (en) * 1992-08-07 1995-06-20 Hitachi, Ltd. Semiconductor device including arrangement for reducing junction degradation
US5496742A (en) * 1993-02-22 1996-03-05 Nec Corporation Method for manufacturing semiconductor device enabling gettering effect
US5893742A (en) * 1995-01-17 1999-04-13 National Semiconductor Corporation Co-implantation of arsenic and phosphorus in extended drain region for improved performance of high voltage NMOS device
US6091111A (en) * 1995-01-17 2000-07-18 National Semiconductor Corporation High voltage mos device having an extended drain region with different dopant species
US5945710A (en) * 1996-03-07 1999-08-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with doped contact impurity regions having particular doping levels
US6162668A (en) * 1996-03-07 2000-12-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having a lightly doped contact impurity region surrounding a highly doped contact impurity region
US5912493A (en) * 1997-11-14 1999-06-15 Gardner; Mark I. Enhanced oxidation for spacer formation integrated with LDD implantation
US6597038B1 (en) * 1998-02-24 2003-07-22 Nec Corporation MOS transistor with double drain structure for suppressing short channel effect
US20050104138A1 (en) * 2003-10-09 2005-05-19 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US7157779B2 (en) * 2003-10-09 2007-01-02 Sanyo Electric Co., Ltd. Semiconductor device with triple surface impurity layers
US20050130372A1 (en) * 2003-12-15 2005-06-16 Hynix Semiconductor Inc. Method for manufacturing flash memory device

Also Published As

Publication number Publication date
EP0195607A2 (fr) 1986-09-24
CA1246758A (fr) 1988-12-13
JPH053751B2 (fr) 1993-01-18
IE57400B1 (en) 1992-08-26
DE3667879D1 (de) 1990-02-01
IE860714L (en) 1986-09-20
EP0195607A3 (en) 1986-12-17
KR890004981B1 (ko) 1989-12-02
JPS61216364A (ja) 1986-09-26
EP0195607B1 (fr) 1989-12-27
KR860007755A (ko) 1986-10-17

Similar Documents

Publication Publication Date Title
US4928163A (en) Semiconductor device
US6064096A (en) Semiconductor LDD device having halo impurity regions
US4703551A (en) Process for forming LDD MOS/CMOS structures
US5510279A (en) Method of fabricating an asymmetric lightly doped drain transistor device
US4503598A (en) Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US5436482A (en) MOSFET with assymetric lightly doped source-drain regions
US5583067A (en) Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication
US5102815A (en) Method of fabricating a composite inverse T-gate metal oxide semiconductor device
EP0164449B1 (fr) Procédé pour fabriquer un dispositif à circuit intégré semi-conducteur comportant un élément du type MISFET
US5097301A (en) Composite inverse T-gate metal oxide semiconductor device and method of fabrication
US5234852A (en) Sloped spacer for MOS field effect devices comprising reflowable glass layer
US5895238A (en) Doping technique for MOS devices
US5831307A (en) Silicon damage free process for double poly emitter and reverse MOS in BICMOS application
US5225357A (en) Low P+ contact resistance formation by double implant
US4826782A (en) Method of fabricating aLDD field-effect transistor
US5424571A (en) Sloped spacer for mos field effect devices
US6576521B1 (en) Method of forming semiconductor device with LDD structure
US5640035A (en) MOSFET having improved driving performance
US5877044A (en) Method of making MOS-gated semiconductor devices
KR0162512B1 (ko) 반도체 집적회로 장치
JPS62120082A (ja) 半導体装置及びその製造方法
KR940010543B1 (ko) 모스 트랜지스터의 제조방법
KR100873814B1 (ko) 이중 엘디디구조를 갖는 반도체소자 및 그 제조 방법
US5334543A (en) Method of making reverse lightly doped drain (LDD) for buried N+ conductor
KR100200343B1 (ko) 고내압 모스 트랜지스터 및 그 제조방법

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12