US4110779A - High frequency transistor - Google Patents

High frequency transistor Download PDF

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Publication number
US4110779A
US4110779A US05/749,609 US74960976A US4110779A US 4110779 A US4110779 A US 4110779A US 74960976 A US74960976 A US 74960976A US 4110779 A US4110779 A US 4110779A
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United States
Prior art keywords
zone
base
emitter
frequency transistor
collector
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Expired - Lifetime
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US05/749,609
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English (en)
Inventor
Ronald Rathbone
Ulrich Schwabe
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/441—Vertical BJTs having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors

Definitions

  • the invention relates to a high frequency transistor having a small emitter width and a low base bulk resistance, which, in a semiconductor body is electrically insulated from adjacent components by oxide layers.
  • the minimum emitter width is determined by the lower limit values which can be attained with photo-lacquer- and etching-techniques.
  • the base bulk resistance can be reduced by implanting a stepped profile (IEEE Transactions on Electron Devices, Vol. ED 21 No. 4, April 1974, pages 273-278).
  • the oxide insulation technique has the advantage that no insulating tubs with lateral insulation diffusions are required in order to electrically isolate a component from an adjacent component. Thus a higher degree of integration can be achieved with the oxide insulation technique.
  • This object is realized in accordance with the invention by providing a base zone which consists of two differently doped zones wherein one of these zones establishes the effective emitter width.
  • a further development of the invention consists in that the zone which establishes the effective emitter width consists of a region between an oxide layer and the other zone of the base zone.
  • the base zone is preferably broken down into a p doped, active base zone and preferably a p + highly doped inactive base zone.
  • the inactive base zone is bounded by a "beak-shaped" region which is formed during the oxidation of the insulating oxide layers. It is in this region that the zone which is doped oppositely to the base zone runs obliquely upwards to the surface of the semiconductor body.
  • an oppositely doped region whose width represents the effective emitter width. In this way, emitter widths from 0.1 to 0.5 ⁇ m can be produced independently of photo-technical processes.
  • the inactive base zone reduces the base bulk resistance.
  • the emitter window is opened and the active base zone is produced by ion implantation.
  • This active base zone is bounded on the one side by the oxide layer and on the other side by the inactive base zone. This provides a self-adjustment.
  • the emitter zone can either be implanted or diffused with arsenic or phosphorus.
  • FIG. 1 is a plan view of the high-frequency transistor in accordance with the invention.
  • FIG. 2 is a cross-sectional view taken along line II--II of the high-frequency transistor in FIG. 1;
  • FIG. 3 shows a side view of the portion III of the high-frequency transistor of FIG. 2 following the implantation of the active base zone
  • FIG. 4 is a side view of the high frequency transistor in accordance with the invention.
  • FIG. 1 schematically illustrates a plan view of a high-frequency transistor in accordance with the invention.
  • a semiconductor body 1 with silicon dioxide layers 9, 11, 13 and silicon dioxide films 14 are a p + doped base zone 5 and a n + doped zone 10.
  • the semiconductor body 1 consists of a p doped substrate wafer 2 having a specific resistance of 0.5 Ohm-cm and a (100) structural orientation.
  • Arranged on the substrate wafer 2 is a 2.5 ⁇ m thick, n doped epitaxial layer 3 having a specific resistance of 0.8 Ohm-cm.
  • a n + doped buried layer 4 having a penetration depth of 4 ⁇ m and a layer resistance of 25 Ohm/ ⁇ is formed by doping with antimony in the substrate wafer 2.
  • pits are introduced into the epitaxial layer 3 by etching to a depth of approximately 1.5 ⁇ m.
  • oxide layers 9, 11, and 13 having a layer thickness of approximately 2 ⁇ m are formed in the pits.
  • a beak-shaped zone 30 is formed along the side walls thereof.
  • the base zone 5 is produced by diffusion and has a layer resistance of 30 to 500 Ohm/ ⁇ (preferably 300 Ohm/ ⁇ ).
  • the zone 10 is produced by diffusion.
  • An emitter window 15 is introduced into the silicon dioxide film 14 formed on the zone 5. Then an active base zone 7 is implanted by ion implantation with an implantation energy of 20 to 150 keV, (preferably 80 keV), and a dose of 10 12 to 10 14 (preferably 10 13 ). The outline of this active base zone 7 is indicated by a broken line 20 in FIG. 3.
  • the emitter zone 25 is produced by diffusion or implantation.
  • the effective emitter width d here is determined by the width of the n doped zone 24 (see FIG. 2) and the penetration depth of the emitter diffusion. In this way it is possible to produce emitter widths of 0.1 to 0.5 ⁇ m with the aid of conventional photo-lacquer and etching techniques.
  • a collector contact 26, an emitter contact 27, and a base contact 28 are formed in the window 15 and in the further windows 21 and 22.
  • the zone 10, the buried layer 4, and the epitaxial layer 3 form the collector zone.
  • the base zone 6 consists of the p + highly-doped inactive base zone 5 and the p doped active base zone 7.
  • the lateral extent of the inactive base zone 5 is determined by the geometry of the beak-shaped zone 30 which latter is formed during the insulation oxidation for the oxide layers 9, 11 and 13. Between the inactive base zone 5 and the oxide layer 9 remains the n doped zone 24 whose width represents the effective emitter width.
  • the active base zone 7 is implanted after the emitter window 15 has been opened. This zone is bounded on the one side by the inactive base zone 5 and on the other side by the oxide layer 9.

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  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
US05/749,609 1976-02-12 1976-12-13 High frequency transistor Expired - Lifetime US4110779A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2605641 1976-02-12
DE2605641A DE2605641C3 (de) 1976-02-12 1976-02-12 Hochfrequenztransistor und Verfahren zu seiner Herstellung

Publications (1)

Publication Number Publication Date
US4110779A true US4110779A (en) 1978-08-29

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US05/749,609 Expired - Lifetime US4110779A (en) 1976-02-12 1976-12-13 High frequency transistor

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US (1) US4110779A (https=)
JP (1) JPS5299078A (https=)
DE (1) DE2605641C3 (https=)
FR (1) FR2341206A1 (https=)
GB (1) GB1530010A (https=)
IT (1) IT1074663B (https=)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4196440A (en) * 1978-05-25 1980-04-01 International Business Machines Corporation Lateral PNP or NPN with a high gain
US4228450A (en) * 1977-10-25 1980-10-14 International Business Machines Corporation Buried high sheet resistance structure for high density integrated circuits with reach through contacts
US4261763A (en) * 1979-10-01 1981-04-14 Burroughs Corporation Fabrication of integrated circuits employing only ion implantation for all dopant layers
US4289550A (en) * 1979-05-25 1981-09-15 Raytheon Company Method of forming closely spaced device regions utilizing selective etching and diffusion
US4333774A (en) * 1979-03-20 1982-06-08 Fujitsu Limited Method for producing walled emitter type bipolar transistors
US4355320A (en) * 1979-05-31 1982-10-19 Siemens Aktiengesellschaft Light-controlled transistor
US4408387A (en) * 1981-09-28 1983-10-11 Fujitsu Limited Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask
US4435225A (en) 1981-05-11 1984-03-06 Fairchild Camera & Instrument Corporation Method of forming self-aligned lateral bipolar transistor
US4519128A (en) * 1983-10-05 1985-05-28 International Business Machines Corporation Method of making a trench isolated device
US4547793A (en) * 1983-12-27 1985-10-15 International Business Machines Corporation Trench-defined semiconductor structure
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
US4677456A (en) * 1979-05-25 1987-06-30 Raytheon Company Semiconductor structure and manufacturing method
US4725562A (en) * 1986-03-27 1988-02-16 International Business Machines Corporation Method of making a contact to a trench isolated device
US5013672A (en) * 1987-10-23 1991-05-07 Sgs-Thomson Microelectronics S.R.L. Manufacturing process for high-frequency bipolar transistors
US5128741A (en) * 1988-06-16 1992-07-07 Telefonaktiebolaget L M Ericsson Methods producing on a semi-conductor substructure a bipolar transistor, or a bipolar and a field effect transistor or a bipolar and a field effect transistor with a complementary field effect transistor and devices resulting from the methods

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7709363A (nl) * 1977-08-25 1979-02-27 Philips Nv Werkwijze ter vervaardiging van een halfgeleider- inrichting en halfgeleiderinrichting vervaardigd onder toepassing van een dergelijke werkwijze.
JPS57149770A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Manufacture of semiconductor device
DE19962907A1 (de) 1999-12-23 2001-07-05 Basf Ag Verfahren zur Herstellung von C¶10¶-C¶30¶-Alkenen durch partielle Hydrierung von Alkinen an Festbett-Palladium-Trägerkatalysatoren

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3933540A (en) * 1973-10-17 1976-01-20 Hitachi, Ltd. Method of manufacturing semiconductor device
US4005453A (en) * 1971-04-14 1977-01-25 U.S. Philips Corporation Semiconductor device with isolated circuit elements and method of making
US4008107A (en) * 1973-09-27 1977-02-15 Hitachi, Ltd. Method of manufacturing semiconductor devices with local oxidation of silicon surface

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
SE373984B (https=) * 1973-03-19 1975-02-17 Ericsson Telefon Ab L M
CA1010157A (en) * 1974-01-14 1977-05-10 Bernard T. Murphy Oxide isolated integrated circuit structure and method for fabricating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005453A (en) * 1971-04-14 1977-01-25 U.S. Philips Corporation Semiconductor device with isolated circuit elements and method of making
US4008107A (en) * 1973-09-27 1977-02-15 Hitachi, Ltd. Method of manufacturing semiconductor devices with local oxidation of silicon surface
US3933540A (en) * 1973-10-17 1976-01-20 Hitachi, Ltd. Method of manufacturing semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
W. J. Evans, "Oxide Isolated Low-implanted Bipolar Transistors for High Packing Density and Low Power-Delay Product," Digest of Technical Papers of the 1973 IEEE International Solid-State Circuits Conference, Philadelphia, Pa., (Feb. 14-16, 1973), pp. 174-175. *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228450A (en) * 1977-10-25 1980-10-14 International Business Machines Corporation Buried high sheet resistance structure for high density integrated circuits with reach through contacts
US4196440A (en) * 1978-05-25 1980-04-01 International Business Machines Corporation Lateral PNP or NPN with a high gain
US4333774A (en) * 1979-03-20 1982-06-08 Fujitsu Limited Method for producing walled emitter type bipolar transistors
US4677456A (en) * 1979-05-25 1987-06-30 Raytheon Company Semiconductor structure and manufacturing method
US4289550A (en) * 1979-05-25 1981-09-15 Raytheon Company Method of forming closely spaced device regions utilizing selective etching and diffusion
US4355320A (en) * 1979-05-31 1982-10-19 Siemens Aktiengesellschaft Light-controlled transistor
US4261763A (en) * 1979-10-01 1981-04-14 Burroughs Corporation Fabrication of integrated circuits employing only ion implantation for all dopant layers
US4435225A (en) 1981-05-11 1984-03-06 Fairchild Camera & Instrument Corporation Method of forming self-aligned lateral bipolar transistor
US4408387A (en) * 1981-09-28 1983-10-11 Fujitsu Limited Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
US4519128A (en) * 1983-10-05 1985-05-28 International Business Machines Corporation Method of making a trench isolated device
US4547793A (en) * 1983-12-27 1985-10-15 International Business Machines Corporation Trench-defined semiconductor structure
US4725562A (en) * 1986-03-27 1988-02-16 International Business Machines Corporation Method of making a contact to a trench isolated device
US5013672A (en) * 1987-10-23 1991-05-07 Sgs-Thomson Microelectronics S.R.L. Manufacturing process for high-frequency bipolar transistors
US5128741A (en) * 1988-06-16 1992-07-07 Telefonaktiebolaget L M Ericsson Methods producing on a semi-conductor substructure a bipolar transistor, or a bipolar and a field effect transistor or a bipolar and a field effect transistor with a complementary field effect transistor and devices resulting from the methods

Also Published As

Publication number Publication date
GB1530010A (en) 1978-10-25
DE2605641B2 (de) 1979-04-19
FR2341206A1 (fr) 1977-09-09
DE2605641A1 (de) 1977-08-18
IT1074663B (it) 1985-04-20
DE2605641C3 (de) 1979-12-20
FR2341206B1 (https=) 1983-05-20
JPS5299078A (en) 1977-08-19

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