US20180197762A1 - Apparatus and Methods for Testing Semiconductor Devices - Google Patents

Apparatus and Methods for Testing Semiconductor Devices Download PDF

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Publication number
US20180197762A1
US20180197762A1 US15/864,778 US201815864778A US2018197762A1 US 20180197762 A1 US20180197762 A1 US 20180197762A1 US 201815864778 A US201815864778 A US 201815864778A US 2018197762 A1 US2018197762 A1 US 2018197762A1
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wafer
alignment
assembly
test
probe card
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Abandoned
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US15/864,778
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English (en)
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Christian O. Cojocneanu
Lucian Scurtu
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Individual
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Individual
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Priority to US15/864,778 priority Critical patent/US20180197762A1/en
Publication of US20180197762A1 publication Critical patent/US20180197762A1/en
Priority to US16/872,542 priority patent/US11594435B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices
    • G01R31/2867—Handlers or transport devices, e.g. loaders, carriers, trays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2868—Complete testing stations; systems; procedures; software aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2893—Handling, conveying or loading, e.g. belts, boats, vacuum fingers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2865—Holding devices, e.g. chucks; Handlers or transport devices

Definitions

  • the invention in its various embodiments relates generally to equipment for testing semiconductor devices, such as semiconductor wafers, and methods for such testing.
  • the invention in its various embodiments relate to a multisite parallel tester for testing multiple semiconductor wafers concurrently.
  • the integrated circuits on semiconductor wafers are typically tested for functional defects prior to die packaging. It is desirable to perform such testing as efficiently and economically as possible. Therefore, there is a need for testing equipment that provides for efficient and economical testing of semiconductor wafers.
  • the invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site.
  • Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly.
  • the robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck. Testing is then commenced and once completed, the wafer can be retrieved.
  • the following description provides additional details about the various components of the tester and the methods used for aligning and testing a given wafer.
  • the tester leverages a single wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly over a two-dimensional array of test sites.
  • the tester is configured as a four-by-eight array of 32 test sites provided by four modular racks, each containing eight test sites from top to bottom. It should be appreciated, however, that other configurations are possible.
  • the leveraging of a single wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly is achieved by means of a mobile design that can be moved using a Cartesian rack robot to place the assembly in position for servicing each individual test site.
  • wafers are automatically aligned inside each test site and the entire array of test sites is capable of testing wafers in parallel, with the test sites containing only a probe card assembly and a floating chuck used to align and hold the wafer.
  • the probe card has a large plurality of high resource gate arrays mounted on its back.
  • gate arrays contain the test engines that allow many wafers to be tested in one touchdown, without having to move the wafer to an additional test site, although it should be appreciated that the tester can be used for multiple touchdown applications as well.
  • the invention is a cost effective way to test multiple wafers in parallel, with all die on the wafer tested in one touchdown or by employing multiple touchdowns. In cases of high die count wafers or high pinout dies, the wafer will still need to be tested in multiple touchdowns, but the multitude of test sites in the present invention makes this requirement cost effective compared to other solutions.
  • a wafer probe card assembly contains a multistage seal and combines with the floating chuck to create a vacuum test chamber.
  • the probe card integrates minimum-delay-test-engines with device-limited test times capabilities.
  • a major cost savings is also achieved by the use of vacuum to compress the probe card contactor springs, without the need to perform stress relief via a convoluted stiffener structure mounted on the back side of the probe card, which would also make the mounting of all test engines on the back of the probe card prohibitive.
  • FIG. 1 illustrates a front view of a tester according to one embodiment of the present invention
  • FIG. 2 illustrates a side view of the tester of FIG. 1 according to one embodiment of the present invention
  • FIG. 3 illustrates a front view of an array of test sites within the tester of FIG. 1 according to one embodiment of the present invention
  • FIG. 4 illustrates a back view of the array of test sites within the tester of FIG. 3 according to one embodiment of the present invention
  • FIG. 5 illustrates a probe card assembly and a floating chuck according to one embodiment of the present invention
  • FIG. 6 illustrates a Cartesian robot for moving a wafer handling and alignment carriage from one test site to another according to one embodiment of the present invention
  • FIGS. 7-9 illustrate various views of the wafer handling and alignment carriage and associated assemblies according to one embodiment of the present invention.
  • FIG. 10 illustrates a top view of the wafer alignment assembly according to one embodiment of the present invention.
  • FIG. 11 illustrates a side view of the wafer alignment assembly according to one embodiment of the present invention.
  • FIG. 12 illustrates another side view of the wafer alignment assembly according to one embodiment of the present invention.
  • FIG. 13 illustrates a top view of the probe card assembly according to one embodiment of the present invention
  • FIG. 14 illustrates a floating chuck according to another embodiment of the present invention.
  • FIG. 15 illustrates a bottom perspective view of the floating chuck of FIG. 14 .
  • the invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site.
  • Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly.
  • the robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck. Testing is then commenced and once completed, the wafer can be retrieved.
  • the following description provides additional details about the various components of the tester and the methods used for aligning and testing a given wafer.
  • the tester leverages a single wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly over a two-dimensional array of test sites.
  • the tester is configured as a four-by-eight array of 32 test sites provided by four modular racks, each containing eight test sites from top to bottom. It should be appreciated, however, that other configurations are possible.
  • the leveraging of a single wafer handling and alignment carriage and the associated wafer handling robot, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly is achieved by means of a mobile design that can be moved using a Cartesian rack robot to place the assembly in position for servicing each individual test site.
  • wafers are automatically aligned inside each test site and the entire array of test sites is capable of testing wafers in parallel, with the test sites containing only a probe card assembly and a floating chuck used to align and hold the wafer.
  • the probe card has a large plurality of high resource gate arrays mounted on its back.
  • These gate arrays contain the test engines that allow many wafers to be tested in one touchdown, without having to move the wafer to an additional test site, although it should be appreciated that the tester can be used for multiple touchdown applications as well. In cases of high die count wafers or high pinout dies, the wafer will still need to be tested in multiple touchdowns, but the multitude of test sites in the present invention makes this requirement cost effective compared to other solutions.
  • FIG. 1 illustrates a front view of a tester according to one embodiment of the present invention.
  • the tester is basically a cabinet containing an array of test sites, each of which can receive a wafer for testing.
  • the array of test sites is organized as a set of four modular racks holding eight test sites from top to bottom, each of which can receive a wafer for testing.
  • the cabinet provides access to each test site through the doors shown.
  • a tester control station is also located adjacent to the test sites.
  • FIG. 2 illustrates a side view of the tester of FIG. 1 according to one embodiment of the present invention. As shown, a holding place for a set of front opening unified pods (FOUP) 1 is provided to load wafers into the tester.
  • FOUP front opening unified pods
  • FIG. 3 illustrates a front view of an array of test sites within the tester of FIG. 1 according to one embodiment of the present invention.
  • the array of test sites is a series of individual wafer test racks 2 , each having a column of individual test sites 3 .
  • there are four modular test racks 1 each having a column of eight test sites.
  • the tester in some embodiments may contain a varying number of racks and that each rack may contain a varying number of test sites. In some embodiments, the tester may contain one, two, three, or four racks, each having a column of a given number of test sites.
  • each test site 3 contains a probe card assembly 4 for testing each wafer inserted into the test site.
  • Each test site also contains a floating chuck 8 (shown and described below in connection with FIG. 5 ).
  • FIG. 4 illustrates a back view of the array of test sites within the tester of FIG. 3 according to one embodiment of the present invention.
  • a test site controller assembly 5 for each test site which controls a corresponding probe card 25 (see FIG. 13 ) is located behind a panel that separates the test site, which is accessible from the front of the tester cabinet, from the test site controller assembly, which is accessible from behind the tester cabinet.
  • FIG. 5 illustrates a probe card assembly and a floating chuck according to one embodiment of the present invention.
  • each test site contains a probe card assembly 4 and a floating chuck 8 .
  • the floating chuck 8 is disposed below the probe card assembly 4 , specifically below a probe card contactor 7 .
  • the wafer to be tested will be placed on top of the floating chuck 8 .
  • the floating chuck 8 will be brought into contact with the probe card assembly 4 as to allow the wafer to be engaged by the probe card contactor 7 .
  • the floating chuck 4 can be moved freely in any direction, including in the X-Y directions and in the Z or vertical direction, as well as rotated, to allow itself to be captured by a wafer alignment assembly 15 (see FIG. 8 ), where it receives the wafer to be tested, and to be aligned, together with the wafer, with the probe card contactor 7 .
  • the floating chuck 8 is also a dual vacuum chuck, wherein a top side vacuum is used to lock the wafer in place for testing and a bottom side vacuum is used to latch itself onto the wafer alignment assembly 15 for the duration of the wafer alignment process (see FIG. 8 ).
  • FIG. 6 illustrates a Cartesian robot for moving a wafer handling and alignment carriage from one test site to another according to one embodiment of the present invention.
  • the test racks 2 are shown from the side, and a single Cartesian rack robot 10 is mounted in front of the test racks 2 so that the test sites 3 can be accessed by the Cartesian rack robot 10 .
  • the Cartesian rack robot 10 is used to move a wafer handling and alignment carriage 9 (shown at the top of the test racks 2 ), from one test site to another test site.
  • the wafer handling and alignment carriage 9 holds a wafer handling robot 11 , a wafer rotation pre-alignment assembly 12 , a wafer alignment assembly 15 , a wafer FOUP 14 , and a wafer camera assembly 13 , which are described further in connection with FIGS. 7-9 .
  • the wafer handling and alignment carriage 9 and the associated wafer handling robot 11 , the wafer rotation pre-alignment assembly 12 , the wafer alignment assembly 15 , the wafer FOUP 14 , and the wafer camera assembly 13 is generally used to facilitate the movement of wafers into and from each test site and to align the wafers on the floating chuck 8 for subsequent alignment with the probe card contactor 7 .
  • Cartesian rack robot 10 can move the wafer handling and alignment carriage 9 , along with the associated wafer handling robot 11 , the wafer rotation pre-alignment assembly 12 , the wafer alignment assembly 15 , the wafer FOUP 14 , and the wafer camera assembly 13 , from any given test site to any other test site as desired.
  • the Cartesian rack robot 10 can be computer controlled to move the wafer handling and alignment carriage 9 to and from any given test site to place and retrieve wafers as necessary or as desired based upon the testing performed.
  • FIGS. 7-9 illustrate various views of the components of a wafer handling and alignment carriage and associated assemblies according to one embodiment of the present invention.
  • FIGS. 7-9 show a wafer buffer FOUP assembly 11 and a wafer rotation pre-alignment assembly 12 .
  • a wafer handling robot 11 loads up to twenty-four wafers from one of the input/output FOUPs 1 to the wafer buffer FOUP 14 .
  • the wafer handling robot 11 will then place a wafer from the wafer buffer FOUP 14 on the wafer rotation pre-alignment assembly 12 .
  • the wafer rotation pre-alignment assembly 12 receives a wafer it will proceed with the rotational alignment of the wafer.
  • the Cartesian rack robot 10 will then move to the first available test site and will dock the wafer handling and alignment carriage 9 in front of that test site.
  • the wafer alignment assembly 15 having two wafer alignment modules 19 , 20 will then be inserted inside the test site to perform wafer alignment to ultimately align the wafer with the probe card within the test site.
  • the wafer camera assembly 13 (see also FIG. 12 ) will be inserted inside the test site between the floating chuck 8 and the probe card assembly 4 .
  • FIG. 11 illustrates the relative positions of the wafer alignment assembly 15 , the wafer camera assembly 13 , and the floating chuck 8 , noting that all of these components at this point are positioned within a given test site.)
  • the wafer on the wafer rotation pre-alignment assembly 12 will be moved by the wafer handling robot 11 from the wafer rotation pre-alignment assembly 12 to a position above the floating chuck 8 .
  • the Z (vertical) stage of the first wafer alignment module (WAM 1 ) 19 is activated to place the top contact platform of the wafer alignment assembly 15 in contact with the floating chuck 8 .
  • the wafer alignment assembly 15 is moved up in a vertical direction to meet the bottom of the floating chuck 8 .
  • the floating chuck alignment assembly vacuum is turned on to latch the floating chuck 8 to the wafer alignment assembly 15 , which places the wafer above the floating chuck 8 .
  • three wafer cameras 16 are mounted on the wafer camera assembly 13 .
  • the wafer cameras 16 will feed images from the edges of the wafer and markers on the floating chuck 8 that will allow for optical alignment of the floating chuck 8 such that it will be centered under the wafer to be tested.
  • the wafer handling robot 11 will lower the wafer onto the floating chuck 8 , and while the alignment of the floating chuck 8 with the wafer is monitored, a floating chuck wafer vacuum will be turned on to lock the wafer in place on top of the floating chuck 8 .
  • wafer cameras 16 With the wafer firmly in place on top of the floating chuck 8 , wafer cameras 16 will feed images of the wafer notch and wafer outline points at +/ ⁇ 35 degrees, noting that different angles can be chosen.
  • two additional cameras 17 also mounted on the wafer camera assembly 13 and placed radially at the same+/ ⁇ 35 degrees but on the larger diameter, feed images of alignment reticles AR 2 and AR 3 22 (see FIG. 11 ) mounted on a wafer alignment base plate 23 of the wafer alignment assembly 15 (see FIG. 12 ) at the same angle and distance from the wafer alignment assembly center (home position) as these two additional wafer cameras 17 on the wafer camera assembly 13 . Processing the optical alignment information will place the wafer in the center and aligned with the wafer alignment base plate 23 of the wafer alignment assembly 15 .
  • an ultra-high resolution alignment process will start, which employs a piezo-based wafer alignment module 20 , which is the second wafer alignment module mounted on top of the wafer alignment assembly 15 (see FIG. 9 ).
  • This process will use the same cameras noted above to perform alignment with a precision of up to three orders of magnitude higher than the precision otherwise achieved without the piezo-based alignment module 20 .
  • the alignment will be performed for each of the X and Y directions as well as for a rotational position.
  • the wafer alignment assembly factory X/Y/Rotation offsets of the wafer alignment assembly 15 are applied.
  • the application of the offsets involves both wafer alignment assembly module 1 19 and wafer alignment assembly module 2 20 .
  • Wafer alignment assembly factory X/Y/Rotation offsets are generated when the wafer alignment assembly 15 is manufactured.
  • the wafer alignment assembly 15 is installed on a high precision optical measurement system to measure the X/Y/Rotational offsets of the wafer alignment assembly module 2 20 mounted on top of the alignment assembly module 1 19 , with regards to alignment assembly reticles 22 (see FIG. 11 ). These offsets are then stored electronically in a wafer alignment assembly controller for later use during the wafer alignment processes.
  • the factory Z/Y/Rotation offsets of the probe card assembly 4 are applied.
  • the application of the offsets involves both alignment assembly module 1 19 and wafer alignment assembly module 2 20 .
  • Probe card assembly factory X/Y/Rotation offsets are generated when the probe card assembly 4 is manufactured.
  • the probe card assembly 4 is installed on a high precision optical measurement system to measure the X/Y/Rotational offsets of the probe card assembly 4 , with regards to the probe card assembly reticles 26 .
  • These offsets are then stored electronically in a probe card controller 24 for later use during the wafer alignment processes.
  • FIG. 10 illustrates a top view of the wafer alignment assembly according to one embodiment of the present invention.
  • FIG. 11 illustrates a side view of the wafer alignment assembly of FIG. 10 according to one embodiment of the present invention.
  • FIG. 12 illustrates another view of the wafer alignment assembly according to one embodiment of the present invention.
  • FIG. 13 illustrates a top view of the probe card assembly according to one embodiment of the present invention.
  • the wafer camera assembly 13 can be retracted to its home position to clear the space between the wafer placed on the floating chuck 8 and the probe card assembly 4 . Then, the alignment of the wafer mounted on the floating chuck 8 with the probe card assembly 4 is performed.
  • four alignment assembly cameras 21 are mounted on the wafer alignment assembly 15 (see also FIG. 10 ). These four cameras 21 feed images of four probe card reticles 26 disposed on the bottom side of the probe card assembly 4 as shown in FIG. 13 .
  • the floating chuck 8 is aligned based on the captured images.
  • the piezo-based ultra-high resolution alignment process will start again, employing the second wafer alignment assembly module 2 20 .
  • This process will use the same four alignment assembly cameras 21 to perform the final alignment with a precision of up to three orders of magnitude higher.
  • the alignment will be performed for each of the X and Y directions as well as for a rotational position.
  • the Z (vertical) stage of the first wafer alignment module 1 19 is activated again in order to bring the wafer in contact with the probe card contactor 7 and the floating chuck 8 in contact with the wafer probe card assembly multilayer seal 6 (see FIG. 5 ). Throughout this process the alignment assembly cameras 21 will continuously monitor the alignment with the four probe card reticles 26 to correct any incurred misalignment during the Z (vertical) motion.
  • the outer perimeter area of the floating chuck 8 extending beyond the size of the wafer will come in contact with the probe card assembly multilayer seal 6 .
  • the friction of the seal and the contact points will start having an effect with regards to keeping the wafer aligned.
  • a test chamber vacuum is turned on, which will start exerting a force to press the wafer against the probe card contactor 7 .
  • motion in the Z (vertical) direction will continue for a determined distance, during which it will work in tandem with the vacuum to compress the contactor pins.
  • the Z motion of the first wafer alignment module 1 19 will be stopped and the floating chuck alignment assembly vacuum will be turned off to disengage the floating chuck 8 from the wafer alignment assembly 15 .
  • a wafer die detecting routine will then be started on the wafer tester to detect the die contacts on the entire surface of the wafer.
  • the test position is within the expected calibrated range for the specific test site and if all die can be detected by the tester, or the test chamber vacuum is locked and monitored, and the wafer test is started. However, if the test position is reached, or the maximum test chamber vacuum is reached, or the maximum test height is reached, and not all die are detected by the die detecting routine, a determination and decision is taken if the testing should commence or if the wafer contact routine should be repeated.
  • the wafer alignment assembly 15 Upon test start, the wafer alignment assembly 15 is being returned to the home position on the wafer handling and alignment carriage 9 , and the carriage is released by the test site for serving other test sites.
  • the test chamber vacuum is precisely monitored and kept at the same level, as to assure no Z-movement of the floating chuck 8 .
  • the wafer handling and alignment carriage 9 is requested to return to the test site for service.
  • the test chamber vacuum is gradually reduced as to allow the floating chuck 8 to disengage from the probe card assembly 4 .
  • the test chamber vacuum is reduced up to a minimum level as to allow the floating chuck 8 to stabilize at a test terminate position where it will wait to be picked up by the wafer alignment assembly 15 and lowered to the floating chuck home position for pickup by the wafer handling robot 11 .
  • FIG. 14 illustrates a floating chuck according to another embodiment of the present invention.
  • a floating chuck 27 is attached to a probe card assembly plate 28 through the use of two sets of dual ball joint damper assemblies 29 .
  • Each dual ball joint damper assembly 29 includes two dampers 30 with ball joints 31 at each end.
  • One end of each assembly 29 is attached to the probe card assembly plate 28 and the other end is attached to the floating chuck 27 .
  • this embodiment allows for smoother alignment of the floating chuck, compared having a floating chuck supported by, for example, a roller guide and air cylinders. When not engaged, the floating chuck 27 is resting in its home position as shown.
  • FIG. 15 illustrates a bottom perspective view of the floating chuck of FIG. 14 .
  • the floating chuck 27 is attached to the probe card assembly plate 28 using the two sets of dual ball joint damper assemblies 29 , each having two dampers 30 and ball joints 31 at each end.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Environmental & Geological Engineering (AREA)
  • Robotics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
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US16/872,542 US11594435B2 (en) 2017-01-08 2020-05-12 Apparatus and methods for testing semiconductor devices

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