US20160064533A1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
US20160064533A1
US20160064533A1 US14/828,046 US201514828046A US2016064533A1 US 20160064533 A1 US20160064533 A1 US 20160064533A1 US 201514828046 A US201514828046 A US 201514828046A US 2016064533 A1 US2016064533 A1 US 2016064533A1
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region
film
insulating film
gate electrode
formation region
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Fukuo Owada
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of US20160064533A1 publication Critical patent/US20160064533A1/en
Priority to US15/201,609 priority Critical patent/US9685453B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species

Definitions

  • the present invention relates to a manufacturing technology of a semiconductor device, for example, a technology effective when applied to a manufacturing technology of a semiconductor device having a main circuit including a field effect transistor and a nonvolatile memory as an add-on circuit.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2007-234861
  • Semiconductor devices having a main circuit including a field effect transistor sometimes have, in addition to the main circuit for achieving the main function of the semiconductor device, an addition circuit (add-on circuit) to be added to the main circuit.
  • an addition circuit include electronic fuses to be used for trimming or relief of the main circuit and memories for storing trimming information.
  • one of the most popular electronic fuses is an OTP (one time program) type electronic fuse that achieves [0]/[1] by the application of a large current to a polysilicon film to physically fuse it.
  • OTP one time program
  • MTP multi time program
  • NV memory nonvolatile memory
  • NV memory nonvolatile memory having a floating gate structure and suited for mix-loading with a field effect transistor included in a main circuit.
  • Using such a nonvolatile memory increases the size of a memory cell so that a shift to a nonvolatile memory capable of downsizing a memory cell is under investigation.
  • a nonvolatile memory having a MONOS (metal oxide nitride oxide semiconductor) structure as an addition circuit.
  • a manufacturing step of a main circuit including a field effect transistor should incorporate therein a manufacturing step of the nonvolatile memory having a MONOS structure. This may raise a manufacturing cost of a semiconductor device. More specifically, mix-loading of the nonvolatile memory having a MONOS structure with the field effect transistor of the main circuit increases the number of masks. There is therefore a demand for reducing the number of masks to be added and thereby reducing the manufacturing cost of the semiconductor device.
  • a gate electrode of a nonvolatile memory cell is formed in a memory formation region by patterning a conductor film with a mask that covers a gate electrode formation region of the memory formation region and exposes an MISFET formation region (field effect transistor formation region); and then, an n ⁇ type semiconductor region of the nonvolatile memory cell is formed in a semiconductor substrate by ion implantation using the above-mentioned mask without changing it to another one.
  • a gate electrode of a nonvolatile memory cell is formed in a memory formation region by patterning a conductor film with a mask that covers a gate electrode formation region of the memory formation region and exposes an MISFET formation region; and then, an n ⁇ type semiconductor region of the nonvolatile memory cell is formed in a semiconductor substrate by ion implantation using, as a mask, the gate electrode of the nonvolatile memory cell exposed by removing the above-mentioned mask.
  • a semiconductor device having both a nonvolatile memory cell and a field effect transistor can be manufactured at a reduced cost.
  • FIG. 1 shows a layout configuration example of a semiconductor chip of First Embodiment
  • FIG. 2 shows one example of a circuit block configuration of a nonvolatile memory
  • FIG. 3 is a cross-sectional view showing a device structure example of the semiconductor chip of First Embodiment
  • FIG. 4 is an explanatory view showing one example of the memory array structure and operation conditions of the nonvolatile memory
  • FIG. 5 is a flow chart showing the flow of manufacturing steps of a semiconductor device in related technology
  • FIG. 6 is a flow chart showing the flow of manufacturing steps of a semiconductor device of First Embodiment
  • FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of First Embodiment.
  • FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7 ;
  • FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8 ;
  • FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9 ;
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10 ;
  • FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11 ;
  • FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12 ;
  • FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13 ;
  • FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14 ;
  • FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15 ;
  • FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16 ;
  • FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17 ;
  • FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 18 ;
  • FIG. 20 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 19 ;
  • FIG. 21A shows a residue pattern formed in a boundary region in First Embodiment and FIG. 21B shows a technology of leaving a resist film in a boundary region and intentionally forming a large residue pattern;
  • FIG. 22 is a cross-sectional view showing a manufacturing step of a semiconductor device of Modification Example 1;
  • FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22 ;
  • FIG. 24 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 23 ;
  • FIG. 25 is a cross-sectional view showing a manufacturing step of a semiconductor device of Modification Example 2;
  • FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25 ;
  • FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26 ;
  • FIG. 28 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 27 ;
  • FIG. 29 is a cross-sectional view showing a manufacturing step of a semiconductor device of Modification Example 3;
  • FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29 ;
  • FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 30 ;
  • FIG. 32 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 31 ;
  • FIG. 33 shows a layout configuration example of a semiconductor chip of Second Embodiment
  • FIG. 34 shows a device structure example of the semiconductor chip of Second Embodiment
  • FIG. 35 is a cross-sectional view showing a manufacturing step of a semiconductor device of Second Embodiment.
  • FIG. 36 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 35 ;
  • FIG. 37 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 36 ;
  • FIG. 38 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 37 ;
  • FIG. 39 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 38 ;
  • FIG. 40 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 39 ;
  • FIG. 41 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 40 ;
  • FIG. 42 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 41 ;
  • FIG. 43 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 42 ;
  • FIG. 44 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 43 ;
  • FIG. 45 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 44 ;
  • FIG. 46 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 45 ;
  • FIG. 47 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 46 ;
  • FIG. 48 shows a device structure example of a semiconductor chip of Third Embodiment
  • FIG. 49 is a flow chart showing the flow of manufacturing steps of a semiconductor device in related technology
  • FIG. 50 is a flow chart showing the flow of manufacturing steps of a semiconductor device of Third Embodiment.
  • FIG. 51 is a cross-sectional view showing a manufacturing step of the semiconductor device of Third Embodiment.
  • FIG. 52 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 51 ;
  • FIG. 53 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 52 ;
  • FIG. 54 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 53 ;
  • FIG. 55 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 54 ;
  • FIG. 56 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 55 ;
  • FIG. 57 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 56 ;
  • FIG. 58 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 57 ;
  • FIG. 59 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 58 ;
  • FIG. 60 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 59 ;
  • FIG. 61 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 60 ;
  • FIG. 62 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 61 ;
  • FIG. 63 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 62 ;
  • FIG. 64 is a cross-sectional view showing a manufacturing step of a semiconductor device of a modification example
  • FIG. 65 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 64 ;
  • FIG. 66 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 65 .
  • the number of elements is not limited to a specific number but may be more or less than the specific number, unless otherwise particularly specified or principally apparent that the number is limited to the specific number.
  • constituent component including component step or the like
  • the constituent component is not always essential unless otherwise particularly specified or principally apparent that it is essential.
  • the technical concept in First Embodiment is a technical concept on a semiconductor device having, in one semiconductor chip, a main circuit for achieving a main function of the semiconductor chip and an addition circuit to be added to the main circuit and called “add-on circuit” and having, as the add-on circuit, a MONOS type rewritable nonvolatile memory.
  • SOC system on chip
  • a memory circuit such as DRAM (dynamic random access memory) or SRAM (static random access memory)
  • a logic circuit such as CPU (central processing unit) or MPU (micro processing unit)
  • a mixed circuit of such a memory circuit and a logic circuit examples of the add-on circuit include a storage circuit for storing relatively small capacity information relating to the main circuit and an electronic fuse to be used for relief of a circuit.
  • the relatively small capacity information include location address information of an element to be used for trimming in a semiconductor chip, location address information of a memory cell to be used for relief of a memory circuit, and product number of a semiconductor device.
  • Examples of the relatively small capacity information when the semiconductor chip is an LCD (liquid crystal display) driver include trimming tap information of an adjusting voltage to be used for LCD image adjustment.
  • the semiconductor chip in First Embodiment includes a low breakdown voltage MISFET (metal insulator semiconductor field effect transistor) that is driven at a relatively low voltage, a high breakdown voltage MISFET that is driven at a relatively high voltage to enable high-voltage driving, and a rewritable nonvolatile memory cell.
  • MISFET metal insulator semiconductor field effect transistor
  • breakdown voltage to be used for describing the MISFET means a pn junction breakdown voltage generated at a boundary of the MISFET between a source region and a semiconductor substrate (well) or between a drain region and the semiconductor substrate (well) or dielectric breakdown voltage of a gate insulating film.
  • a semiconductor substrate has thereon a high breakdown voltage MISFET having a relatively high breakdown voltage and a low breakdown voltage MISFET having a relatively low breakdown voltage.
  • FIG. 1 shows a layout configuration example of a semiconductor chip CHP 1 of First Embodiment.
  • the semiconductor chip CHP 1 has a CPU 1 , a ROM (read only memory) 2 , a RAM 3 , an analog circuit 4 , a nonvolatile memory 5 , and an I/O (input/output) circuit 6 .
  • the CPU 1 is also called a central processing unit and is the heart of a computer. This CPU 1 reads and decodes instructions from a memory device and based on them, performs a variety of operations or controls. It is required to have high-speed processing properties.
  • An MISFET configuring the CPU 1 needs, among the elements formed over the semiconductor chip CHP 1 , a relatively high current driving force capability. This means that the CPU 1 is comprised of a low breakdown voltage MISFET.
  • the ROM 2 is a memory in which memory information is unchangeably fixed and is called a read only memory.
  • the ROM 2 has two types of configuration, that is, an NAND type in which MISFETs are coupled in series and an NOR type in which MISFETs are coupled in parallel.
  • the NAND type and NOR type are often used for integration degree-oriented purpose and operation rate-oriented purpose, respectively.
  • the ROM 2 is also required to have high speed operability so that MISFETs configuring the ROM 2 need relatively high current driving force capability. This means that the ROM 2 is comprised of low breakdown voltage MISFETs.
  • the RAM 3 is a memory capable of reading the stored information at random, which means reading the stored information at any time, or capable of writing the stored information newly. It is also called a random access memory.
  • the RAM 3 as an IC memory has two types, that is, a DRAM (dynamic RAM) using a dynamic circuit and a SRAM (static RAM) using a static circuit.
  • the DRAM is a random access memory which needs memory retaining operation
  • the SRAM is a random access memory which does not need memory retaining operation. Since the RAM 3 needs high speed operability, the MISFETs configuring the RAM 3 need relatively high current driving force capability. This means that the RAM 3 is comprised of low breakdown voltage MISFETs.
  • the analog circuit 4 is a circuit handling signals of a voltage or current which show a continuous time-dependent change, that is, analog signals. It is composed of, for example, an amplification circuit, conversion circuit, modulation circuit, oscillation circuit and power supply circuit. Such an analog circuit 4 uses, among elements formed over the semiconductor chip CHP 1 , a high breakdown voltage MISFET having a relatively high breakdown voltage.
  • the nonvolatile memory 5 is one of nonvolatile memories capable of electrically rewriting both write operation and erase operation and is also called “electrically erasable programmable read only memory”.
  • this nonvolatile memory 5 is comprised of a MONOS transistor.
  • the MONOS transistor makes use of, for example, the Fowler-Nordheim tunneling phenomenon for its write operation and erase operation. It can also make use of hot electrons or hot holes for its write operation or erase operation.
  • a high potential difference (about 12V) is applied to the MONOS transistor so that a transistor having a relatively high breakdown voltage is necessary as the MONOS transistor.
  • the I/O circuit 6 is an input/output circuit and is a circuit for outputting data from the semiconductor chip CHP 1 to an apparatus coupled to the outside of the semiconductor chip CHP 1 or inputting data from the apparatus coupled to the outside of the semiconductor chip CHP 1 to the semiconductor chip CHP 1 .
  • This I/O circuit 6 is comprised of a high breakdown voltage MISFET having a relatively high breakdown voltage.
  • the main circuit is comprised of the CPU 1 , the ROM 2 , the RAM 3 , and the analog circuit 4 , while the add-on circuit is comprised of the nonvolatile memory 5 .
  • the semiconductor chip CHP 1 of First Embodiment has the main circuit for achieving a main function and the add-on circuit to be added to the main circuit.
  • First Embodiment is different from the related art in that a MONOS transistor is used as the add-on circuit. Due to this difference, the present embodiment provides the following advantages.
  • the add-on circuit includes an electronic fuse and this electronic fuse is comprised of a MONOS transistor which is a rewritable nonvolatile memory
  • a MTP (multi time program) type electronic fuse that can be adjusted repeatedly in a wafer form or package form can be achieved (first advantage).
  • a nonvolatile memory (NV memory) having a floating gate structure and suited for mix-loading with a field effect transistor included in the main circuit has been used as a memory for storing trimming information, but it increases the size of the memory cell.
  • NV memory nonvolatile memory
  • the memory cell can be downsized.
  • the MONOS transistor enables rewriting of data at a constant current and low power consumption, because it uses an FN tunneling current for rewriting of data.
  • First Embodiment the difference of First Embodiment from the related art is in that in the semiconductor device equipped with the main circuit and the add-on circuit, a MONOS transistor is used as the add-on circuit.
  • some measures are taken for a manufacturing technology of the semiconductor device. These measures taken in First Embodiment are those relating to the technology of mix-loading the MONOS transistor which is a constituent component of the add-on circuit with the low breakdown voltage MISFET and the high breakdown voltage MISFET which are constituent components of the main circuit. These measures will be described later.
  • FIG. 2 shows one example of the circuit block configuration of the nonvolatile memory 5 .
  • the nonvolatile memory 5 has a memory array 10 and as a drive circuit for driving the memory array 10 , a direct peripheral circuit portion 11 and an indirect peripheral circuit portion 12 for the memory array 10 .
  • the memory array 10 is a memory portion of the nonvolatile memory 5 , and it has a number of memory cells arranged two-dimensionally in rows and columns (in array form). Each memory cell is a circuit for storing 1 bit as a unit of information and it is comprised of an MONOS transistor which is a memory portion.
  • the drive circuit is a circuit for driving the memory array 10 and it has, as the direct peripheral circuit portion 11 , for example, a booster circuit for boosting a voltage level by several times from a power supply voltage, a clock generator circuit for boosting, a voltage clamp circuit, a column decoder or row address decoder for selecting a column or row, a column latch circuit, a WELL control circuit, and the like.
  • MISFETs configuring the direct peripheral circuit portion 11 are comprised of high breakdown voltage MISFETs that require a relatively high breakdown voltage among the elements which the semiconductor chip CHP 1 has.
  • the indirect peripheral circuit portion 12 formed is a programmable control circuit of the memory array, and it is comprised of a setting circuit and circuits having a programmable clock generator unit for ordinary use, a programmable clock generator unit for high speed use, a programmable timing control unit, and the like, respectively.
  • MISFETs configuring the indirect peripheral circuit portion 12 are comprised of low breakdown voltage MISFETs which can be driven at a relatively low voltage and can be operated at high speed, among the elements which the semiconductor chip CHP 1 has.
  • FIG. 3 is a cross-sectional view showing a device structure example of the semiconductor chip CHP 1 of First Embodiment.
  • a memory formation region MR a main circuit formation region AR
  • a boundary region BR sandwiched between the memory formation region MR and the main circuit formation region AR and the main circuit formation region AR is comprised of a low breakdown voltage MISFET formation region LR and a high breakdown voltage MISFET formation region HR.
  • the memory formation region MR has therein a memory cell of the nonvolatile memory 5 shown in FIG. 1 and this memory cell is comprised of a MONOS transistor MC.
  • the low breakdown voltage MISFET formation region LR has therein a low breakdown voltage MISFETQ 1 that requires large current driving force capability for enabling high-speed operation.
  • Such a low breakdown voltage MISFETQ 1 can be formed, for example, in the formation region of the CPU 1 , the ROM 2 , or the RAM 3 .
  • the low breakdown voltage MISFETQ 1 operates at a power supply voltage of, for example, about 1.5V.
  • the high breakdown voltage MISFET formation region HR has therein a high breakdown voltage MISFETQ 2 and such a high breakdown voltage MISFETQ 2 can be formed, for example, in the formation region of the analog circuit 4 or the I/O circuit 6 .
  • This high breakdown voltage MISFETQ 2 operates at a power supply voltage of, for example, about 5V.
  • the semiconductor substrate 1 S has therein an element isolation region STI for isolating elements and active regions isolated by the element isolation region STI are the memory formation region MR, the low breakdown voltage MISFET formation region LR, and the high breakdown voltage MISFET formation region HR, respectively.
  • the semiconductor substrate 1 S of the memory formation region MR, the low breakdown voltage MISFET formation region LR, and the high breakdown voltage MISFET formation region HR has therein a well isolation layer NISO and the well isolation layer NISO has thereon a well.
  • the well isolation layer NISO has thereon a p well MPW.
  • the well isolation layer NISO has thereon a p well PW and in the high breakdown voltage MISFET formation region HR, the well isolation layer NISO has thereon a p well HPW. In the boundary region BR, the well isolation layer NISO has thereon an isolation layer HNW.
  • an n channel MISFET is illustrated and described as an MISFET formed in each of the low breakdown voltage MISFET formation region LR and the high breakdown voltage MISFET formation region HR, but these regions each have therein a p channel MISFET.
  • the MONOS transistor MC formed in the memory formation region MR has the following configuration. Described specifically, the p well MPW formed in the semiconductor substrate 1 S has thereon an insulating film (potential barrier film) IF 1 and the insulating film IF 1 has thereon a charge storage film EC. This charge storage film EC has thereon an insulating film (potential barrier film) IF 2 .
  • the insulating film IF 2 has thereon a gate electrode CG made of a conductive film.
  • the gate electrode CG is comprised of a stacked film of, for example, a polysilicon film PF 2 and a silicide film CS in order to lower the resistance.
  • the gate electrode CG has, on both side walls thereof, a side wall SW made of, for example, an insulating film to form an LDD (lightly doped drain) structure.
  • the semiconductor substrate 1 S below the side wall SW has therein, as a semiconductor region, an n ⁇ type semiconductor region MLD and an n + type semiconductor region NDF.
  • the p well MPW has therein a channel region just below the insulating film IF 1 .
  • the insulating film IF 1 functioning as a gate insulating film is made of, for example, a silicon oxide film and it also functions as a tunnel insulating film.
  • This MONOS transistor MC stores or erases data by injecting electrons into the charge storage film EC from the semiconductor substrate 1 S via the insulating film IF 1 or ejecting electrons stored in the charge storage film EC to the semiconductor substrate 1 S so that insulating film IF 1 functions as a tunnel insulating film.
  • the charge storage film EC is a film provided for storing charges contributing to data memory and it is made of, for example, a silicon nitride film.
  • a polysilicon film has conventionally been used mainly as the charge storage film EC.
  • a polysilicon film is used as the charge storage film EC and an oxide film surrounding the charge storage film EC has, in a portion thereof, a defect, all the charges stored in the charge storage film EC may escape due to abnormal leakage because the charge storage film EC is a conductor.
  • a silicon nitride film which is an insulator has come to be used as the charge storage film EC.
  • charges contributing to the data memory are stored in a discrete trap level (trap level) present in the silicon nitride film. Even if a defect appears in a portion of the oxide film surrounding the charge storage film EC, all the charges do not escape from the charge storage film EC because charges are stored in the discrete trap level of the charge storage film EC. The reliability of data retention can therefore be improved.
  • the reliability of data retention can be improved by using, as the charge storage film EC, not only a silicon nitride film but also a film containing a discrete trap level.
  • the side wall SW is formed to obtain a source region and a drain region, which are semiconductor regions of the MONOS transistor MC, having an LDD structure. Described specifically, the source region and the drain region of the MONOS transistor MC are each made of an n ⁇ type semiconductor region MLD and an n + type semiconductor region NDF. Electric field concentration below the end portion of the gate electrode CG can be suppressed by forming the source region and the drain region below the gate electrode CG from the n ⁇ type semiconductor region MLD.
  • the p well PW formed in the semiconductor substrate 1 S has thereon a gate insulating film GOX 1 .
  • This gate insulating film GOX 1 has thereon a gate electrode G 1 .
  • the gate insulating film GOX 1 is made of, for example, a silicon oxide film and the gate electrode G 1 is made of, for example, a stacked film of a polysilicon film PF 1 and a silicon film CS in order to have a reduced resistance.
  • the gate electrode G 1 has, on both side walls thereof, a side wall SW and the semiconductor substrate 1 S below this side wall SW has therein, as a semiconductor region, an n ⁇ type semiconductor region LNLD and an n + type semiconductor region NDF.
  • the P well PW just below the gate insulating film GOX 1 has therein a channel region.
  • the p well HPW formed in the semiconductor substrate 1 S has thereon a gate insulating film GOX 2 and this gate insulating film GOX 2 has thereon a gate electrode G 2 .
  • the gate insulating film GOX 2 is made of, for example, a silicon oxide film and the gate electrode G 2 is made of, for example, a stacked film of a polysilicon film PF 1 and a silicide film CS in order to have a reduced resistance.
  • the gate electrode G 2 has, on both side walls thereof, a side wall SW and the semiconductor substrate 1 S below the side wall SW has therein, as a semiconductor region, an n ⁇ type semiconductor region HNLD and an n + type semiconductor region NDF.
  • the p well HPW just below the gate insulating film GOX 2 has therein a channel region.
  • a gate length of the gate electrode G 2 of the high breakdown voltage MISFETQ 2 is set longer than that of the gate length G 1 of the low breakdown voltage MISFETQ 1 .
  • the low breakdown voltage MISFETQ 1 by decreasing the gate length of the gate electrode G 1 and thereby reducing the resistance between the source region and the drain region, current driving force capability should be improved.
  • the high breakdown voltage MISFETQ 2 a relatively high potential is applied so that a decrease in gate length may cause punch-through between the source region and the drain region.
  • a voltage applied to the high breakdown voltage MISFETQ 2 is higher than that applied to the low breakdown voltage MISFETQ 1 so that the gate insulating film GOX 2 is thicker than the gate insulating film GOX 1 of the low breakdown voltage MISFETQ 1 .
  • the gate insulating film GOX 2 of the high breakdown voltage MISFETQ 2 has improved insulation resistance tolerance.
  • the boundary region BR has therein a residue pattern LFT which is a trace of a manufacturing step. More specifically, the residue pattern LFT in First Embodiment is, as shown in FIG. 3 , comprised of a residue portion LFT 3 which is a residue of the polysilicon film PF 2 , a residue portion LFT 2 which is a residue of a stacked insulating film comprised of the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 , and a residue portion LFT 1 which is a residue of the polysilicon film PF 1 .
  • the residue portion LFT 3 is formed in sidewall form on the side surface of the residue portion LFT 1 via the residue portion LFT 2 .
  • the semiconductor device of First Embodiment has a configuration as described above.
  • the operation of the memory cell (nonvolatile memory cell) included in the semiconductor device will next be described.
  • FIG. 4 is an explanatory view showing one example of the memory array structure and operation conditions (1 cell/1 transistor) of the nonvolatile memory 5 shown in FIG. 1 .
  • Cell transistors CT 1 to CT 8 in FIG. 4 each correspond to a memory cell comprised of the MONOS transistor MC shown in FIG. 3 .
  • the gate electrodes of the cell transistors CT 1 to CT 8 are coupled to word lines WL 1 to WL 2 and their source regions are coupled to source lines SL 1 to SL 4 . Their drain regions are coupled to data lines DL 1 to DL 4 .
  • the back gates of the cell transistors CT 1 , CT 2 , CT 5 and CT 6 are coupled to a well WE 1 , while the back gates of the cell transistors CT 3 , CT 4 , CT 7 and CT 8 are coupled to a well WE 2 .
  • memory cells are arranged in two rows and four columns in FIG. 4 , but they are not limited thereto. In practice, more memory cells are arranged in matrix form and configure a memory array.
  • the memory cell arrangement which shares the same well and the same word line is two-column configuration of, for example, the cell transistors CT 1 and CT 2 . In an 8-bit (1 byte) configuration, eight columns of cell transistors share the same well. In this case, the erase and write operations of the memory cell are performed one byte at a time.
  • the erase operation will be described. For example, supposing that data stored in the cell transistors CT 1 and CT 2 as a memory cell whose data are to be erased (selected memory cell) are erased.
  • the potentials of the selected well WE 1 , word line WL 1 , source lines SL 1 and SL 2 , and data lines DL 1 and DL 2 are set at 1.5V, ⁇ 8.5V, 1.5V, and floating potential, respectively.
  • the charges stored in the charge storage film of the cell transistors CT 1 and CT 2 are then withdrawn to the semiconductor substrate side and the data are erased.
  • the potentials of the non-selected well WE 2 , word line WL 2 , source lines SL 3 and SL 4 , and data lines DL 3 and DL 4 are set at ⁇ 8.5V, 1.5V, 1.5V, and floating potential, respectively. Escape of the charges stored in the charge storage film of the cell transistors CT 3 to CT 8 is thus prevented, whereby the data are not erased.
  • the write operation For example, supposing that data are written in the cell transistor CT 1 as the memory cell in which the data are to be written (selected memory cell).
  • the potentials of the selected well WE 1 , word line WL 1 , source line SL 1 , and data line DL 1 are set at ⁇ 10.5V, 1.5V, ⁇ 10.5V, and floating potential, respectively.
  • the charges are then injected into the charge storage film of the cell transistors CT 1 and the data are written therein.
  • the potentials of the non-selected well WE 2 , word line WL 2 , source lines SL 2 to SL 4 , and data lines DL 2 to DL 4 are set at ⁇ 10.5V, ⁇ 10.5V, 1.5V, and floating potential, respectively. Injection of charges into the charge storage film of the cell transistors CT 2 to CT 8 is thus prevented.
  • the potential of the non-selected well WE 2 , word line WL 2 , source lines SL 3 and SL 4 , and data lines DL 3 and DL 4 are set at ⁇ 2V, ⁇ 2V, 0V and 0V, respectively, whereby the cell transistors CT 3 to CT 8 are prevented from turning on.
  • the memory cell does not need a selected transistor.
  • the semiconductor device of First Embodiment has a main circuit for realizing a main function and an add-on circuit to be added to the main circuit.
  • a MONOS transistor is used for the add-on circuit from the standpoint of incorporation of an MTP type electronic fuse in the add-on circuit or downsizing of the nonvolatile memory cell.
  • a manufacturing step of the nonvolatile memory having a MONOS structure must be incorporated in a manufacturing step of the main circuit having a field effect transistor, which may increase a manufacturing cost of the semiconductor device.
  • This means that desired is a manufacturing process capable of mix-loading the MONOS transistor as the add-on circuit while minimizing a change in the manufacturing process of a base product having therein the main circuit. More specifically, mix-loading of the MONOS transistor with the electric field transistor of the main circuit increases the number of masks so that it is desired to reduce the number of masks added due to the mix-loading and thereby reduce the manufacturing cost of the semiconductor device.
  • FIG. 5 is a flow chart showing, in the related technology, the flow of manufacturing steps for mix-loading of a field effect transistor which is a constituent component of a main circuit and a MONOS transistor which is a constituent component of an add-on circuit.
  • a step requiring an additional mask for mix-loading of the MONOS transistor is surrounded with a broken line.
  • a well is formed in a main circuit formation region (S 1001 ). Then, a well is formed in a memory formation region (S 1002 ). At this time, an additional mask MSK 1 that covers the main circuit formation region and exposes the memory formation region is used. This means that the additional mask MSK 1 becomes necessary for the formation of the well of the MONOS transistor in the memory formation region.
  • a gate electrode is formed in the memory formation region (S 1003 ).
  • an additional mask MSK 2 becomes necessary for the formation of the gate electrode of the MONOS transistor in the memory formation region.
  • a gate electrode of the field effect transistor is formed in the main circuit formation region (S 1004 ).
  • an n ⁇ type semiconductor region (extension region) is formed in the memory formation region (S 1005 ).
  • an additional mask MSK 3 becomes necessary for the formation of the n ⁇ type semiconductor region of the MONOS transistor in the memory formation region.
  • an n ⁇ type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 1006 ).
  • a sidewall spacer is formed on each of the side wall of the gate electrode of the MONOS transistor and the side wall of the gate electrode of the field effect transistor (S 1007 ). Then, an n + type semiconductor region (diffusion layer) is formed in the memory formation region (S 1008 ). At this time, an additional mask MSK 4 becomes necessary for the formation of the n + type semiconductor region of the MONOS transistor in the memory formation region. Then, an n + type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 1009 ).
  • the field effect transistor which is a constituent component of a main circuit and the MONOS transistor which is a main constituent component of an add-on circuit can thus be mix-loaded.
  • the manufacturing steps of a semiconductor device in the related technology needs four additional masks MSK 1 to MSK 4 for mix-loading of the MONOS transistor (add-on circuit) with the base product (main circuit).
  • a further reduction in the number of additional masks (four masks) used in the related technology is desired.
  • a measure is taken to make the number of masks added for mix-loading of a MONOS transistor smaller than that in the related technology. The technical concept of First Embodiment which employs this measure will next be described.
  • FIG. 6 is a flow chart showing the flow of manufacturing steps for mix-loading of a field effect transistor which is a constituent component of a main circuit and a MONOS transistor which is a constituent component of an add-on circuit.
  • steps requiring an additional mask for mix-loading of the MONOS transistor are surrounded with a broken line.
  • a well is formed in a main circuit formation region (S 101 ). Then, a well is formed in a memory formation region (S 102 ). At this time, an additional mask MSK 1 that covers the main circuit formation region and at the same time, exposes the memory formation region is used. This means that the additional mask MSK 1 becomes necessary for the formation of the well of the MONOS transistor in the memory formation region.
  • a gate electrode is formed in the memory formation region (S 103 ).
  • an additional mask MSK 2 becomes necessary for the formation of a gate electrode of the MONOS transistor in the memory formation region.
  • an n ⁇ type semiconductor region is formed in the memory formation region (S 104 ). This means that in First Embodiment, the n ⁇ type semiconductor region is formed in alignment with the gate electrode of the MONOS transistor by ion implantation using the additional mask used in patterning for the formation of the gate electrode of the MONOS transistor without changing it to another one.
  • First Embodiment a mask is shared between processing for the formation of the gate electrode of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region in alignment with the gate electrode of the MONOS transistor.
  • First Embodiment therefore makes it possible to reduce the number of masks added for mix-loading of the MONOS transistor (first mask reduction effect).
  • a gate electrode of the field effect transistor is formed in the main circuit formation region (S 105 ). Then, an n ⁇ type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 106 ). Next, a sidewall spacer is formed on each of the side wall of the gate electrode of the MONOS transistor and the side wall of the gate electrode of the field effect transistor (S 107 ). Then, an n + type semiconductor region (diffusion layer) of the MONOS transistor is formed in the memory formation region and at the same time, an n + type semiconductor region (diffusion layer) of the field effect transistor is formed in the main circuit formation region (S 108 ).
  • the n + type semiconductor region of the MONOS transistor and the n + type semiconductor region of the field effect transistor are formed simultaneously.
  • the n + type semiconductor region of the MONOS transistor and the n + type semiconductor region of the field effect transistor are formed simultaneously by ion implantation using a common mask.
  • the number of masks to be added for mix loading of the MONOS transistor can be made smaller than that of the related technology. Described specifically, four additional masks MSK 1 to MSK 4 become necessary for mix-loading of the MONOS transistor (add-on circuit) is mix-loaded with a base product (main circuit) in the related technology. In First Embodiment, on the other hand, mix-loading of the MONOS transistor (add-on circuit) with the base product (main circuit) can be achieved using two additional masks MSK 1 and MSK 2 .
  • the MONOS transistor can be mix-loaded as an add-on circuit to be added to the main circuit while minimizing a change in the manufacturing process of the base product having therein a main circuit. As a result, a manufacturing cost of the semiconductor device can be reduced.
  • MONOS LAST is a method of forming, first, a conductor film (first conductor film) to be processed into a gate electrode of a field effect transistor which will be a constituent component of a main circuit and then forming a conductor film (second conductor film) to be processed in to a gate electrode of a MONOS transistor which will be a constituent component of an add-on circuit.
  • the manufacturing method called “MONOS LAST” is advantageous in that the influence of a heat load, which is applied at the time of forming the field effect transistor of the main circuit, on the MONOS transistor of the add-on circuit can be suppressed.
  • the manufacturing method called “MONOS LAST” is therefore a useful manufacturing method from the standpoint of suppressing application of an excessive heat load to the MONOS transistor and thereby reducing variation in characteristics of the MONOS transistor which will be a constituent component of the add-on circuit.
  • a semiconductor substrate 1 S made of a silicon single crystal implanted with a p type impurity such as boron (B).
  • the semiconductor substrate 1 S at this time is a semiconductor wafer having a substantially disk shape.
  • An element isolation region STI is formed in the semiconductor substrate 1 S.
  • the element isolation region STI is provided in order to prevent interference between elements.
  • This element isolation region STI can be formed, for example, by STI (shallow trench isolation).
  • the element isolation region STI is formed in the following manner. Described specifically, an element isolation trench is formed in the semiconductor substrate 1 S by photolithography and etching.
  • An insulating film (silicon oxide film or the like) is formed on the semiconductor substrate 1 S so as to fill the element isolation trench. Then, an unnecessary portion of the silicon oxide film on the semiconductor substrate 1 S is removed by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the element isolation region STI is thus formed by filling only the element isolation trench with the insulating film (silicon oxide film or the like).
  • a memory formation region MR and a main circuit formation region AR are separated from each other via a barrier region BR and the main circuit formation region AR is separated into a low breakdown voltage MISFET formation region LR and a high breakdown voltage MISFET formation region HR.
  • a well isolation layer NISO made of an n type semiconductor region is formed in the semiconductor substrate 1 S by implantation of an n type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 1 S. Then, by photolithography and ion implantation, a p well PW is formed in the semiconductor substrate 1 S of the low breakdown voltage MISFET formation region LR and a p well HPW is formed in the semiconductor substrate 1 S of the high breakdown voltage MISFET formation region HR.
  • An isolation layer HNW is formed below the element isolation region STI formed in the boundary region BR.
  • a conductivity impurity is implanted into a channel region of the p well PW by ion implantation in order to adjust the threshold voltage of the low breakdown voltage MISFET.
  • a conductivity type impurity is implanted into a channel region of the p well HPW by ion implantation in order to adjust the threshold voltage of the high breakdown voltage MISFET.
  • a gate insulating film GOX 1 is formed on the semiconductor substrate 1 S of the low breakdown voltage MISFET formation region LR and a gate insulating film GOX 2 is formed on the semiconductor substrate 1 S of the high breakdown voltage MISFET formation region HR and the memory formation region MR.
  • the gate insulating film GOX 1 and the gate insulating film GOX 2 are each made of, for example, a silicon oxide film and the thickness of the gate insulating film GOX 1 is smaller than that of the gate insulating film GOX 2 .
  • a polysilicon film (polycrystalline silicon film) PF 1 is formed on the entire main surface of the semiconductor substrate 1 S.
  • the resist film PR 1 is patterned by photolithography. Patterning of the resist film PR 1 is performed so as to cover the main circuit formation region AR and expose the memory formation region MR.
  • the patterned resist film PR 1 serves as an additional mask MSK 1 shown in the flow chart of FIG. 6 . By etching with the patterned resist film PR 1 as a mask, the polysilicon film PF 1 and the gate insulating film GOX 2 formed in the memory formation region MR are removed.
  • a p well MPW is formed in the semiconductor substrate 1 S of the memory formation region MR. Further, in the memory formation region MR, a conductivity type impurity is implanted into a channel region in the p well MPW by ion implantation in order to adjust the threshold voltage of the MONOS transistor.
  • an insulating film IF 1 is formed on the semiconductor substrate 1 S and the polysilicon film PF 1 , followed by the formation of a charge storage film EC on the insulating film IF 1 . Then, an insulating film IF 2 is formed on the charge storage film EC and then, a polysilicon film PF 2 is formed on the insulating film IF 2 .
  • the insulating film IF 1 is made of, for example, a silicon oxide film and for the formation of it, ISSG oxidation capable of forming a dense silicon oxide film with good film quality can be used.
  • the insulating film IF 1 has a thickness of about 4 nm.
  • the charge storage film EC is made of a silicon nitride film and can be formed, for example, by CVD.
  • the charge storage film EC has a thickness of about 10 nm.
  • the insulating film IF 2 is made of a silicon oxide film and for the formation of it, HTO (high temperature oxide) capable of forming a dense silicon oxide film with good film quality can be used.
  • the insulating film IF 2 has a thickness of about 5 nm.
  • the polysilicon film PF 2 can be formed using, for example, CVD. In such a manner, a stacked insulating film (ONO film) which is dense, is excellent in insulation resistance tolerance, and has a good film quality can be formed.
  • the resist film PR 2 is patterned by photolithography. Patterning of the resist film PR 2 is performed so as to cover a gate electrode formation region of the memory formation region MR and expose the main circuit formation region AR.
  • the patterned resist film PR 2 thus obtained becomes an additional mask MSK 2 shown in the flow chart of FIG. 6 .
  • a gate electrode CG is then formed in the memory formation region MR by patterning the polysilicon film PR 2 by using etching with the patterned resist film PR 2 as a mask.
  • a residue portion LFT 3 of the polysilicon film PF 2 is formed in sidewall form.
  • the exposed insulating film IF 2 , charge storage film EC, and insulating film IF 1 are removed using, for example, dry etching.
  • the stacked insulating film comprised of the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 remains below the gate electrode CG formed in the memory formation region MR, while a residue portion LFT 2 comprised of the insulating film IF 2 , the charge storage film EC, and the insulating film IF 1 is formed in a portion of the boundary region BR covered with the residue portion LFT 3 .
  • an n ⁇ type semiconductor region (extension region or lightly doped impurity diffusion region) MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment with the gate electrode CG by ion implantation using the mask made of the patterned resist film PR 2 without changing it to another one.
  • a mask is shared between processing for the formation of the gate electrode CG of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region MLD in alignment with the gate electrode CG of the MONOS transistor. According to First Embodiment, therefore, the number of additional masks necessary for mix-loading of the MONOS transistor can be reduced.
  • an n type impurity is also implanted in this polysilicon film PF 1 . Also in this case, however, an n type impurity can be prevented from penetrating through the polysilicon film PF 1 and being implanted into the semiconductor substrate 1 S of the main circuit formation region AR by controlling the implantation energy in the ion implantation step.
  • an n type impurity has been implanted into the polysilicon film PF 1 at a concentration higher by several orders of magnitude greater than that in the ion implantation step shown in FIG. 12 , implantation of the n type impurity into the polysilicon film PF 1 by the ion implantation step shown in FIG. 12 does not pose any problem.
  • the main circuit formation region AR not only an n channel type field effect transistor but also a p channel type field effect transistor are formed and a p type impurity is implanted into the polysilicon film PF 1 in the p channel type field effect transistor formation region.
  • the concentration of the p type impurity is however also high so that implantation of the n type impurity in the ion implantation step shown in FIG. 12 does not pose any problem.
  • a resist film PR 3 extending from the memory formation region MR to the main circuit formation region AR is formed by application. More specifically, a resist film PR 3 that covers the gate electrode CG formed in the memory formation region MR and extends over the polysilicon film PF 1 formed in the main circuit formation region AR is formed by application. Then, the resist film PR 3 is patterned by photolithography. Patterning of the resist film PR 3 is performed so as to cover the memory formation region MR and at the same time, cover a gate electrode formation region of the main circuit formation region AR.
  • the polysilicon film PF 1 is processed and a gate electrode G 1 and a gate electrode G 2 are formed in the low breakdown voltage MISFET formation region LR of the main circuit formation region AR and in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR, respectively.
  • a residue portion LFT 1 which is a residue of the polysilicon film PF 1 is formed in the boundary region BR.
  • the residue pattern LFT having a structure in which the residue portion LFT 1 has, on the side wall thereof, the residue portion LFT 3 via the residue portion LFT 2 remains.
  • a resist film PR 4 is formed on the semiconductor substrate 1 S by application.
  • the resist film PR 4 is then patterned by photolithography. Patterning of the resist film PR 4 is performed so as to cover the memory formation region MR, the boundary region BR, and the low breakdown voltage MISFET formation region LR, while exposing the high breakdown voltage MISFET formation region HR. Then, by ion implantation with the patterned resist film PR 4 as a mask, an n ⁇ type semiconductor region HNLD is formed in the semiconductor substrate 1 S of the high breakdown voltage MISFET formation region HR in alignment with the gate electrode G 2 .
  • a resist film PR 5 is formed on the semiconductor substrate 1 S by application. Then, the resist film PR 5 is patterned by photolithography. Patterning of the resist film PR 5 is performed so as to cover the memory formation region MR, the boundary region BR, and the high breakdown voltage MISFET formation region HR, while exposing the low breakdown voltage MISFET formation region LR. Then, by ion implantation with the patterned resist film PR 5 as a mask, an n ⁇ type semiconductor region LNLD is formed in the semiconductor substrate 1 S of the low breakdown voltage MISFET formation region LR in alignment with the gate electrode G 1 .
  • a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the semiconductor substrate 1 S as shown in FIG. 16 .
  • CVD can be used for the formation of the silicon oxide film and the silicon nitride film.
  • the stacked film is anisotropically etched to form a side wall SW. More specifically, the side wall SW is formed on both side walls of the gate electrode CG (staked structure: gate electrode CG+ONO film) in the memory formation region MR.
  • a side wall SW is formed on both side walls of the gate electrode G 1 and in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR, a side wall SW is formed on both side walls of the gate electrode G 2 . Also in the boundary region BR, a side wall SW is formed on the side wall of the residue pattern LFT.
  • an n + type semiconductor region (diffusion layer or heavily doped impurity diffusion region) NDF is formed in the memory formation region MR in alignment with the side wall SW.
  • the n + type semiconductor region NDF is a semiconductor region implanted with an n type impurity such as phosphor or arsenic.
  • the n + type semiconductor region NDF and the n ⁇ type semiconductor region MLD configure the source or drain region of the MONOS transistor.
  • each of the source region and drain region of the MONOS transistor can each have an LDD (lightly doped drain) structure.
  • an n + type semiconductor region NDF is formed in alignment with the side wall SW also in the low breakdown voltage MISFET formation region LR of the main circuit formation region AR.
  • the n + type semiconductor region NDF and the n ⁇ type semiconductor region LNLD configure the source or drain region of the low breakdown voltage MISFET.
  • the source region and the drain region of the low breakdown voltage MISFET can each have an LDD structure.
  • an n + type semiconductor region NDF is formed in alignment with the side wall SW also in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR.
  • the n + type semiconductor region NDF and the n ⁇ type semiconductor region HNLD configure the source or drain region of the high breakdown voltage MISFET.
  • the source region and the drain region of the high breakdown voltage MISFET can each have an LDD structure.
  • the n + type semiconductor region NDF of the MONOS transistor, the n + type semiconductor region NDF of the low breakdown voltage MISFET, and the n + type semiconductor region NDF of the high breakdown voltage MISFET are formed together.
  • the n + type semiconductor region NDF of the MONOS transistor, the n + type semiconductor region NDF of the low breakdown voltage MISFET, and the n + type semiconductor region NDF of the high breakdown voltage MISFET are formed simultaneously by ion implantation using a common mask.
  • an additional mask for the formation of the n + type semiconductor region NDF of the MONOS transistor becomes unnecessary. According to First Embodiment, therefore, the number of additional masks necessary for mix-loading of the MONOS transistor can be reduced.
  • the gate electrode CG has a stacked structure of the polysilicon film PF 2 and the silicide film CS.
  • silicon and the nickel platinum film react with each other on the surface of the n + type semiconductor region NDF to form a silicide film CS.
  • a silicide film CS made of a nickel platinum silicide film is formed on the surface of the polysilicon film PF 1 configuring the gate electrode G 1 also in the low breakdown voltage MISFET formation region LR of the main circuit formation region AR.
  • the gate electrode G 1 is comprised of the polysilicon film PF 1 and the silicide film CS.
  • a silicide film CS made of a nickel platinum silicide film is also formed as a result of a reaction between silicon and the nickel platinum film on the surface of the n + type semiconductor region NDF.
  • a silicide film CS made of a nickel platinum silicide film is formed on the surface of the polysilicon film PF 1 configuring the gate electrode G 2 also in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR.
  • the gate electrode G 2 is comprised of the polysilicon film PF 1 and the silicide film CS.
  • a silicide film CS made of a nickel platinum silicide film is formed as a result of a reaction between silicon and the nickel platinum film on the surface of the n + type semiconductor region NDF.
  • the nickel platinum silicide film is formed, but, for example, a cobalt silicide film, a nickel silicide film, a titanium silicide film, or a platinum silicide film may be formed instead of the nickel platinum silicide film.
  • the MONOS transistor is formed in the memory formation region MR of the semiconductor substrate 1 S, the low breakdown voltage MISFETQ 1 is formed in the low breakdown voltage MISFET formation region LR of the main circuit formation region AR, and the high breakdown voltage MISFETQ 2 is formed in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR.
  • a silicon nitride film SNF is formed on the main surface of the semiconductor substrate 1 S.
  • a silicon oxide film OXF is formed on the silicon nitride film SNF.
  • a contact interlayer insulating film IL comprised of the silicon nitride film SNF and the silicon oxide film OXF can be formed.
  • the surface of the contact interlayer insulating film IL is then planarized by using, for example, CMP (chemical mechanical polishing).
  • a contact hole CNT is formed in the contact interlayer insulating film IL by using photolithography and etching.
  • a titanium/titanium nitride film is formed on the contact interlayer insulating film IL including the bottom surface and the inner wall of the contact hole CNT.
  • the titanium/titanium nitride film is comprised of a stacked film of a titanium film and a titanium nitride film and can be formed using, for example, sputtering. This titanium/titanium nitride film prevents diffusion of, for example, tungsten, a material of a film to be filled in the later step, into silicon. In short, it has a so-called barrier property.
  • a tungsten film is formed on the entire main surface of the semiconductor substrate 1 S so as to fill the contact hole CNT.
  • the tungsten film can be formed, for example, by CVD.
  • An unnecessary portion of the titanium/titanium nitride film and tungsten film formed on the contact interlayer insulating film IL is removed, for example, by CMP. Then, annealing is performed in a hydrogen atmosphere to form a plug PLG.
  • an interlayer insulating film IL 1 made of, for example, a silicon oxide film is formed on the contact interlayer insulating film IL having therein the plug PLG.
  • a wiring trench is then formed in the interlayer insulating film IL 1 by photolithography and etching.
  • a tantalum/tantalum nitride film is formed on the interlayer insulating film IL 1 and also in the wiring trench.
  • the tantalum/tantalum nitride film can be formed, for example, by sputtering.
  • a copper film is formed, by electroplating with the seed film as an electrode, on the interlayer insulating film IL 1 having the wiring trench therein. Then, the copper film exposed on the interlayer insulating film IL 1 except the inside of the wiring trench is polished and removed, for example, by CMP to leave the copper film only in the wiring trench formed in the interlayer insulating film IL 1 .
  • a wiring W 1 can be formed. Another wiring is formed above the wiring W 1 , but a description on it is omitted. In such a manner, the semiconductor device of First Embodiment can be formed finally.
  • the wiring W 1 may be formed, for example, from an aluminum film instead.
  • a titanium/nitride titanium film, an aluminum film, and a titanium/titanium nitride film are formed successively on the interlayer insulating film IL 1 and the plug PLG.
  • These films can be formed using, for example, sputtering.
  • these films are patterned into a wiring W 1 by using photolithography and sputtering.
  • a wiring W 1 made of an aluminum film can be formed.
  • the first characteristic in First Embodiment is that as shown in FIGS. 10 to 12 , the polysilicon film PF 2 is processed with the patterned resist film PR 2 as a mask to form a gate electrode CG in the memory formation region MR; and then, by ion implantation using the mask without changing it to another one, the n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment of the gate electrode CG.
  • the first characteristic of First Embodiment is that a mask is shared between formation of the gate electrode CG of the MONOS transistor MC by processing and ion implantation for the formation of the n ⁇ type semiconductor region MLD in self alignment with the gate electrode CG of the MONOS transistor MC.
  • the number of additional masks necessary for mix-loading of the MONOS transistor MC can be reduced.
  • the second characteristic of First Embodiment is that as shown in FIG. 17 , the n + type semiconductor region NDF of the MONOS transistor MC, the n + type semiconductor region NDF of the low breakdown voltage MISFETQ 1 , and the n + type semiconductor region NDF of the high breakdown voltage MISFETQ 2 are formed simultaneously.
  • the second characteristic of First Embodiment is that the n + type semiconductor region NDF of the MONOS transistor MC, the n + type semiconductor region NDF of the low breakdown voltage MISFETQ 1 , and the n + type semiconductor region NDF of the high breakdown voltage MISFETQ 2 are formed simultaneously by ion implantation using a common mask.
  • an additional mask for forming the n + type semiconductor region NDF of the MONOS transistor MC becomes unnecessary.
  • First Embodiment therefore makes it possible to reduce the number of additional masks necessary for mix-loading of the MONOS transistor MC.
  • the number of masks to be added for mix-loading of the MONOS transistor MC can be made smaller than that in the related technology. More specifically, in the related technology, four additional masks become necessary for mix-loading of the MONOS transistor MC (add-on circuit) with the base product (main circuit). In First Embodiment, on the other hand, the MONOS transistor MC (add-on circuit) can be mix-loaded with the base product (main circuit) by using only two additional masks. According to the semiconductor device of First Embodiment, while minimizing a change in the manufacturing process of the base product having a main circuit therein, it is possible to mix-load the MONOS transistor as an add-on circuit to be added to the main circuit.
  • n ⁇ type semiconductor region MLD of the MONOS transistor MC In association with the second characteristic of First Embodiment, it seems possible to form the n ⁇ type semiconductor region MLD of the MONOS transistor MC, the n ⁇ type semiconductor region LNLD of the low breakdown voltage MISFETQ 1 , and the n ⁇ type semiconductor region HNLD of the high breakdown voltage MISFETQ 2 simultaneously. It is however difficult to simultaneously form, as the same semiconductor region, the n ⁇ type semiconductor region MLD of the MONOS transistor with the n ⁇ type semiconductor region LNLD of the low breakdown voltage MISFETQ 1 and the n ⁇ type semiconductor region HNLD of the high breakdown voltage MISFETQ 2 which configure the main circuit, from the standpoint of write operation or disturbance characteristic.
  • a step of forming the n ⁇ type semiconductor region MLD of the MONOS transistor MC is performed separately from a step of forming the n ⁇ type semiconductor region LNLD of the low breakdown voltage MISFETQ 1 or a step of forming the n ⁇ type semiconductor region HNLD of the high breakdown voltage MISFETQ 2 but the number of additional masks is reduced based on the first characteristic.
  • the n + type semiconductor region NDF of the MONOS transistor MC, the n + type semiconductor region NDF of the low breakdown voltage MISFETQ 1 , and the n + type semiconductor region NDF of the high breakdown voltage MISFETQ 2 can be formed simultaneously as the same semiconductor region by proper optimization and therefore, the number of additional masks is reduced based on the second characteristic.
  • First Embodiment by taking the measures described as the first and second characteristics in the ion implantation step for forming the source region and the drain region of the MONOS transistor MC, the number of additional masks can be reduced. As a result, in First Embodiment, due to a reduction in the number of additional masks, the manufacturing cost of a semiconductor device can be reduced.
  • FIG. 21 is an explanatory view of the third characteristic in First Embodiment.
  • the polysilicon film PF 2 for the formation of the gate electrode CG of the MONOS transistor MC is different from the polysilicon film PF 1 for the formation of the gate electrode G 1 of the low breakdown voltage MISFETQ 1 or the gate electrode G 2 of the high breakdown voltage MISFETQ 2 so that a residue pattern is inevitably formed in the boundary region BR.
  • FIG. 21B shows a technology of leaving a resist film in the boundary region BR and thereby intentionally forming a large-size residue pattern LFT(P).
  • the large-size residue pattern LFT(P) thus formed increases adhesive force of the residue pattern LFT(P) so that it gives an advantage that the residue pattern is prevented from peeling off and becoming foreign matters.
  • the increase in the size of the residue pattern has the following disadvantage. Described specifically, as shown in FIG.
  • the increase in the size of the residue pattern LFT(P) decreases a distance LB between the surface of the contact interlayer insulating film and the upper surface of the residue pattern LFT(P). This means that an increase in a thickness L 2 of the contact interlayer insulating film becomes necessary.
  • the increase in the size of the residue pattern LFT(P) is useful from the standpoint of preventing the residue pattern LFT(P) from peeling off, but this technology needs a change in the manufacturing process of the main circuit in order to ensure a distance LB between the surface of the contact interlayer insulating film and the upper surface of the residue pattern LFT(P). This process therefore has difficulty in minimizing a change in the manufacturing process of the main circuit when the MONOS transistor is mix-loaded. As a result, it increases the manufacturing cost due to a change in the manufacturing process of the main circuit.
  • FIG. 21A shows the shape of the residue pattern LFT formed in the boundary region BR in First Embodiment.
  • the residue pattern LFT is formed without leaving a resist film in the boundary region BR in First Embodiment (third characteristic).
  • the height of the residue pattern LFT is not greater than the height of the gate electrode of the field effect transistor formed in the main circuit formation region AR. This means that in First Embodiment, a distance LA can be ensured between the surface of the contact interlayer insulating film and the upper surface of the residue pattern LFT.
  • First embodiment there is no necessity of changing the thickness L 1 of the contact interlayer insulating film and a change in the manufacturing process of the main circuit can be minimized. According to First Embodiment, therefore, an increase in the manufacturing cost due to a change in the manufacturing process of the main circuit is avoidable.
  • First Embodiment Due to the synergistic effect of first and second characteristics that enable a reduction in the number of additional masks and the third characteristic that enables minimization of a change in the manufacturing process of the main circuit, First Embodiment has a marked effect on reduction in the manufacturing cost of the semiconductor device having the MONOS transistor MC as an add-on circuit to be added to a main circuit.
  • Modification Example 1 A manufacturing method of a semiconductor device in Modification Example 1 is substantially similar to that of the semiconductor device of First Embodiment so that a difference between them will be described mainly.
  • steps shown in FIGS. 7 to 9 are performed.
  • a resist film PR 2 is formed on the polysilicon film PF 2 by application and the resist film PR 2 thus formed is patterned usig photolithography.
  • the patterning of the resist film PR 2 is performed so as to cover the gate electrode formation region of the memory formation region MR and expose the main circuit formation region AR.
  • the polysilicon film PF 2 is patterned to form a gate electrode CG in the memory formation region MR.
  • an n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment with the gate electrode CG.
  • a mask is shared between processing for the formation of the gate electrode CG of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region MLD in alignment with the gate electrode CG of the MONOS transistor. Also in Modification Example 1, this makes it possible to reduce the number of additional masks to be used for mix-loading of the MONOS transistor.
  • the n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S via a stacked insulating film comprised of the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 and exposed from the gate electrode CG.
  • the characteristic of Modification Example 1 is that the n ⁇ type semiconductor region MLD is formed by ion implantation while leaving the stacked insulating film exposed from the gate electrode CG.
  • the exposed insulating film IF 2 , charge storage film EC, and insulating film IF 1 are then removed, for example, by dry etching. Steps after that are similar to those of First Embodiment.
  • the surface of the semiconductor substrate 1 S can be protected from the damage which may occur upon ion implantation.
  • the damage which may occur upon ion implantation can be reduced and at the same time, the surface of the semiconductor substrate 1 S can be prevented from contamination which may be caused by ion implantation.
  • the stacked insulating film remaining on the polysilicon film PF 1 in the main circuit formation region AR is effective for preventing easy penetration of an ion-implanted conductivity type impurity through the polysilicon film PF 1 .
  • Modification Example 2 A manufacturing method of a semiconductor device in Modification Example 2 is almost similar to that of the semiconductor device of First Embodiment so that a difference between them will be described mainly.
  • steps shown in FIGS. 7 to 9 are performed.
  • a resist film PR 2 is formed on the polysilicon film PF 2 by application and the resist film PR 2 is patterned using photolithography. Patterning of the resist film PR 2 is performed so as to cover the gate electrode formation region of the memory formation region MR and at the same time, expose the main circuit formation region AR. By etching with the patterned resist film PR 2 as a mask, the polysilicon film PF 2 is patterned to form a gate electrode CG in the memory formation region MR.
  • the insulating film IF 2 exposed from the gate electrode CG is removed, for example, by wet etching. Then, the exposed surface of the gate electrode CG is oxidized to form a silicon oxide film OX 1 on the exposed surface of the gate electrode CG.
  • the charge storage film EC made of a silicon nitride film is removed, for example, by wet etching with hot phosphoric acid.
  • an n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment with the gate electrode CG.
  • the semiconductor substrate 1 S can be prevented from the damage due to dry etching because the stacked insulating film is removed not by dry etching but by wet etching.
  • the silicon oxide film OX 1 is formed on the exposed surface of the gate electrode CG and this silicon oxide film OX 1 functions as an offset spacer during the ion implantation step using the gate electrode CG as a mask so that a short-channel effect at the MONOS transistor MC can be suppressed.
  • Modification Example 3 A manufacturing method of a semiconductor device in Modification Example 3 is substantially similar to that of the semiconductor device of First Embodiment so that a difference between them will be described mainly.
  • steps shown in FIGS. 7 to 9 are performed.
  • a resist film PR 2 is formed on the polysilicon film PF 2 by application and the resist film PR 2 is patterned using photolithography. Patterning of the resist film PR 2 is performed so as to cover the gate electrode formation region of the memory formation region MR and at the same time, expose the main circuit formation region AR. By etching with the patterned resist film PR 2 as a mask, the polysilicon film PF 2 is patterned to form a gate electrode CG in the memory formation region MR.
  • an n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment with the gate electrode CG.
  • the n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S via the stacked insulating film (the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 ) exposed from the gate electrode CG.
  • the insulating film IF 2 exposed from the gate electrode CG is removed, for example, by wet etching. Then, the exposed surface of the gate electrode CG is oxidized to form a silicon oxide film OX 1 on the exposed surface of the gate electrode CG.
  • the charge storage film EC made of a silicon nitride film is removed by wet etching with hot phosphoric acid.
  • the insulating film IF 1 exposed from the gate electrode CG is removed by wet etching (not illustrated). Steps after that are similar to those of First Embodiment.
  • the manufacturing method of the semiconductor device in Modification Example 3 can suppress the semiconductor substrate 1 S from being damaged by dry etching because the stacked insulating film is removed not by dry etching but by wet etching.
  • Second Embodiment a semiconductor device having both a main circuit having a power transistor and a MONOS transistor included in an add-on circuit will be described.
  • FIG. 33 shows a layout configuration example of a semiconductor chip CHP 2 of Second Embodiment.
  • the semiconductor chip CHP 2 of Second Embodiment has an analog circuit 4 , a nonvolatile memory 5 , an I/O circuit 6 , a logic circuit 7 , and a driver circuit 8 .
  • the logic circuit 7 is comprised of, for example, an n channel type low breakdown voltage MISFET (n type MISFET) and a p channel type low breakdown voltage MISFET (p type MISFET), while the driver circuit 8 is comprised of, for example, an n channel type power transistor (n type power transistor) and a p channel type power transistor (p type power transistor).
  • the main circuit is comprised of the analog circuit 4 , the logic circuit 7 , and the driver circuit 8 , while the add-on circuit is comprised of the nonvolatile memory 5 .
  • the semiconductor chip CHP 2 of Second Embodiment has the main circuit realizing a main function and the add-on circuit to be added to the main circuit.
  • a MONOS transistor is used for the add-on circuit.
  • the add-on circuit is comprised of an electronic fuse to be used for voltage regulation after completion of a wafer. By configuring this electronic fuse from a MONOS transistor which is a rewritable nonvolatile memory, an MTP (multi time program) type electronic fuse which can be regulated repeatedly in wafer form or package form can be realized.
  • FIG. 34 is a cross-sectional view showing the device structure example of the semiconductor chip CHP 2 in Second Embodiment.
  • FIG. 34 shows a memory formation region MR, a main circuit formation region AR, and a boundary region BR sandwiched between the memory formation region MR and the main circuit formation region AR.
  • the main circuit formation region AR is comprised of an n type MISFET formation region LR(N), a p type MISFET formation region LR(P), an n type power transistor formation region PWR(N), and a p type power transistor formation region PWR (P).
  • the semiconductor substrate 1 S has thereon a buried insulating layer BOX.
  • This buried insulating layer BOX has thereon a silicon layer SIL.
  • This silicon layer SIL has therein an element isolation region STI for isolating elements from each other. Active regions isolated by the element isolation region STI become a memory formation region MR, an n type MISFET formation region LR(N), a p type MISFET formation region LR(P), an n type power transistor formation region PWR(N), and a p type power transistor formation region PWR(P), respectively.
  • the element isolation region STI separating the n type power transistor formation region PWR(N) from the p type power transistor formation region PWR(P) has a deep trench isolation region DTI that penetrates through the silicon layer SIL and reaches the buried insulating layer BOX.
  • the MONOS transistor MC formed in the memory formation region MR has the following configuration. Described specifically, the p well MPW formed in the silicon layer SIL has thereon an insulating film (potential barrier film) IF 1 and this insulating film IF 1 has thereon a charge storage film EC. This charge storage film EC has thereon an insulating film (potential barrier film) IF 2 and the insulating film IF 2 has thereon a gate electrode CG made of a conductive film.
  • the gate electrode CG is comprised of a stacked film of, for example, a polysilicon film PF 2 and a silicide film CS in order to reduce the resistance.
  • the gate electrode CG has, on both side walls thereof, a side wall SW made of, for example, an insulating film to have an LDD structure.
  • the silicon layer SIL below the side wall SW has therein, as a semiconductor region, an n ⁇ type semiconductor region MLD and an n + type semiconductor region NDF.
  • the p well MPW just below the insulating film IF 1 has therein a channel region.
  • n type MISFETQ 1 (N) formed in the n type MISFET formation region LR(N) a p well PW formed in the silicon layer SIL has thereon a gate insulating film GOX 1 and this gate insulating film GOX 1 has thereon a gate electrode G 1 (N).
  • the gate insulating film GOX 1 is made of, for example, a silicon oxide film, while the gate electrode G 1 (N) is made of, for example, a polysilicon film.
  • the gate electrode G 1 (N) has, on both side walls thereof, a side wall SW and the silicon layer SIL below this side wall SW has therein, as a semiconductor region, an n ⁇ type semiconductor region LNLD and an n + type semiconductor region NDF.
  • the p well PW just below the gate insulating film GOX 1 has therein a channel region.
  • a p type MISFETQ 1 (P) formed in the p type MISFET formation region LR(P) an n well NW formed in the silicon layer SIL has thereon a gate insulating film GOX 1 and this gate insulating film GOX 1 has thereon a gate electrode G 1 (P).
  • the gate insulating film GOX 1 is made of, for example, a silicon oxide film, while the gate electrode G 1 (P) is made of, for example, a polysilicon film.
  • the gate electrode G 1 (P) has, on both side walls thereof, a side wall SW and the silicon layer SIL below this side wall SW has therein, as a semiconductor region, a p ⁇ type semiconductor region LPLD and a p + type semiconductor region PDF.
  • the n well NW just below the gate insulating film GOX 1 has therein a channel region.
  • the silicon layer SIL has therein an n well NWL and a p well PW which are separated from each other.
  • the n well NW is formed so as to be embraced in the n well NWL.
  • An n + type semiconductor region NDF drain region is formed so as to be embraced in the n well NW.
  • an n + type semiconductor region NDF (source region) and a p + type semiconductor region PDF (body contact region) are formed so as to be embraced in the p type well PW (body region).
  • the n + type semiconductor region NDF and the p + type semiconductor region PDF are formed so as to be adjacent to each other.
  • the silicon layer SIL has, on the surface thereof, a gate insulating film GOX 2 and this gate insulating film GOX 2 has thereon a gate electrode G 3 (N).
  • the gate electrode GOX 2 is made of, for example, a silicon oxide film and the gate electrode G 3 (N) is made of, for example, a polysilicon film.
  • the silicon layer SIL has therein a p well HPW and an n well NW which are separated from each other.
  • a p well PW is formed so as to be embraced in the p well HPW.
  • a p + type semiconductor region PDF (drain region) is formed so as to be embraced in the p well PW.
  • a p + type semiconductor region PDF (source region) and an n + type semiconductor region NDF (body contact region) are formed so as to be embraced in the n well NW (body region).
  • the p + type semiconductor region PDF and the n + type semiconductor region NDF are formed so as to be adjacent to each other.
  • the silicon layer SIL has, on the surface thereof, a gate insulating film GOX 2 and this gate insulating film GOX 2 has thereon a gate electrode G 3 (P).
  • the gate electrode GOX 2 is made of, for example, a silicon oxide film and the gate electrode G 3 (P) is made of, for example, a polysilicon film.
  • the boundary region BR has therein a residue pattern LFT which is a trace of a manufacturing step. More specifically, the residue pattern LFT in Second Embodiment is, as shown in FIG. 34 , comprised of a residue portion LFT 3 which is a residue of the polysilicon film, a residue portion LFT 2 which is a residue of the stacked insulating film comprised of the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 , and a residue portion LFT 1 which is a residue of the polysilicon film.
  • the residue portion LFT 3 is formed in sidewall form on the side surface of the residue portion LFT 1 via the residue portion LFT 2 .
  • the semiconductor device of Second Embodiment has the configuration as described above. A manufacturing method of it will hereinafter be described referring to some drawings.
  • the method of manufacturing the semiconductor device of Second Embodiment is called “MONOS LAST”.
  • This “MONOS LAST” is advantageous in that in particular, application of an excessive heat load to a MONOS transistor can be suppressed.
  • Second Embodiment is premised on mix-loading of a power transistor and a MONOS transistor. At this time, a considerably large heat load is applied to the power transistor as a manufacturing condition of it, because control of a large voltage or current is required for its usage.
  • MONOS LAST a manufacturing method called “MONOS LAST” capable of suppressing application of an excessive heat load to the MONOS transistor.
  • the manufacturing method of the semiconductor device of Second Embodiment using the manufacturing method called “MONOS LAST” will hereinafter be described.
  • a SOI (silicon on insulator) substrate having a buried insulating layer BOX on a semiconductor substrate 1 S and having a silicon layer SIL on the buried insulating layer BOX. Then, an element isolation region STI is formed in the silicon layer SIL, whereby a memory formation region MR, an n type MISFET formation region LR(N), a p type MISFET formation region LR(P), an n type power transistor formation region PWR(N), and a p type power transistor formation region PWR(P) are separated from each other.
  • a p well PW is formed in the silicon layer SIL of the n type MISFET formation region LR(N) and an n well NW in the silicon layer SIL of the p type MISFET formation region LR(P).
  • an n well NWL, an n well NW, and a p well PW are formed in the silicon layer SIL of the p type power transistor formation region PWR(N).
  • a p well HPW, a p well PW, and an n well NW are formed in the silicon layer SIL of the p type power transistor formation region PWR(P).
  • a gate insulating film GOX 1 is formed on the surface of the silicon layer SIL of each of the n type MISFET formation region LR(N) and the p type MISFET formation region LR(P), while a gate insulating film GOX 2 is formed on the surface of the silicon layer SIL of each of the n type power transistor formation region PWR(N) and the p type power transistor formation region PWR(P).
  • a polysilicon film (polycrystalline silicon film) PF 1 is formed on the entire surface of the SOI substrate.
  • the resist film PR 6 is patterned using photolithography. Patterning of the resist film PR 6 is performed so as to cover the main circuit formation region AR and at the same time, expose the memory formation region MR. Then, by etching with the patterned resist film PR 6 as a mask, the polysilicon film PF 1 and the gate insulating film GOX 1 are removed from the memory formation region MR.
  • a p well MPW is formed in the silicon layer SIL of the memory formation region MR. Further, in the memory formation region MR, a conductivity type impurity is implanted into a channel region of the p well MPW by ion implantation in order to regulate the threshold voltage of the MONOS transistor.
  • an insulating film IF 1 is formed on the SOI substrate and the polysilicon film PF 1 and a charge storage film EC is formed on this insulating film IF 1 .
  • an insulating film IF 2 is formed on the charge storage film EC, followed by the formation of a polysilicon film PF 2 on the insulating film IF 2 .
  • the insulating film IF 1 is made of, for example, a silicon oxide film and for the formation of it, ISSG oxidation capable of forming a silicon oxide film which is dense and has a good film quality can be used.
  • the insulating film IF 1 has a thickness of about 4 nm.
  • the charge storage film EC is made of a silicon nitride film and can be formed, for example, by CVD.
  • the charge storage film EC has a thickness of about 10 nm.
  • the insulating film IF 2 is made of a silicon oxide film and for the formation of it, HTO (high temperature oxide) capable of forming a silicon oxide film which is dense and has a good film quality can be used.
  • the insulating film IF 2 has a thickness of about 5 nm.
  • the polysilicon film PF 2 can be formed using, for example, CVD. In such a manner, a stacked insulating film (ONO film) which is dense, is excellent in insulation resistance tolerance, and has a good quality can be formed.
  • the resist film PR 7 is patterned by photolithography. Patterning of the resist film PR 7 is performed so as to cover a gate electrode formation region of the memory formation region MR and at the same time, expose the main circuit formation region AR. By etching with the patterned resist film PR 7 as a mask, the polysilicon film PF 2 is patterned to form a gate electrode CG in the memory formation region MR. At this time, as shown in FIG. 38 , a residue portion LFT 3 of the polysilicon film PF 2 is formed in sidewall form in the boundary region BR. Then, as shown in FIG.
  • the exposed insulating film IF 2 , charge storage film EC, and insulating film IF 1 are removed, for example, by dry etching.
  • a stacked insulating film comprised of the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 remains below the gate electrode CG formed in the memory formation region MR and at the same time, a residue portion LFT 2 comprised of the insulating film IF 2 , the charge storage film EC, and the insulating film IF 1 is formed in a portion of the boundary region BR covered with the residue portion LFT 3 .
  • an n ⁇ type semiconductor region MLD is formed in alignment with the gate electrode CG in the silicon layer SIL of the memory formation region MR.
  • a mask is shared between processing for the formation of the gate electrode CG of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region MLD in alignment with the gate electrode CG of the MONOS transistor. In Second Embodiment, this makes it possible to reduce the number of additional masks necessary for mix-loading of the MONOS transistor.
  • a resist film PR 8 extending from the memory formation region MR to the main circuit formation region AR is formed by application. More specifically, a resist film PR 8 that covers the gate electrode CG formed in the memory formation region MR and at the same time, extends over the polysilicon film PF 1 formed in the main circuit formation region AR is formed by application. Then, the resist film PR 8 is patterned by photolithography. Patterning of the resist film PR 8 is performed so as to cover the memory formation region MR and at the same time cover the gate electrode formation region of the main circuit formation region AR. By etching with the patterned resist film PR 8 as a mask, the polysilicon film PF 1 is processed.
  • a gate electrode G 1 (N) and a gate electrode G 1 (P) can be formed in the n type MISFET formation region LR(N) of the main circuit formation region AR and in the p type MISFET formation region LR(P) of the main circuit formation region AR, respectively.
  • a gate electrode G 3 (N) and a gate electrode G 3 (P) can be formed in the n type power transistor formation region PWR(N) of the main circuit formation region AR and in the p type power transistor formation region PWR(P) of the main circuit formation region AR, respectively.
  • a residual portion LFT 1 which is a residue of the polysilicon film PF 1 is formed in the boundary region BR.
  • a residue pattern LFT having a structure in which the residue portion LFT 1 has, on the side wall thereof, the residue portion LFT 3 via the residue portion LFT 2 remains in the boundary region BR.
  • a resist film PR 9 is formed on the SOT substrate by application.
  • the resist film PR 9 is patterned. Patterning of the resist film PR 9 is performed so as to cover therewith the memory formation region MR, the boundary region BR, the p type MISFET formation region LR(P), the n type power transistor formation region PWR(N), and the p type power transistor formation region PWR(N), while exposing the n type MISFET formation region LR(N).
  • an n ⁇ type semiconductor region LNLD is formed in alignment with the gate electrode G 1 (N) in the silicon layer SIL of the n type MISFET formation region LR(N).
  • a resist film PR 10 is formed on the SOT substrate by application.
  • the resist film PR 10 is patterned. Patterning of the resist film PR 10 is performed so as to cover therewith the memory formation region MR, the boundary region BR, the n type MISFET formation region LR(N), the n type power transistor formation region PWR(N), and the p type power transistor formation region PWR(N), while exposing the p type MISFET formation region LR(P).
  • a p ⁇ type semiconductor region LPLD is formed in alignment with the gate electrode G 1 (P) in the silicon layer SIL of the P type MISFET formation region LR(P).
  • a silicon oxide film is formed on the SOI substrate as shown in FIG. 44 .
  • the silicon oxide film can be formed, for example, by CVD.
  • the silicon oxide film is anisotropically etched to form a side wall SW. More specifically, in the memory formation region MR, a side wall SW is formed on both side walls of the gate electrode CG (stacked structure: gate electrode CG+ONO film).
  • a side wall SW is formed on both side walls of the gate electrode G 1 (N), while in the p type MISFET formation region LR(P) of the main circuit formation region AR, a side wall SW is formed on both side walls of the gate electrode G 1 (P). Further, a side wall SW is formed on both side walls of the gate electrode G 3 (N) in the n type power transistor formation region PWR(N) of the main circuit formation region AR and a side wall SW is formed on both side walls of the gate electrode G 3 (P) in the p type power transistor formation region PWR(P) of the main circuit formation region AR. Also in the boundary region BR, a side wall SW is formed on the side wall of the residue pattern LFT.
  • a resist film PR 11 is formed on the SOI substrate by application.
  • the resist film PR 11 is patterned. Patterning of the resist film PR 11 is performed so as to expose the memory formation region MR, the boundary region BR, the n type MISFET formation region LR(N), and a region of the n type power transistor formation region PWR(N) other than the body contact region.
  • patterning of the resist film PR 11 is performed so as to cover the p type MISFET formation region LR(P), the body contact region of the n type power transistor formation region PWR(N), and a region of the p type power transistor formation region PWR(P) other than the body contact region.
  • an n + type semiconductor region NDF is formed in the memory formation region MR in alignment with the side wall SW.
  • the source or drain region of the MONOS transistor is formed from the n + type semiconductor region NDF and n ⁇ type semiconductor region MLD.
  • an n + type semiconductor region NDF is formed also in the n type MISFET formation region LR(N) of the main circuit formation region AR in alignment with the side wall SW.
  • the source or drain region of the n type MISFET is formed from the n + type semiconductor region NDF and the n ⁇ type semiconductor region LNLD.
  • an n + type semiconductor region NDF is formed also in the n type power transistor formation region PWR(N) of the main circuit formation region AR.
  • the source or drain region of the n type power transistor is formed from this n + type semiconductor region NDF.
  • an n + type semiconductor region NDF which will be a body contact region is formed also in the p type power transistor formation region PWR(P) of the main circuit formation region AR.
  • the n + type semiconductor region NDF of the MONOS transistor, the n + type semiconductor region NDF of the n type MISFET, the n + type semiconductor region NDF of the n type power transistor, and the n + type semiconductor region NDF of the p type power transistor are formed simultaneously.
  • the n + type semiconductor region NDF of the MONOS transistor, the n + type semiconductor region NDF of the n type MISFET, the n + type semiconductor region NDF of the n type power transistor, and the n + type semiconductor region NDF of the p type power transistor are formed simultaneously by ion implantation using a common mask.
  • Second Embodiment makes it possible to reduce the number of additional masks necessary for mix loading or the MONOS transistor.
  • a resist film PR 12 is formed on the SOT substrate by application.
  • the resist film PR 12 is patterned. Patterning of the resist film PR 12 is performed so as to cover the memory formation region MR, the boundary region BR, the n type MISFET formation region LR(N), a region of the n type power transistor formation region PWR(N) other than the body contact region, and the body contact region of the p type power transistor formation region PWR(P).
  • patterning of the resist film PR 12 is performed so as to expose the p type MISFET formation region LR(P), the body contact region of the n type power transistor formation region PWR(N), and a region of the p type power transistor formation region PWR(P) other than the body contact region.
  • a p + type semiconductor region PDF is formed in the p type MISFET formation region LR(P) of the main circuit formation region AR in alignment with the side wall SW.
  • the source or drain region of the p type MISFET is formed from the resulting p + type semiconductor region PDF and the n ⁇ type semiconductor region LPLD.
  • a p + type semiconductor region PDF which will be a body contact region is formed also in the n type power transistor formation region PWR(N) of the main circuit formation region AR.
  • a p + type semiconductor region PDF is formed also in the p type power transistor formation region PWR(P) of the main circuit formation region AR.
  • the source or drain region of the p type power transistor is formed from the resulting p + type semiconductor region PDF.
  • a deep trench isolation region DTI that penetrates through the silicon layer SIL and reaches the buried insulating layer BOX is formed.
  • a wiring step thereafter is performed as in First Embodiment.
  • the semiconductor device of Second Embodiment having, mix-loaded therein, the MONOS transistor MC, the n type MISFETQ 1 (N), the p type MISFETQ 1 (P), the n type power transistor Q 3 (N), and the p type power transistor Q 3 (P) can be manufactured.
  • MONOS FIRST a manufacturing method of a semiconductor device having, mix-loaded therein, a main circuit including a field effect transistor and a MONOS transistor included in an add-on circuit.
  • FIG. 48 is a cross-sectional view showing a device structure example of a semiconductor chip CHP 3 in Third Embodiment.
  • FIG. 48 shows a memory formation region MR, a main circuit formation region AR, and a boundary region BR sandwiched between the memory formation region MR and the main circuit formation region AR.
  • the main circuit formation region AR is comprised of a low breakdown voltage MISFET formation region LR and a high breakdown voltage MISFET formation region HR.
  • the device structure of the semiconductor chip CHP 3 in Third Embodiment is substantially similar to the device structure (refer to FIG. 3 ) of the semiconductor chip CHP 1 of First Embodiment so that a difference between them will be described mainly.
  • a residue pattern LFT formed in the boundary region BR is different from the residue pattern LFT of First Embodiment. This owes to a difference in the manufacturing method of a semiconductor device.
  • a semiconductor device manufacturing method called “MONOS LAST” is used in First Embodiment, while a semiconductor device manufacturing method called “MONOS FIRST” is used in Third Embodiment. More specifically, the manufacturing method called “MONOS LAST” is used in First Embodiment so that the residue pattern LET of First Embodiment has, as shown in FIG. 3 , a structure in which the residue portion LFT 1 has, on the side wall thereof, the residue portion LFT 3 in side wall form via the residue portion LFT 2 .
  • the manufacturing method called “MONOS FIRST” is employed and as a result, as shown in FIG. 48 , the residue pattern LFT of Third Embodiment has a structure in which the residue portion LFT 3 has, on the side wall thereof, the residue portion LFT 1 in sidewall form via the residue portion LFT 2 .
  • the residue portion LFT 3 is in sidewall form
  • the residue portion LFT 1 is in sidewall form.
  • Another device structure of the semiconductor chip CHP 3 of Third Embodiment is similar to the device structure of the semiconductor chip CHP 1 in First Embodiment.
  • the manufacturing method of the semiconductor device of Third Embodiment is a method called “MONOS FIRST”.
  • the “MONOS FIRST” is a manufacturing method of forming a conductor film (second conductor film) to be processed into a gate electrode of a MONOS transistor which is a constituent component of an add-on circuit and then forming a conductor film (first conductor film) to be processed into a gate electrode of a field effect transistor which is a constituent component of a main circuit.
  • the manufacturing method called “MONOS FIRST” is advantageous because the field effect transistor of the main circuit (base product) can be suppressed from being influenced by a heat load applied during formation of the MONOS transistor.
  • the manufacturing method called “MONOS FIRST” is therefore effective particularly for suppressing application of an excessive heat load to the field effect transistor configuring the main circuit and thereby reducing variation in the characteristic of the field effect transistor which is a constituent component of the main circuit.
  • MONOS FIRST In the manufacturing method of a semiconductor device called “MONOS FIRST” similar to the manufacturing method of a semiconductor device called “MONOS LAST”, it is desired to mix-load a MONOS transistor as an add-on circuit while minimizing a change in the manufacturing process of a base product having therein a main circuit. More specifically, mix-loading of a MONOS transistor with a field effect transistor of a main circuit increases the number of masks so that it is desired to reduce the number of additional masks and thereby reduce the manufacturing cost of a semiconductor device.
  • MONOS FIRST related technology of “MONOS FIRST” will be described, followed by description on the room for improvement in this related technology.
  • FIG. 49 is a flow chart of the related technology showing the flow of manufacturing steps for mix-loading a field effect transistor which is a constituent component of a main circuit and a MONOS transistor which is a constituent component of an add-on circuit.
  • steps requiring an additional mask for mix-loading of a MONOS transistor are surrounded by a broken line.
  • a well is formed in the memory formation region (S 2001 ).
  • an additional mask MSK 1 covering the main circuit formation region and exposing the memory formation region is used. This means that the additional mask MSK 1 becomes necessary for the formation of a well of a MONOS transistor in the memory formation region.
  • a polysilicon film is formed on the entire main surface of a semiconductor substrate. Then, the polysilicon film formed in the main circuit formation region is removed while leaving the polysilicon film formed in the memory formation region (S 2002 ).
  • an additional mask MSK 2 covering the memory formation region and at the same time, exposing the main circuit formation region is used. Then, a well is formed in the main circuit formation region (S 2003 ).
  • a gate electrode is formed in the main circuit formation region (S 2004 ). Then, a gate electrode is formed in the memory formation region (S 2005 ). At this time, an additional mask MSK 3 becomes necessary for the formation of a gate electrode of the MONOS transistor in the memory formation region.
  • an n ⁇ type semiconductor region (extension region) is formed in the memory formation region (S 2006 ).
  • an additional mask MSK 4 becomes necessary for the formation of an n ⁇ type semiconductor region of the MONOS transistor in the memory formation region.
  • an n ⁇ type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 2007 ).
  • a sidewall spacer is formed on each of the side wall of the gate electrode of the MONOS transistor and the side wall of the gate electrode of the field effect transistor (S 2008 ). Then, an n + type semiconductor region (diffusion layer) is formed in the memory formation region (S 2009 ). At this time, an additional mask MSK 5 becomes necessary for the formation of the n + type semiconductor region of the MONOS transistor in the memory formation region. Next, an n + type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 2010 ).
  • Steps thereafter do not need an additional mask so that description on them is omitted.
  • the field effect transistor which is a constituent component of a main circuit and the MONOS transistor which is a constituent component of an add-on circuit can be mix-loaded in such a manner.
  • manufacturing steps of a semiconductor device according to the related technology need five additional masks MSK 1 to MSK 5 for mix-loading of the MONOS transistor (add-on circuit) with a base product (main circuit). In this point, it is desired to reduce the number of masks to be added for mix-loading of a MONOS transistor and thereby reduce the manufacturing cost of a semiconductor device.
  • third Embodiment therefore, a measure is taken to make the number of masks added for mix-loading of the MONOS transistor smaller than that of the related technology.
  • the technical concept of Third Embodiment taking this measure will next be described.
  • FIG. 50 is a flow chart showing the flow of manufacturing steps of Third Embodiment for mix-loading of a field effect transistor which is a constituent component of a main circuit and a MONOS transistor which is a constituent component of an add-on circuit.
  • a step requiring an additional mask for mix-loading of the MONOS transistor is surrounded by a broken line.
  • a well is formed in the memory formation region (S 201 ).
  • an additional mask MSK 1 that covers the main circuit formation region and exposes the memory formation region is used.
  • the additional mask MSK 1 becomes necessary for the formation of a well of the MONOS transistor in the memory formation region.
  • a polysilicon film is formed on the entire whole surface of the semiconductor substrate.
  • the polysilicon film formed in the main circuit formation region is removed while leaving the polysilicon film formed in the memory formation region (S 202 ).
  • an additional mask MSK 2 that covers the memory formation region and exposes the main circuit formation region is used.
  • a well is formed in the main circuit formation region (S 203 ).
  • a gate electrode is formed in the main circuit formation region (S 204 ). Then, a gate electrode is formed in the memory formation region (S 205 ). At this time, an additional mask MSK 3 becomes necessary for the formation of the gate electrode of the MONOS transistor in the memory formation region.
  • an n ⁇ type semiconductor region is formed in the memory formation region while using the additional mask used for the formation of the gate electrode of the MONOS transistor in the memory formation region without changing it to another one (S 206 ).
  • the n ⁇ type semiconductor region is formed in alignment with the gate electrode of the MONOS transistor by ion implantation using the additional mask used for patterning for the formation of the gate electrode of the MONOS transistor without changing it to another one.
  • a mask is shared between processing for the formation of the gate electrode of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region in alignment with the gate electrode of the MONOS transistor.
  • Third Embodiment therefore achieves a reduction in the number of additional masks used for mix-loading of the MONOS transistor (first mask reduction effect).
  • an n ⁇ type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 207 ). Then, a sidewalls pacer is formed on the side wall of each of the gate electrode of the MONOS transistor and the gate electrode of the field effect transistor (S 208 ). Then, an n + type semiconductor region of the MONOS transistor is formed in the memory formation region and at the same time, an n + type semiconductor region of the field effect transistor is formed in the main circuit formation region (S 209 ).
  • the n + type semiconductor region of the MONOS transistor and the n + type semiconductor region of the field effect transistor are formed simultaneously. In other words, in Third Embodiment, the n + type semiconductor region of the MONOS transistor and the n + type semiconductor region of the field effect transistor are formed simultaneously by ion implantation with a common mask.
  • Third Embodiment an additional mask for the formation of the n + type semiconductor region of the MONOS transistor becomes unnecessary. Third Embodiment therefore achieves a reduction in the number of additional masks used for mix-loading of the MONOS transistor (second mask reduction effect).
  • the number of additional masks used for mix-loading of the MONOS transistor can be made smaller than that of the related technology due to the above-mentioned first mask reduction effect and the second mask reduction effect. More specifically, five additional masks MSK 1 to MSK 5 become necessary for mix-loading of the MONOS transistor (add-on circuit) with the base product (main circuit) in the related technology, while mix-loading of the MONOS transistor (add-on circuit) with the base product (main circuit) requires only three additional masks MSK 1 to MSK 3 in Third embodiment.
  • the semiconductor device of Third Embodiment therefore, it is possible to mix-load the MONOS transistor as an add-on circuit to be added to a main circuit while minimizing a change in the manufacturing process of the base product having therein the main circuit. As a result, a manufacturing cost of the semiconductor device can be reduced.
  • a manufacturing method of the semiconductor device of Third Embodiment will next be described referring to drawings.
  • the manufacturing method of the semiconductor device of Third Embodiment is called “MONOS FIRST”.
  • a semiconductor substrate 1 S made of a silicon single crystal implanted with a p type impurity such as boron (B).
  • the semiconductor substrate 1 S at this time is in the form of a semiconductor wafer having a substantially disk shape.
  • An element isolation region STI is formed in the semiconductor substrate 1 S.
  • the element isolation region STI is provided in order to prevent interference between elements.
  • a well isolation layer NISO comprised of an n type semiconductor region is formed in the semiconductor substrate 1 S by implanting an n type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 1 S.
  • a resist film PR 13 is formed on the semiconductor substrate 1 S by application.
  • the resist film PR 13 is then patterned by photolithography. Pattering of the resist film PR 13 is performed to expose the memory formation region MR and cover the main circuit formation region AR.
  • a p well MPW is formed in the semiconductor substrate 1 S of the memory formation region MR.
  • a conductivity type impurity is implanted into a channel region in the p well MPW by ion implantation in order to control the threshold voltage of the MONOS transistor in the memory formation region MR.
  • an insulating film IF 1 is formed on the semiconductor substrate 1 S, followed by the formation of a charge storage film EC on the insulating film IF 1 . Then, an insulating film IF 2 is formed on the charge storage film EC and then, a polysilicon film PF 2 is formed on the insulating film IF 2 .
  • the insulating film IF 1 is made of, for example, a silicon oxide film and for the formation of it, ISSG oxidation capable of forming a dense silicon oxide film with a good film quality can be used.
  • the insulating film IF 1 has a thickness of about 4 nm.
  • the charge storage film EC is made of a silicon nitride film and can be formed, for example, by CVD.
  • the charge storage film EC has a thickness of about 10 nm.
  • the insulating film IF 2 is made of a silicon oxide film and for the formation of it, HTO (high temperature oxide) capable of forming a dense silicon oxide film with a good film quality can be used.
  • the insulating film IF 2 has a thickness of about 5 nm.
  • the polysilicon film PF 2 can be formed using, for example, CVD. In such a manner, a stacked insulating film (ONO film) which is dense, is excellent in insulation resistance tolerance, and has a good film quality can be formed.
  • a resist film PR 14 is formed on the polysilicon film PF 2 by application.
  • the resist film PR 14 is then patterned by photolithography. Patterning of the resist film PR 14 is performed so as to cover the entirety of the memory formation region MR and expose the main circuit formation region AR. Then, by etching with the patterned resist film PR 14 as a mask, the polysilicon film PF 2 and the stacked insulating film (ONO film) are removed from the main circuit formation region AR.
  • the polysilicon film PF 2 and the stacked insulating film remain in the entire memory formation region MR and processing for the formation of a gate electrode of the MONOS transistor is not performed in the memory formation region MR, because when a gate electrode of the MONOS transistor is formed in the memory formation region MR in this step, the MONOS transistor inevitably has a bird's beak due to the step of forming a gate insulating film in the main circuit formation region AR to be performed later. In Third Embodiment, therefore, to prevent the MONOS transistor from having a bird's beak, the polysilicon film PF 2 and the stacked insulating film are left in the entirety of the memory formation region MR in this step.
  • a resist film PR 15 is formed on the polysilicon film PF 2 and the semiconductor substrate 1 S by application.
  • the resist film PR 15 is then patterned by photolithography. Patterning of the resist film PR 15 is performed so as to cover the memory formation region MR and the low breakdown voltage MISFET formation region LR and at the same time, expose the high breakdown voltage MISFET formation region HR.
  • a p well HPW is formed in the semiconductor substrate 1 S of the high breakdown voltage MISFET formation region HR.
  • a p well PW is formed in the semiconductor substrate 1 S of the low breakdown voltage MISFET formation region LR and an isolation layer HNW is formed below the element isolation region STI formed in the boundary region BR by photolithography and ion implantation.
  • a gate insulating film GOX 1 is formed on the low breakdown voltage MISFET formation region LR of the semiconductor substrate 1 S and a gate insulating film GOX 2 is formed on the high breakdown voltage MISFET formation region HR of the semiconductor substrate 1 S.
  • the gate insulating film GOX 1 and the gate insulating film GOX 2 are each made of, for example, a silicon oxide film and the thickness of the gate insulating film GOX 1 is smaller than that of the gate insulating film GOX 2 .
  • the gate insulating film GOX 2 is formed on the polysilicon film PF 2 in the memory formation region MR.
  • a polysilicon film PF 1 is formed on the gate insulating film GOX 1 and the gate insulating film GOX 2 .
  • the resist film PR 16 is patterned using photolithography. Patterning of the resist film PR 16 is performed so as to cover the gate electrode formation region of the main circuit formation region AR and exposes the memory formation region MR.
  • a gate electrode G 1 is formed in the low breakdown voltage MISFET formation region LR and a gate electrode G 2 is formed in the high breakdown voltage MISFET formation region HR.
  • a residue portion LFT 2 and a residue portion LFT 1 in sidewall form are formed on the side wall of the polysilicon film PF 2 in the boundary region BR.
  • a resist film PR 17 extending from the memory formation region MR to the main circuit formation region AR is formed by application. More specifically, the resist film PR 17 that covers the gate electrode G 1 and the gate electrode G 2 formed in the main circuit formation region AR and extends over the polysilicon film PF 2 in the memory formation region MR is formed by application. Then, the resist film PR 17 is patterned by photolithography. Patterning of the resist film PR 17 is performed so as to cover the main circuit formation region AR and at the same time, cover the gate electrode formation region of the memory formation region MR.
  • the polysilicon film PF 2 is processed and a gate electrode CG is formed in the memory formation region MR. Then, the exposed insulating film IF 2 , charge storage film EC, and insulating film IF 1 are removed, for example, by dry etching.
  • a residue pattern LFT having a structure in which the residue portion LFT 3 has, on the side wall thereof, the residue portion LFT 1 via the residue portion LFT 2 remains.
  • an n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment with the gate electrode CG by ion implantation using a mask made of the patterned resist film PR 17 without changing it to another one.
  • a mask is shared between processing for the formation of the gate electrode CG of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region MLD in alignment with the gate electrode CG of the MONOS transistor.
  • the number of additional masks used for mix-loading of the MONOS transistor can be reduced.
  • a silicon oxide film OX 2 is formed on the entire main surface of the semiconductor substrate 1 S and a resist film PR 18 is formed on the resulting silicon oxide film OX 2 by application.
  • the resist film PR 18 is then patterned by photolithography. Patterning of the resist film PR 18 is performed so as to cover the memory formation region MR, the boundary region BR, and the low breakdown voltage MISFET formation region LR, while exposing the high breakdown voltage MISFET formation region HR. Then, by ion implantation with the patterned resist film PR 18 as a mask, an n ⁇ type semiconductor region HNLD is formed in the semiconductor substrate 1 S of the high breakdown voltage MISFET formation region HR in alignment with the gate electrode G 2 .
  • a resist film PR 19 is formed on the semiconductor substrate 1 S by application.
  • the resist film PR 19 is then patterned by photolithography. Patterning of the resist film PR 19 is performed so as to cover the memory formation region MR, the boundary region BR, and the high breakdown voltage MISFET formation region HR, while exposing the low breakdown voltage MISFET formation region LR. Then, by ion implantation with the patterned resist film PR 19 as a mask, an n ⁇ type semiconductor region LNLD is formed in the semiconductor substrate 1 S of the low breakdown voltage MISFET formation region LR in alignment with the gate electrode G 1 .
  • a stacked film of a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the semiconductor substrate 1 S as shown in FIG. 62 .
  • the silicon oxide film and the silicon nitride film can each be formed, for example, by CVD.
  • the stacked film is then anisotropically etched to form a side wall SW. More specifically, a side wall SW is formed on both side walls of the gate electrode CG (stacked structure: gate electrode CG+ONO film) in the memory formation region MR.
  • a side wall SW is formed on both side walls of the gate electrode G 1 and in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR, a side wall SW is formed on both side walls of the gate electrode G 2 . Also in the boundary region BR, a side wall SW is formed on the side wall of the residue pattern LFT.
  • an n + type semiconductor region NDF is formed in the memory formation region MR in alignment with the side wall SW by photolithography and ion implantation.
  • the n + type semiconductor region NDF is a semiconductor region implanted with an n type impurity such as phosphorus or arsenic.
  • the source or drain region of the MONOS transistor is formed from the n + type semiconductor region NDF and the n ⁇ type semiconductor region MLD.
  • the source region and the drain region of the MONOS transistor can have an LDD structure by forming each of the source region and the drain region of the MONOS transistor from the n + type semiconductor region NDF and the n ⁇ type semiconductor region MLD.
  • an n + type semiconductor region NDF is formed also in the low breakdown voltage MISFET formation region LR of the main circuit formation region AR in alignment with the side wall SW.
  • the source or drain region of the low breakdown voltage MISFET is formed from the n + type semiconductor region NDF and the n ⁇ type semiconductor region LNLD.
  • the source region and the drain region of the low breakdown voltage MISFET can have an LDD structure by forming each of the source region and the drain region from the n + type semiconductor region NDF and the n ⁇ type semiconductor region LNLD.
  • an n + type semiconductor region NDF is formed also in the high breakdown voltage MISFET formation region HR of the main circuit formation region AR in alignment with the side wall SW.
  • the source or drain region of the high breakdown voltage MISFET is formed from the n + type semiconductor region NDF and the n ⁇ type semiconductor region HNLD.
  • the source region and the drain region of the high breakdown voltage MISFET can have an LDD structure by forming each of the source region and the drain region from the n + type semiconductor region NDF and the n ⁇ type semiconductor region HNLD.
  • the n + type semiconductor region NDF of the MONOS transistor, the n + type semiconductor region NDF of the low breakdown voltage MISFET, and the n + type semiconductor region NDF of the high breakdown voltage MISFET are formed simultaneously.
  • the n + type semiconductor region NDF of the MONOS transistor, the n + type semiconductor region NDF of the low breakdown voltage MISFET, and the n + type semiconductor region NDF of the high breakdown voltage MISFET are formed simultaneously by ion implantation using a common mask.
  • an additional mask for the formation of the n + type semiconductor region NDF of the MONOS transistor becomes unnecessary. In Third Embodiment, therefore, the number of additional masks used for mix-loading of the MONOS transistor can be reduced.
  • Steps thereafter are similar to those of First Embodiment so that a description on them is omitted.
  • the semiconductor device of Third Embodiment can be manufactured in the above-mentioned manner.
  • a modification example will next be described.
  • the method of manufacturing a semiconductor device of the present modification example is substantially similar to that of the semiconductor device of Third Embodiment so that a difference between them will be described mainly.
  • steps shown in FIGS. 51 to 57 are performed.
  • a resist film PR 17 extending from the memory formation region MR to the main circuit formation region AR is formed by application. More specifically, the resist film PR 17 covering the gate electrode G 1 and the gate electrode G 2 formed in the main circuit formation region AR and extending over the polysilicon film PF 2 formed in the memory formation region MR is formed by application.
  • the resist film PR 17 thus obtained is then patterned by photolithography. Patterning of the resist film PR 17 is performed so as to cover the main circuit formation region AR and cover the gate electrode formation region of the memory formation region MR. By etching with the patterned resist film PR 17 as a mask, the polysilicon film PF 2 is processed and a gate electrode CG is formed in the memory formation region MR.
  • an n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S of the memory formation region MR in alignment with the gate electrode CG by ion implantation using the patterned resist film PR 17 as a mask without changing it to another one.
  • a mask is shared between processing for the formation of the gate electrode CG of the MONOS transistor and ion implantation for the formation of the n ⁇ type semiconductor region MLD in alignment with the gate electrode CG of the MONOS transistor. In the present modification example, therefore, a reduction in the number of additional masks used for mix-loading of the MONOS transistor can be achieved.
  • the n ⁇ type semiconductor region MLD is formed in the semiconductor substrate 1 S via the stacked insulating film comprised of the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 and exposed from the gate electrode CG.
  • the present modification example is characterized in that the n ⁇ type semiconductor region MLD is formed by ion implantation while leaving the stacked insulating film exposed from the gate electrode CG.
  • the exposed insulating film IF 2 , charge storage film EC, and insulating film IF 1 are removed, for example, by dry etching. Steps thereafter are similar to those of Third Embodiment
  • the n ⁇ type semiconductor region MLD is formed via the stacked insulating film (the insulating film IF 1 , the charge storage film EC, and the insulating film IF 2 ) so that the surface of the semiconductor substrate 1 S can be protected from the damage during ion implantation.
  • the stacked insulating film can decrease the damage during ion implantation and at the same time, suppress contamination of the surface of the semiconductor substrate 1 S due to ion implantation.
  • step (b) after the step (a), forming the first insulating film on the semiconductor substrate;
  • step (g) after the step (f), forming an insulating film on the second conductor film and the semiconductor substrate;
  • step (i) after the step (h), patterning the first conductor film by using a third mask that covers a second gate electrode formation region of the second region and exposes the first region to form a second gate electrode of the field effect transistor in the second region;
  • step (j) after the step (i), patterning the second conductor film by using a fourth mask that covers a first gate electrode formation region of the first region and covers the second region to form the first gate electrode in the first region;
  • the manufacturing method of a semiconductor device wherein in the step (k), the first semiconductor region is formed in the semiconductor substrate via the stacked insulating film comprised of the first insulating film, the charge storage film, and the second insulating film and exposed from the first gate electrode.
  • first region and the second region have therebetween a boundary region.
  • the boundary region has therein a residue pattern.

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