US20120098126A1 - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
US20120098126A1
US20120098126A1 US13/274,296 US201113274296A US2012098126A1 US 20120098126 A1 US20120098126 A1 US 20120098126A1 US 201113274296 A US201113274296 A US 201113274296A US 2012098126 A1 US2012098126 A1 US 2012098126A1
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Prior art keywords
flip chip
solder
chip bonding
pressing
wiring board
Prior art date
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Abandoned
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US13/274,296
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English (en)
Inventor
Toshihiro Iwasaki
Takeumi KATO
Takanori Okita
Yoshikazu SHIMOTE
Shinji Baba
Kazuyuki Nakagawa
Michitaka Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BABA, SHINJI, KIMURA, MICHITAKA, IWASAKI, TOSHIHIRO, KATO, TAKEUMI, NAKAGAWA, KAZUYUKI, OKITA, TAKANORI, SHIMOTE, YOSHIKAZU
Publication of US20120098126A1 publication Critical patent/US20120098126A1/en
Priority to US15/375,072 priority Critical patent/US10037966B2/en
Abandoned legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Definitions

  • the present invention relates to a semiconductor device and processing technologies therefor and in particular to a technology effectively applicable to flip chip bonding using solder bumps.
  • Patent Document 1 A technique for taking the following measure in a manufacturing process for semiconductor devices (semiconductor packages) is described in, for example, Japanese Unexamined Patent Publication No. 2007-227555 (Patent Document 1): a semiconductor device with molding resin exposed on the ball surface side is flip chip joined to a wiring board and underfill resin is filled between them.
  • flip chip bonded semiconductor devices are known.
  • the following are electrically coupled together by flip chip bonding: multiple solder bumps formed over a semiconductor chip (hereafter, also simply referred to as chip) and solder bumps formed over the main surface of a substrate in positions corresponding to them.
  • chip semiconductor chip
  • solder bumps formed over the main surface of a substrate in positions corresponding to them solder bumps formed over the main surface of a substrate in positions corresponding to them.
  • the following advantages are obtained: the footprint of a semiconductor chip can be reduced as compared with wire bonded semiconductor devices; the number of surface electrodes of a semiconductor chip can be increased; and the signal speed between a semiconductor chip and a substrate can be enhanced.
  • the number of pins of each semiconductor device has tended to be increased.
  • the bump pitch over each semiconductor chip has also tended to be narrowed. Consequently, the gap between bumps is also narrow; therefore, the following can take place when flip chip bonding is carried out using flux: when flux is cleaned off, cleaning fluid cannot get into between a chip and a substrate; and cleaning fluid is less prone to be discharged from between a chip and a substrate and this leads to the production of a residue, and as a result, the flux cannot be completely cleaned off.
  • FIG. 27 to FIG. 30 illustrate the procedure for fluxless flip chip bonding in a comparative example examined by the present inventors; and the drawings from FIG. 31 to FIG. 33 illustrate how a solder bridge results in solder bump bonding in the comparative example.
  • a wiring board 2 is positioned and placed in position over the upper surface of a bonding stage 19 heated to a temperature close to a solder melting point.
  • the bonding stage 19 is provided with an exhaust system 19 a and is exhausted to vacuum through this exhaust system 19 a and is caused to suck and hold the wiring board 2 .
  • the bonding head 18 is provided with an exhaust system 18 a and is exhausted to vacuum through this exhaust system 18 a and is caused to suck and hold the semiconductor chip 4 .
  • the semiconductor chip 4 is positioned (aligned) to a predetermined position by the movement of the bonding head 18 in the horizontal direction and in this state, it is positioned above the wiring board 2 . Since the bonding head 18 is heated to the predetermined preheat temperature higher than the solder melting point, in this state, the solder bumps 5 ( 5 b ) formed over the semiconductor chip 4 are melted.
  • the bonding head 18 is moved down to place the semiconductor chip 4 in position over the wiring board 2 . Since the semiconductor chip 4 is sucked to the lower surface of the bonding head 18 , it is moved down in the vertical direction as is positioned in the horizontal direction. The semiconductor chip 4 is held over the wiring board 2 for a predetermined time with a predetermined gap maintained between them and is thereby flip chip mounted over the wiring board 2 .
  • solder bumps 5 ( 5 b ) formed over the semiconductor chip 4 and the solder bumps 5 ( 5 a ) formed over the wiring board 2 are brought into contact with each other.
  • the solder bumps 5 ( 5 a ) on the substrate side are heated from the solder bumps 5 ( 5 b ) on the chip side and their temperature rises to the solder melting point or higher.
  • the melted and integrated solder bumps 5 are periodically rhythmically vibrated (scrubbed) either in the horizontal direction X or in the vertical direction Y.
  • the oxide film covering the surfaces of the solder bumps 5 is broken and taken into the solder bumps 5 and thus bonding can be carried out without use of flux.
  • the suction of the semiconductor chip 4 to the bonding head 18 is canceled and the bonding head 18 is moved up to terminate the flip chip bonding.
  • solder bumps 5 a are prevented from being deformed outward by pressing and become local solder protrusions 5 c and are protruded in the solder protrusion direction 5 d .
  • a solder bridge becomes prone to be formed between adjacent bumps as illustrated in FIG. 33 .
  • solder bumps 5 a on the substrate side are nonuniformly formed.
  • a solder protrusion 5 c may be formed depending on how the above-mentioned oxide film is ripped. That is, the present inventors found that in fluxless flip chip bonding, a solder bridge results (problem).
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2007-227555 discloses a fluxless flip chip bonding technique in which the following procedure is taken: the solder balls of a bare chip and the solder balls of a wiring board are brought into contact with each other; they are heated to a temperature higher than the melting point of solder; and ultrasonic vibration is applied to the bare chip to remove the oxide film over the ball surfaces.
  • the invention has been made with the above problem taken into account and it is an object of the invention to provide a technology that enables the enhancement of joint reliability in flip chip bonding of a semiconductor device.
  • a semiconductor device includes: a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; a semiconductor chip placed over the upper surface of the wiring board by flip chip bonding; and multiple external terminals provided in the lower surface of the wiring board.
  • the shortest parts where the distance between the following patterns is shortest are placed in positions where they are not opposed to each other between the bumps: the outer shape pattern of each the electrode for flip chip bonding as viewed in a plane and the bump placement portion pattern for the electrode for flip chip bonding as viewed in a plane.
  • a manufacturing method for a semiconductor device includes the steps of: (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; (c) forming a solder ball over each of the electrodes for flip chip bonding of the wiring board; (d) after the step (c), applying flux to the multiple solder balls and then subjecting the solder balls to reflow/cleaning; and (e) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other.
  • Another manufacturing method for a semiconductor device includes the steps of; (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; (c) applying flux paste to each of the electrodes for flip chip bonding of the wiring board; (d) placing a solder ball on the flux paste over each of the electrodes for flip chip bonding; (e) after the step (d), subjecting the multiple solder balls to reflow/cleaning; and (f) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other.
  • the semiconductor chip is presssed into the wiring board by two-staged pressing, first pressing and second pressing subsequent to the first pressing, to implement the flip chip bonding.
  • FIG. 1 is a sectional view illustrating an example of the structure of a semiconductor device in a first embodiment of the invention and an enlarged partial sectional view of a flip chip bonded portion;
  • FIG. 2 is a manufacturing flowchart illustrating an example of the structure on the substrate side in the assembly of the semiconductor device illustrated in FIG. 1 ;
  • FIG. 3 is a manufacturing flowchart illustrating an example of flip chip bonding in the assembly of the semiconductor device illustrated in FIG. 1 ;
  • FIG. 4 is a manufacturing flowchart illustrating an example of an underfill application and a ball mounting in the assembly of the semiconductor device illustrated in FIG. 1 ;
  • FIG. 5 is a flowchart illustrating a first modification to the assembly of a semiconductor device in the first embodiment of the invention
  • FIG. 6 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5 ;
  • FIG. 7 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5 ;
  • FIG. 8 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5 ;
  • FIG. 9 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5 ;
  • FIG. 10 is a flowchart illustrating a second modification to the assembly of a semiconductor device in the first embodiment of the invention.
  • FIG. 11 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10 ;
  • FIG. 12 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10 ;
  • FIG. 13 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10 ;
  • FIG. 14 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10 ;
  • FIG. 15 is a manufacturing flowchart illustrating a third modification to the assembly of a semiconductor device in the first embodiment of the invention.
  • FIG. 16 is a partial sectional view illustrating a fourth modification to the assembly of a semiconductor device in the first embodiment of the invention.
  • FIG. 17 is an enlarged partial sectional view illustrating the structure of a flip chip bonded portion in a semiconductor device in a comparative example related to a second embodiment of the invention.
  • FIG. 18 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of a wiring board with the structure illustrated in FIG. 17 ;
  • FIG. 19 is a plan view illustrating the solder bridge structure taken along line A of FIG. 17 as viewed from above;
  • FIG. 20 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of the wiring board in a semiconductor device in the second embodiment of the invention.
  • FIG. 21 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in the solder resist film illustrated in FIG. 20 ;
  • FIG. 22 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of the wiring board in a semiconductor device in a first modification to the second embodiment of the invention
  • FIG. 23 is a plan view illustrating the structure of solder bumps placed over openings in the solder resist film illustrated in FIG. 22 ;
  • FIG. 24 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in the solder resist film illustrated in FIG. 22 ;
  • FIG. 25 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in a solder resist film of the wiring board in a semiconductor device in a second modification to the second embodiment of the invention
  • FIG. 26 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in a solder resist film of the wiring board in a semiconductor device in a third modification to the second embodiment of the invention
  • FIG. 27 is a partial sectional view illustrating a procedure for fluxless flip chip bonding in a comparative example
  • FIG. 28 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example
  • FIG. 29 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example.
  • FIG. 30 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example
  • FIG. 31 is an enlarged partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example
  • FIG. 32 is an enlarged partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example.
  • FIG. 33 is an enlarged partial sectional view illustrating the structure of a solder bridge formed during the fluxless flip chip bonding in the comparative example.
  • FIG. 1 is a sectional view illustrating an example of the structure of a semiconductor device in the first embodiment of the invention and an enlarged partial sectional view of a flip chip bonded portion;
  • FIG. 2 is a manufacturing flowchart illustrating an example of the manufacture on the substrate side in the assembly of the semiconductor device illustrated in FIG. 1 ;
  • FIG. 3 is a manufacturing flowchart illustrating an example of flip chip bonding in the assembly of the semiconductor device illustrated in FIG. 1 ;
  • FIG. 4 is a manufacturing flowchart illustrating an example of an underfill application and ball mounting in the assembly of the semiconductor device illustrated in FIG. 1 .
  • the semiconductor device in the first embodiment is a semiconductor package obtained by placing a semiconductor chip 4 over a substrate by flip chip bonding.
  • BGA All Grid Array
  • the BGA 1 includes: a wiring board 2 that is a substrate having an upper surface 2 a and a lower surface 2 b located on the opposite side thereto; the semiconductor chip 4 placed over the upper surface 2 a of the wiring board 2 through multiple solder bumps (bump electrodes, solder balls) 5 and having a semiconductor integrated circuit formed therein; underfill 3 filled around each of the solder bumps 5 and around the side surface of the semiconductor chip 4 ; and multiple solder balls 7 as external terminals provided over the lower surface 2 b of the wiring board 2 .
  • the solder balls 7 are arranged, for example, in a lattice pattern in the lower surface 2 b of the wiring board 2 .
  • electrical signals sent from the semiconductor chip 4 are transmitted to solder balls 7 over the lower surface 2 b of the wiring board 2 through solder bumps 5 or wiring, through hole wiring, or the like, not shown, in the wiring board 2 .
  • the semiconductor chip 4 has: a main surface 4 a in which multiple electrode pads 4 c as surface electrodes are respectively formed in openings in a protective film 4 d ; and a back surface 4 b located on the opposite side to the main surface 4 a .
  • the semiconductor chip 4 is electrically coupled with the wiring board 2 by flip chip bonding. As illustrated in the enlarged partial sectional view in FIG. 1 , that is, the semiconductor chip 4 is electrically coupled with the electrodes 2 c for flip chip bonding of the wiring board 2 through the solder bumps 5 respectively electrically coupled to the electrode pads 4 c . Since the semiconductor chip 4 is placed over the wiring board 2 by flip chip bonding, it is face-down mounted over the wiring board 2 .
  • the upper surface 2 a of the wiring board 2 and the main surface 4 a of the semiconductor chip 4 are opposed to each other; therefore, the back surface 4 b of the semiconductor chip 4 faces upward.
  • Electronic components such as chip components 6 are mounted around the semiconductor chip 4 in the upper surface 2 a of the wiring board 2 .
  • the chip components 6 are, for example, a chip capacitor and a chip resistor and are solder mounted over the wiring board 2 through solder 8 .
  • the wiring board 2 has an upper surface 2 a and a lower surface 2 b located on the opposite side to the upper surface 2 a .
  • multiple electrodes 2 c for flip chip bonding are formed in the upper surface 2 a .
  • the wiring board 2 is a substrate that underwent wiring formation, surface insulating layer formation, land surface layer processing, and the like. In the description of the first embodiment, attention will be paid mainly to the state of the surfaces of the bumps for chip bonding.
  • solder paste for flip chip bonding is applied. That is, to form the bumps for chip bonding, solder paste 10 is applied to the electrodes 2 c for flip chip bonding illustrated in FIG. 1 .
  • the solder paste 10 is, for example, a paste material containing flux and solder at a volume ratio of approximately 50%.
  • the solder paste 10 is applied to each electrode 2 c for flip chip bonding from above by a print process using a metal mask.
  • Step S 3 a reflow/cleaning of Step S 3 is carried out.
  • heat treatment is carried out using a nitrogen reflow furnace with the oxygen concentration controlled to, for example, 100 ppm or below.
  • Solder bumps (solder balls) 5 a are thereby formed over the predetermined electrodes 2 c for flip chip bonding. Further, flux cleaning is carried out to remove flux.
  • Step S 4 a solder paste application of Step S 4 is carried out.
  • the solder paste 10 for peripheral element placement is applied only to areas where a peripheral element is to be placed by a print process using a metal mask.
  • Step S 5 peripheral element placement & reflow/cleaning of Step S 5 is carried out.
  • electronic components such as chip components 6
  • the reflow/cleaning flux cleaning
  • Step S 6 a flux application of Step S 6 is carried out.
  • flux 9 is applied to the solder bumps 5 a over the electrodes 2 c for flip chip bonding.
  • Step S 7 a reflow/cleaning of Step S 7 is carried out. That is, the flux 9 is applied to the solder bumps 5 a for flip chip bonding and then reflow and cleaning processing is carried out.
  • the following can be implemented by the flux application and reflow/cleaning (flux cleaning) after the completion of the mounting of the chip components 6 : reflow processing can be carried out without the flux 9 left over the solder bumps 5 a for flip chip bonding. Therefore, the thick and nonuniform surface oxide film over the solder bumps 5 a can be turned into a thin and uniform surface oxide film.
  • Each of the solder bumps 5 a for flip chip bonding is 80 ⁇ m in bump diameter and 50 ⁇ m in bump height when the bump pitch is, for example, 150 ⁇ m. Since it is necessary to minimize variation in bump height, it is required to supply solder with accuracy. In addition, the bump placement surface must be flat. Therefore, it is desirable to take the procedure shown in the flow in FIG. 2 . That is, it is desirable that the solder bumps 5 a for flip chip bonding should be formed first and then peripheral elements (electronic components), such as chip components 6 , should be placed.
  • solder bumps 5 a obtained by subjecting bumps formed beforehand to reflow processing without carrying out anti-oxidation processing, such as flux application, and thereafter applying flux and carrying out the reflow/cleaning again.
  • solder bumps (bump electrodes) 5 b of the semiconductor chip 4 and the solder bumps (solder balls) 5 a of the wiring board 2 are (fluxless) flip chip bonded to each other.
  • Step S 11 in FIG. 3 a chip bump heat melting & alignment of Step S 11 in FIG. 3 is carried out.
  • the wiring board 2 is positioned in a predetermined position in the supporting surface of a bonding stage 19 heated to a temperature close to a solder melting point and placed there.
  • the bonding stage 19 is provided with an exhaust system 19 a and is exhausted to vacuum through this exhaust system 19 a to suck and hold the wiring board 2 .
  • the back surface 4 b of the semiconductor chip 4 is sucked and held by the suction surface of a bonding head 18 preheated to a predetermined preheat temperature higher than the solder melting point.
  • the bonding head 18 is provided with an exhaust system 18 a and is exhausted to vacuum through this exhaust system 18 a to suck and hold the semiconductor chip 4 .
  • the semiconductor chip 4 is positioned (aligned) in a predetermined position by the movement of the bonding head 18 in the horizontal direction and in this state, it is positioned above the wiring board 2 . Since the bonding head 18 is heated to the predetermined preheat temperature higher than the solder melting point, in this state, the solder bumps 5 ( 5 b ) formed over the semiconductor chip 4 are melted.
  • Step S 12 a chip/substarate bump contacting & pressing of Step S 12 is carried out.
  • the bonding head 18 is moved down to place the semiconductor chip 4 over the wiring board 2 in a predetermined position. That is, the semiconductor chip 4 is placed so that the solder bumps 5 a on the substrate side and the solder bumps 5 b on the chip side are aligned with each other. Since the semiconductor chip 4 is sucked to the suction surface of the bonding head 18 , it is moved down in the vertical direction as is positioned in the horizontal direction. The semiconductor chip 4 is held for a predetermined time with a predetermined distance maintained between the wiring board 2 and the semiconductor chip 4 and is thereby flip chip placed over the wiring board 2 .
  • solder bumps 5 b formed over the semiconductor chip 4 and the solder bumps 5 a formed over the wiring board 2 are brought into contact with each other. Further, the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side. The solder bumps 5 a on the substrate side are heated by the solder bumps 5 b on the chip side and their temperature becomes equal to or higher than the solder melting point.
  • the integrated and melted solder bumps 5 are periodically rhythmically vibrated (scrubbed) either in the horizontal direction X or in the vertical direction Y.
  • Step S 14 As shown in the illustration of, a chip releasing of Step S 14 , the suction of the semiconductor chip 4 to the bonding head 18 is canceled and the bonding head 18 is moved up to complete flip chip bonding.
  • Step S 15 in FIG. 4 an underfill application of Step S 15 in FIG. 4 is carried out.
  • underfill 3 is dripped to the side of the semiconductor chip 4 to fill the gap between the semiconductor chip 4 and the wiring board 2 with the underfill 3 . That is, the underfill 3 is filled to the flip chip bonded portions and it is also supplied to the side surface of the semiconductor chip 4 to cover the periphery of the semiconductor chip 4 with the underfill 3 .
  • the flip chip bonded portions and the semiconductor chip 4 are thereby protected.
  • Step S 16 an outer ball mounting of Step S 16 is carried out.
  • the lower surface 2 b of the wiring board 2 is provided with a predetermined number of solder balls (external terminals) 7 .
  • the flux 9 is applied to the solder bumps 5 a for flip chip bonding over the substrate before fluxless flip chip bonding is carried out.
  • flip chip bonding is carried out after the reflow/cleaning (flux cleaning) is carried out.
  • the flip chip bonding can be achieved with the oxide film over the surfaces of the solder bumps 5 a made relatively thin and uniform.
  • the surface oxide film of the solder bumps 5 a can be made uniform by forming the solder bumps 5 a of the solder paste 10 and thereafter applying the flux 9 again and carrying out the reflow/cleaning (flux cleaning) again.
  • the surface oxide film of the solder bumps 5 a on the substrate side is made uniform before fluxless flip chip bonding is carried out.
  • the shape of solder protrusions outward of solder when the solder bumps 5 a are pressed is spread (concentrically) all around the bumps (balls) by the surface tension of molten solder.
  • the solder protrusions take on such a shape that their tips are rounded.
  • solder protrusions produced at the time of solder pressing can be provided with an entire circumferential shape (concentric shape) or a rounded shape.
  • the gap between chip and substrate where a bridge between adjacent bumps is produced is reduced and it is possible to increase the amount of solder pressing.
  • the oxide film over the surfaces of the solder bumps is relatively thin and uniform, the oxide film over the surfaces of the solder bumps is easy to break and it is possible to reduce the amount of solder pressing required for bonding. As a result, it is possible to ensure a large area for pressing solder so that bonding can be achieved.
  • the BGA 1 is a semiconductor device having a structure in which chip components 6 are solder mounted around the semiconductor chip 4 . That is, after the solder bumps 5 a for flip chip bonding are formed by the reflow/cleaning, the solder 8 for the chip components 6 are subjected to the reflow/cleaning. At this stage, the solder bumps 5 a are heated and melted without flux and their surface oxide film is increased in thickness. Therefore, the surface oxide film of the solder bumps 5 a is not uniform.
  • the flux 9 is applied to the solder bumps 5 a and the reflow/cleaning (flux cleaning) is carried out again before flip chip bonding is carried out Therefore, the surface oxide film of the solder bumps 5 a can be made relatively thin and uniform by the oxide film removing effect of flux before flip chip bonding. That is, the following can be implemented even in the BGA 1 having such a structure that electronic components, such as chip components 6 , are solder mounted around the semiconductor chip 4 : the production of solder bridges can be reduced to enhance the joint reliability in flip chip bonding.
  • the melted solder bumps 5 b on the chip side are brought into contact with and pressed into the solder bumps 5 a on the substrate side during flip chip bonding.
  • the bumps at least on either side are melted during flip chip bonding, as mentioned above, protruded bumps are prone to be formed at the time of bump pressing.
  • the flip chip bonding of the BGA 1 in the first embodiment is carried out after the following procedure is taken: the solder bumps 5 a on the substrate side are subjected to the flux application and the reflow/cleaning again to make uniform the surface oxide film of the solder bumps 5 a . Therefore, the following can be implemented even when the bumps on either side are melted: the solder protrusions can be spread (concentrically) all around the bumps by the surface tension of the molten Solder and the production of solder bridges can be reduced.
  • FIG. 5 is a flowchart illustrating the first modification to the assembly of the semiconductor device in the first embodiment of the invention
  • FIG. 6 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5
  • FIG. 7 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5
  • FIG. 8 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5
  • FIG. 9 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5 .
  • the first modification is an example of assembly in which the following procedure is taken: the solder bumps 5 b on the chip side are formed by a printing method and the flux application and the reflow/cleaning are carried out only on the solder bumps 5 a on the substrate side.
  • Step S 21 in FIG. 5 A preparation of land-formed wafer of Step S 21 in FIG. 5 is carried out.
  • a wafer (semiconductor wafer) 12 including multiple electrode pads 4 c as aluminum electrodes and a protective film 12 a for protecting the surface thereof is prepared by wafer preparation of Step S 41 in FIG. 6 .
  • Step S 42 a formation of bump underlaying metal film of Step S 42 is carried out.
  • a bump underlaying metal film 12 b is formed over the electrode pads 4 c and protective film 12 a over the surface of the wafer 12 .
  • Ti, NiV, Cu, or the like is used for the bump underlaying metal film.
  • Step S 43 an etching resist film formation of Step S 43 is carried out.
  • an etching resist film 12 c is formed in multiple bump placement portions for flip chip bonding.
  • Step S 44 underlaying film etching & resist film removal of Step S 44 is carried out.
  • etching is carried out to remove the unnecessary portions of the bump underlaying metal film 12 b and then the etching resist film 12 c is removed. This establishes a state in which the bump underlaying metal film 12 b is formed over each electrode pad 4 c in the wafer 12 .
  • solder paste application of Step S 22 in FIG. 5 is carried out.
  • solder paste 10 is formed over the bump underlaying metal films 12 b in the bump placement portions by a print process using a printing mask 14 as a metal mask by solder paste printing of Step S 45 in FIG. 7 .
  • the printing mask 14 is placed around the bump underlaying metal films 12 b as the bump placement portions and then solder paste 10 is printed over the bump underlaying metal films 12 b by a print process using a squeegee 13 .
  • Step S 46 in FIG. 7 a printing mask removal of Step S 46 in FIG. 7 is carried out. At this step, the printing mask 14 over the wafer 12 is removed.
  • Step S 23 in FIG. 5 and Step S 47 in FIG. 7 are carried out.
  • the solder paste 10 over the wafer 12 is heated and melted at a predetermined temperature by ref lowing and cleaned (flux cleaning) to form multiple solder bumps 5 b.
  • Step S 24 in FIG. 5 a chip segmentation of Step S 48 in FIG. 7
  • the wafer is diced into a chip size to form semiconductor chips 4 each having multiple solder bumps 5 b placed therein.
  • wafer back surface polishing is carried out to a predetermined wafer thickness after or before the formation of the solder bumps 5 b .
  • a desired chip thickness can be obtained.
  • Step S 31 in FIG. 5 A preparation of land-formed substrate of Step S 31 in FIG. 5 is carried out.
  • the following matrix arrayed substrate 11 having a plurality of device forming areas is prepared by a substrate preparation of Step S 51 in FIG. 8 : a matrix arrayed substrate 11 having a plurality of device forming areas as a multilayer wiring board including multiple electrodes 2 c for flip chip bonding as copper lands, a solder resist film 11 a for protecting the surface thereof, and multiple land terminals 11 b formed on the back surface side.
  • solder paste 10 is formed over the multiple electrodes 2 c for flip chip bonding by a print process using a printing mask 14 as a metal mask by a solder paste printing of Step S 52 in FIG. 8 .
  • the solder paste 10 is, for example, a paste material containing flux and solder at a volume ratio of approximately 50%.
  • the printing mask 14 is placed around the electrodes 2 c for flip chip bonding and then the solder paste 10 is printed over the electrodes 2 c for flip chip bonding by a print process using a squeegee 13 .
  • Step S 53 in FIG. 8 a printing mask removal of Step S 53 in FIG. 8 is carried out.
  • the printing mask 14 over the matrix arrayed substrate 11 having a plurality of device forming areas is removed.
  • Step S 33 in FIG. 5 and Step S 54 in FIG. 8 are carried out.
  • the solder paste 10 over the electrodes 2 c for flip chip bonding of the matrix arrayed substrate 11 having a plurality of device forming areas is heated and melted at a predetermined temperature by ref lowing and cleaned to form multiple solder bumps 5 a.
  • Step S 55 in FIG. 9 a probing of Step S 55 in FIG. 9 is carried out.
  • a probe 15 is brought into contact with the multiple solder bumps 5 a over the matrix arrayed substrate 11 having a plurality of device forming areas to conduct electrical testing.
  • Step S 34 in FIG. 5 Step S 56 in FIG. 9
  • flux 9 is applied (re-applied) so as to cover the multiple solder bumps 5 a provided over the matrix arrayed substrate 11 having a plurality of device forming areas.
  • Step S 35 in FIG. 5 flux cleaning of Step S 57 in FIG. 9
  • the solder bumps 5 a over the matrix arrayed substrate 11 having a plurality of device forming areas with the flux 9 applied thereto are heated and cleaned (flux cleaning) at a predetermined temperature by reflowing. This makes it possible to eliminate variation in bump height due to a probing mark, thin the surface oxide film sticking to each of the solder bumps 5 a , and make the surface oxide film uniform.
  • Step S 58 in FIG. 9 a substrate segmentation of Step S 58 in FIG. 9 is carried out to form wiring boards 2 each having multiple solder bumps 5 a for flip chip bonding placed therein.
  • Step S 36 in FIG. 5 a flip chip bonding of Step S 36 in FIG. 5 is carried out.
  • flip chip bonding is carried out using the following semiconductor chip and wiring board: a semiconductor chip 4 with multiple solder bumps 5 b placed therein shown in the illustration of Step S 48 in FIG. 7 and a wiring board 2 with multiple solder bumps 5 a placed therein shown in the illustration of Step S 58 in FIG. 9 .
  • Step S 11 to Step S 14 in FIG. 3 the same (fluxless) flip chip bonding method as illustrated as Step S 11 to Step S 14 in FIG. 3 is used to flip chip bond the following semiconductor chip and wiring board to each other: the semiconductor chip 4 shown in the illustration of Step S 48 in FIG. 7 and the wiring board 2 shown in the illustration of Step S 58 in FIG. 9 . This completes the assembly.
  • FIG. 10 is a flowchart illustrating the second modification to the assembly of the semiconductor device in the first embodiment of the invention
  • FIG. 11 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10
  • FIG. 12 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10
  • FIG. 13 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10
  • FIG. 14 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10 .
  • the solder bumps 5 b on the chip side are formed by plating and the solder bumps 5 a on the substrate side are formed by a micro solder ball placement method. It is an example of assembly in which the flux application and the reflow/cleaning are carried out on the solder bumps 5 a on the substrate side.
  • Step S 61 in FIG. 10 A preparation of pad opening-formed wafer of Step S 61 in FIG. 10 is carried out.
  • the following wafer (semiconductor wafer) 12 is prepared by a wafer preparation of Step S 81 in FIG. 11 : a wafer in which multiple electrode pads 4 c as bump placement portions and aluminum electrodes and a protective film 12 a exposing the electrode pads 4 c by openings therein are formed.
  • Step S 82 a formation of bump underlaying metal film of Step S 82 is carried out.
  • a bump underlaying metal film 12 b (UBM) is formed over the entire surface of the wafer 12 by sputtering using the UBM (Under Bump Metal) sputtering of Step S 62 in FIG. 10 . That is, the bump underlaying metal film 12 b is formed over the electrode pads 4 c and protective film 12 a over the surface of the wafer 12 by sputtering.
  • UBM Under Bump Metal
  • Step S 83 a resist film formation of Step S 83 is carried out.
  • plating resist film formation and patterning of Step S 63 in FIG. 10 is carried out. That is, a plating resist film 12 d is applied to the wafer 12 by a spin coat method and openings are formed in positions corresponding to bump placement portions by a photoengraving process.
  • Step S 84 a plating film formation of Step S 84 is carried out.
  • formation of Ni plating film and solder plating film of Step S 64 in FIG. 10 is carried out. That is, a Ni plating film, not shown, is formed as a solder diffusion barrier over the bump underlaying metal film 12 b and then a solder plating film 12 e is formed as shown in the illustration of Step S 84 in FIG. 11 .
  • Step S 85 a resist film removal of Step S 85 is carried out. That is, the portions of the plating resist film 12 d around the solder plating films 12 e are removed.
  • Step S 86 in FIG. 12 Step S 65 in FIG. 10
  • flux 9 is applied to the multiple solder plating films 12 e over the wafer 12 by a spin coat method.
  • Step S 87 a flux cleaning of Step S 87 (reflow/cleaning of Step S 66 in FIG. 10 ) is carried out.
  • the solder plating films 12 e over the wafer 12 are heated and melted at a predetermined temperature by ref lowing and cleaned to form multiple solder bumps 5 b.
  • Step S 88 an underlaying film etching of Step S 88 is carried out.
  • the exposed bump underlaying metal films 12 b other than those located under the solder bumps 5 b are etched using the solder bumps 5 b as a mask and removed by UBM etching of Step S 67 in FIG. 10 .
  • Wafer back surface polishing is carried out as required to control the thickness of the wafer 12 to a desired value.
  • Step S 68 in FIG. 10 chip segmentation of Step S 89 in FIG. 12
  • the wafer is diced into a chip size to form semiconductor chips 4 each having multiple solder bumps 5 b placed therein.
  • Step S 71 in FIG. 10 A preparation of land-formed substrate of Step S 71 in FIG. 10 is carried out.
  • the following matrix arrayed substrate 11 having a plurality of device forming areas is prepared by a substrate preparation of Step S 91 in FIG. 13 : a matrix arrayed substrate 11 having a plurality of device forming areas as a multilayer wiring board including multiple electrodes 2 c for flip chip bonding as copper lands and a solder resist film 11 a for protecting the surface thereof.
  • the copper lands may be coated with a Ni/Au plating, a Ni/Pd/Au plating, a Sn plating, or the like.
  • Step S 72 in FIG. 10 a flux paste application of Step S 72 in FIG. 10 is carried out.
  • paste-like flux 9 (flux paste) is applied to the multiple electrodes 2 c for flip chip bonding by a print process using a printing mask 14 as a metal mask by a flux printing of Step S 92 in FIG. 13 .
  • the paste-like flux 9 is 100% flux.
  • Step S 73 in FIG. 10 a micro ball placement of Step S 73 in FIG. 10 is carried out.
  • the printing mask 14 is removed and then a ball placement mask 16 is placed in position over the matrix arrayed substrate 11 having a plurality of device forming areas by a solder ball placement of Step S 93 in FIG. 14 .
  • the ball placement mask 16 openings are formed in correspondence with the positions of the electrodes 2 c for flip chip bonding as bump placement portions.
  • small solder balls 17 as micro balls are shaken into the openings in the ball placement mask 16 . This establishes a state in which a small solder ball 17 is placed over the paste-like flux 9 (flux paste) over each of the electrodes 2 c for flip chip bonding.
  • Step S 74 in FIG. 10 and Step S 94 in FIG. 14 are carried out.
  • the small solder balls 17 placed over the paste-like flux 9 over the electrodes 2 c for flip chip bonding of the matrix arrayed substrate 11 having a plurality of device forming areas are heated and melted at a predetermined temperature by ref lowing and cleaned (flux cleaning) to form multiple solder bumps 5 a.
  • Step S 95 in FIG. 14 a substrate segmentation of Step S 95 in FIG. 14 is carried out to form wiring boards 2 each having multiple solder bumps 5 a for flip chip bonding placed therein.
  • Step S 75 in FIG. 10 flip chip bonding is carried out.
  • flip chip bonding is carried out using the following semiconductor chip and wiring board: a semiconductor chip 4 with multiple solder bumps 5 b placed therein shown in the illustration of Step S 89 in FIG. 12 and a wiring board 2 with multiple solder bumps 5 a placed therein shown in the illustration of Step S 95 in FIG. 14 .
  • Step S 11 to Step S 14 in FIG. 3 the same (fluxless) flip chip bonding method as illustrated as Step S 11 to Step S 14 in FIG. 3 is used to flip chip bond the following semiconductor chip and wiring board to each other: the semiconductor chip 4 shown in the illustration of Step S 89 in FIG. 12 and the wiring board 2 shown in the illustration of Step S 95 in FIG. 14 . This completes the assembly.
  • the flux 9 is supplied to the solder bumps 5 a on the substrate side before the semiconductor chip 4 and the wiring board 2 are flip chip bonded to each other. Further, reflow/cleaning (flux cleaning) is carried out before flip chip bonding is carried out. This makes it possible to thin the surface oxide film of the solder bumps 5 a and carry out flip chip bonding with the surface oxide films uniformly formed.
  • the other effects obtained by the first modification and the second modification are the same as the other effects obtained by the assembly of the semiconductor device (BGA 1 ) illustrated in FIG. 2 to FIG. 4 ; therefore, the repetitive description thereof will be omitted.
  • the measure described below is taken.
  • the above effects are obtained by the flip chip bonding procedure in which: the solder bumps 5 b on the chip side and the solder bumps 5 a on the substrate side are brought into contact with each other; and then they are further presses into each other to join the bumps together. Therefore, the steps up to melting and joining of bumps are carried out in a flip chip bonder.
  • bumps are pressed into each other by expansion of a bonding tool, a substrate, and the like and the same effects can be obtained even in cases where the procedures described below are taken.
  • alignment in, for example, the flow illustrated in FIG.
  • a chip bump heat melting &alignment is carried out without melting bumps and thereafter the bonding tool is moved down; and after contact is detected, the bonding tool is heated to carry out bonding.
  • the flux 9 is transferred to the solder bumps 5 b on the chip side during flip chip bonding; the solder bumps 5 b on the chip side and the solder bumps 5 a on the substrate side are aligned with each other; then the bonding tool is moved down; and after contact is detected, the bonding tool is heated to carry out bonding.
  • FIG. 15 is a manufacturing flowchart illustrating the third modification to the assembly of the semiconductor device in the first embodiment of the invention.
  • the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side by two-stage action during flip chip bonding.
  • the semiconductor chip 4 supported by the bonding head 18 is placed so that the following is implemented by a chip placement of Step S 101 illustrated in FIG. 15 : the solder bumps 5 a on the substrate side and the solder bumps 5 b on the chip side are opposed to each other over the wiring board 2 . Thereafter, the solder bumps 5 b on the chip side are brought into contact with the solder bumps 5 a on the substrate side. After this contact, the semiconductor chip 4 is pressed into the wiring board 2 by the pressing amount Y 1 as shown by a first pressing in Step S 102 . Further, first scrubbing operation (periodical rhythmical vibration) is carried out with the amplitude X 1 as shown by a first scrubbing of Step S 103 .
  • first scrubbing operation peripheral rhythmical vibration
  • the semiconductor chip 4 is pressed with the pressing amount Y 2 by a second pressing of Step S 104 and second scrubbing operation is carried out with the amplitude X 2 as shown in the illustration of a second pressing of Step S 105 .
  • the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side by two-stage action. At this time, it is desirable to make the pressing amount Y 1 in first pressing smaller than the pressing amount Y 2 in second pressing. That is, Y 1 ⁇ Y 2 .
  • solder bumps 5 a , 5 b higher in profile and those lower in profile. To cope with this, the higher solder bumps 5 a , 5 b are pressed first with a smaller pressing amount and scrubbed to bond them together; thereafter, the lower solder bumps 5 a , 5 b are pressed and scrubbed to bond them together.
  • solder protrusion may be locally produced in a place where the surface oxide film of molten solder bumps is prone to be broken during bonding. Even in this case, the solder protrusion amount (length) can be suppressed because the pressing amount Y 1 in the first pressing is smaller than the pressing amount Y 2 in the second pressing (Y 1 ⁇ Y 2 ).
  • a bridge between adjacent bumps is prone to be produced when the bumps are large in volume (high bumps) and the protrusion amount is large.
  • these bumps are scrubbed in the position of the first pressing with the amplitude X 1 so that the local broken areas in the surface oxide film are spread all around the bumps.
  • solder protrusion directions 5 d as shown in FIG. 32 are made to extend (concentrically) all around the bumps. This makes it possible to suppress the production of local solder protrusions and prevent the production of a solder bridge between adjacent bumps.
  • FIG. 16 is a partial sectional view illustrating the fourth modification to the assembly of the semiconductor device in the first embodiment of the invention.
  • solder bumps 5 b are formed only on the chip side in bump bonding. That is, the drawing illustrates solder bump bonding carried out when solder bumps 5 b are provided only in the semiconductor chip 4 and bumps are not provided on the substrate side. Even in this bump bonding, the same effect as in the assembly of the semiconductor device (BGA 1 ) illustrated in FIG. 2 to FIG. 4 and the first modification to the third modification is obtained as long as the following measure is taken in flip chip bonding: after molten solder bumps are brought into contact, they are pressed to break the surface oxide film of the solder bumps 5 b .
  • FIG. 17 is an enlarged partial sectional view illustrating the structure of a flip chip bonded portion in a semiconductor device in a comparative example related to the second embodiment of the invention
  • FIG. 18 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board with the structure illustrated in FIG. 17
  • FIG. 19 is a plan view illustrating the solder bridge structure cut along line A of FIG. 17 as viewed from above.
  • FIG. 20 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board in a semiconductor device in the second embodiment of the invention.
  • FIG. 21 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over the openings in the solder resist film illustrated in FIG. 20 ; and FIG. 22 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board in a semiconductor device in a first modification to the second embodiment of the invention.
  • FIG. 23 is a plan view illustrating the structure of solder bumps placed over the openings in the solder resist film illustrated in FIG. 22 ;
  • FIG. 24 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over the openings in the solder resist film illustrated in FIG. 22 ;
  • FIG. 25 is a plan view illustrating the directions of solder protrusions obtained when solder bumps are placed over openings in the solder resist film of the wiring board in a semiconductor device in a second modification to the second embodiment of the invention
  • FIG. 26 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over openings in the solder resist film of the wiring board in a semiconductor device in a third modification to the second embodiment of the invention.
  • the second embodiment is so configured that the production of local solder protrusions is suppressed during flip chip bonding in a semiconductor device (for example, the BGA 1 illustrated in FIG. 1 ) assembled by carrying out flip chip bonding.
  • the production of local solder protrusions is suppressed by the structure of a wiring board 2 flip chip bonded with a semiconductor chip.
  • solder bumps the following takes place when the oxide film over the surfaces of bumps are thin and uniform: such solder protrusions 5 c as illustrated in FIG. 19 tend to enlarge as the distance between the substrate surface and the chip surface is narrowed.
  • FIG. 17 and FIG. 19 illustrating solder bumps 5 show a case where multiple bumps are formed over each of common large metal lands (electrodes 2 c for flip chip bonding) like a power supply and ground.
  • the drawings show the boundary between metal lands (electrodes 2 c for flip chip bonding) different in kind, for example, ground and a power supply.
  • solder protrusion directions 5 d tend to extend to the direction thereof (toward the recessed portion 2 h ): Therefore, such a land shape that a solder protrusion 5 c is extended to the direction of the shortest pitch (the nearest area) reduces the pressing amount at which a bridge between adjacent bumps and narrows the settable range of pressing amount to reduce the junction margin. As a result, a solder bridge results.
  • a solder bridge is prone to be caused when the following shortest parts 2 g are placed in positions where they are opposed to each other between adjacent solder bumps 5 between the bumps in flip chip bonding as illustrated in FIG. 18 : the shortest parts 2 g where the distance between the following patterns is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding as a metal land as viewed in a plane; and the opening pattern (bump placement portion pattern) 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
  • the following shortest parts 2 g are placed in positions where they are not opposed to each other between adjacent bumps between the bumps in flip chip bonding: the shortest parts 2 g where the distance between the following patterns is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding in the wiring board 2 as viewed in a plane; and the opening pattern (bump placement portion pattern) 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
  • the shortest part 2 g refers to a part where the distance L between the outer shape pattern 2 f and the opening pattern 2 d is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding as viewed in a place and the opening pattern 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
  • the shortest parts are placed in positions where the directions 5 d of their respective solder protrusions from adjacent solder bumps are not identical.
  • the shortest parts 2 g are arranged so that the solder protrusion directions 5 d are not opposed to each other by shifting the following positions from each other: the position of each midpoint between shortest-pitch (nearest) bumps (opening patterns 2 d ) and the position of each midpoint between lands (outer shape patterns 2 f ).
  • the individual shortest parts 2 g are so placed that their identical solder protrusion directions 5 d agree with the diagonal directions (oblique direction) of solder bumps 5 .
  • a space between bumps can be additionally provided and this structure is preferable.
  • FIG. 25 and FIG. 26 illustrate examples of isolated lands like signal bumps.
  • the shortest parts 2 g in electrodes 2 c for flip chip bonding as isolated lands are arranged in such positions that their respective solder protrusion directions 5 d differ from one another between the bumps.
  • the shortest parts 2 g in electrodes 2 c for flip chip bonding as isolated lands are arranged in positions where their respective solder protrusion directions 5 d are identical between the bumps.
  • the structure in FIG. 26 makes it possible to provide solder with a tendency to protrude in the longest-pitch direction.
  • the following shortest parts 2 g are placed in positions where they are not opposed to each other between bumps: the shortest parts where the distance between the following patterns is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding in the wiring board 2 as viewed in a place and the opening pattern 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
  • a means for reducing the production of a solder bridge by lands (electrodes 2 c for flip chip bonding) on the substrate side has been taken as an example. Instead, the means in the second embodiment can also be applied to lands (electrode pads 4 c ) on the chip side.
  • flux 9 is applied to solder bumps 5 a on the substrate side and then the reflow/cleaning (flux cleaning) is carried out before flip chip bonding is carried out has been described in relation to the first embodiment.
  • This technology may be applied to solder bumps 5 b on the chip side and even in this case, the same effects as in cases where it is applied to solder bumps 5 a on the substrate side can be obtained.
  • the following technologies may be combined or may be singly adopted: the technology for the assembly of a semiconductor device described in relation to the first embodiment and illustrated in FIG. 2 to FIG. 4 ; the technologies in the first modification to the fourth modification thereto; the technology related to the structure of a semiconductor device described in relation to the second embodiment; and the technologies in the first modification to the third modification to the second embodiment.
  • the invention is favorably applicable to the assembly of an electronic device using flip chip bonding.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
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