US20120098126A1 - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method therefor Download PDFInfo
- Publication number
- US20120098126A1 US20120098126A1 US13/274,296 US201113274296A US2012098126A1 US 20120098126 A1 US20120098126 A1 US 20120098126A1 US 201113274296 A US201113274296 A US 201113274296A US 2012098126 A1 US2012098126 A1 US 2012098126A1
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- Prior art keywords
- flip chip
- solder
- chip bonding
- pressing
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Definitions
- the present invention relates to a semiconductor device and processing technologies therefor and in particular to a technology effectively applicable to flip chip bonding using solder bumps.
- Patent Document 1 A technique for taking the following measure in a manufacturing process for semiconductor devices (semiconductor packages) is described in, for example, Japanese Unexamined Patent Publication No. 2007-227555 (Patent Document 1): a semiconductor device with molding resin exposed on the ball surface side is flip chip joined to a wiring board and underfill resin is filled between them.
- flip chip bonded semiconductor devices are known.
- the following are electrically coupled together by flip chip bonding: multiple solder bumps formed over a semiconductor chip (hereafter, also simply referred to as chip) and solder bumps formed over the main surface of a substrate in positions corresponding to them.
- chip semiconductor chip
- solder bumps formed over the main surface of a substrate in positions corresponding to them solder bumps formed over the main surface of a substrate in positions corresponding to them.
- the following advantages are obtained: the footprint of a semiconductor chip can be reduced as compared with wire bonded semiconductor devices; the number of surface electrodes of a semiconductor chip can be increased; and the signal speed between a semiconductor chip and a substrate can be enhanced.
- the number of pins of each semiconductor device has tended to be increased.
- the bump pitch over each semiconductor chip has also tended to be narrowed. Consequently, the gap between bumps is also narrow; therefore, the following can take place when flip chip bonding is carried out using flux: when flux is cleaned off, cleaning fluid cannot get into between a chip and a substrate; and cleaning fluid is less prone to be discharged from between a chip and a substrate and this leads to the production of a residue, and as a result, the flux cannot be completely cleaned off.
- FIG. 27 to FIG. 30 illustrate the procedure for fluxless flip chip bonding in a comparative example examined by the present inventors; and the drawings from FIG. 31 to FIG. 33 illustrate how a solder bridge results in solder bump bonding in the comparative example.
- a wiring board 2 is positioned and placed in position over the upper surface of a bonding stage 19 heated to a temperature close to a solder melting point.
- the bonding stage 19 is provided with an exhaust system 19 a and is exhausted to vacuum through this exhaust system 19 a and is caused to suck and hold the wiring board 2 .
- the bonding head 18 is provided with an exhaust system 18 a and is exhausted to vacuum through this exhaust system 18 a and is caused to suck and hold the semiconductor chip 4 .
- the semiconductor chip 4 is positioned (aligned) to a predetermined position by the movement of the bonding head 18 in the horizontal direction and in this state, it is positioned above the wiring board 2 . Since the bonding head 18 is heated to the predetermined preheat temperature higher than the solder melting point, in this state, the solder bumps 5 ( 5 b ) formed over the semiconductor chip 4 are melted.
- the bonding head 18 is moved down to place the semiconductor chip 4 in position over the wiring board 2 . Since the semiconductor chip 4 is sucked to the lower surface of the bonding head 18 , it is moved down in the vertical direction as is positioned in the horizontal direction. The semiconductor chip 4 is held over the wiring board 2 for a predetermined time with a predetermined gap maintained between them and is thereby flip chip mounted over the wiring board 2 .
- solder bumps 5 ( 5 b ) formed over the semiconductor chip 4 and the solder bumps 5 ( 5 a ) formed over the wiring board 2 are brought into contact with each other.
- the solder bumps 5 ( 5 a ) on the substrate side are heated from the solder bumps 5 ( 5 b ) on the chip side and their temperature rises to the solder melting point or higher.
- the melted and integrated solder bumps 5 are periodically rhythmically vibrated (scrubbed) either in the horizontal direction X or in the vertical direction Y.
- the oxide film covering the surfaces of the solder bumps 5 is broken and taken into the solder bumps 5 and thus bonding can be carried out without use of flux.
- the suction of the semiconductor chip 4 to the bonding head 18 is canceled and the bonding head 18 is moved up to terminate the flip chip bonding.
- solder bumps 5 a are prevented from being deformed outward by pressing and become local solder protrusions 5 c and are protruded in the solder protrusion direction 5 d .
- a solder bridge becomes prone to be formed between adjacent bumps as illustrated in FIG. 33 .
- solder bumps 5 a on the substrate side are nonuniformly formed.
- a solder protrusion 5 c may be formed depending on how the above-mentioned oxide film is ripped. That is, the present inventors found that in fluxless flip chip bonding, a solder bridge results (problem).
- Patent Document 1 Japanese Unexamined Patent Publication No. 2007-227555 discloses a fluxless flip chip bonding technique in which the following procedure is taken: the solder balls of a bare chip and the solder balls of a wiring board are brought into contact with each other; they are heated to a temperature higher than the melting point of solder; and ultrasonic vibration is applied to the bare chip to remove the oxide film over the ball surfaces.
- the invention has been made with the above problem taken into account and it is an object of the invention to provide a technology that enables the enhancement of joint reliability in flip chip bonding of a semiconductor device.
- a semiconductor device includes: a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; a semiconductor chip placed over the upper surface of the wiring board by flip chip bonding; and multiple external terminals provided in the lower surface of the wiring board.
- the shortest parts where the distance between the following patterns is shortest are placed in positions where they are not opposed to each other between the bumps: the outer shape pattern of each the electrode for flip chip bonding as viewed in a plane and the bump placement portion pattern for the electrode for flip chip bonding as viewed in a plane.
- a manufacturing method for a semiconductor device includes the steps of: (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; (c) forming a solder ball over each of the electrodes for flip chip bonding of the wiring board; (d) after the step (c), applying flux to the multiple solder balls and then subjecting the solder balls to reflow/cleaning; and (e) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other.
- Another manufacturing method for a semiconductor device includes the steps of; (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; (c) applying flux paste to each of the electrodes for flip chip bonding of the wiring board; (d) placing a solder ball on the flux paste over each of the electrodes for flip chip bonding; (e) after the step (d), subjecting the multiple solder balls to reflow/cleaning; and (f) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other.
- the semiconductor chip is presssed into the wiring board by two-staged pressing, first pressing and second pressing subsequent to the first pressing, to implement the flip chip bonding.
- FIG. 1 is a sectional view illustrating an example of the structure of a semiconductor device in a first embodiment of the invention and an enlarged partial sectional view of a flip chip bonded portion;
- FIG. 2 is a manufacturing flowchart illustrating an example of the structure on the substrate side in the assembly of the semiconductor device illustrated in FIG. 1 ;
- FIG. 3 is a manufacturing flowchart illustrating an example of flip chip bonding in the assembly of the semiconductor device illustrated in FIG. 1 ;
- FIG. 4 is a manufacturing flowchart illustrating an example of an underfill application and a ball mounting in the assembly of the semiconductor device illustrated in FIG. 1 ;
- FIG. 5 is a flowchart illustrating a first modification to the assembly of a semiconductor device in the first embodiment of the invention
- FIG. 6 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5 ;
- FIG. 7 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5 ;
- FIG. 8 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5 ;
- FIG. 9 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5 ;
- FIG. 10 is a flowchart illustrating a second modification to the assembly of a semiconductor device in the first embodiment of the invention.
- FIG. 11 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10 ;
- FIG. 12 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10 ;
- FIG. 13 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10 ;
- FIG. 14 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10 ;
- FIG. 15 is a manufacturing flowchart illustrating a third modification to the assembly of a semiconductor device in the first embodiment of the invention.
- FIG. 16 is a partial sectional view illustrating a fourth modification to the assembly of a semiconductor device in the first embodiment of the invention.
- FIG. 17 is an enlarged partial sectional view illustrating the structure of a flip chip bonded portion in a semiconductor device in a comparative example related to a second embodiment of the invention.
- FIG. 18 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of a wiring board with the structure illustrated in FIG. 17 ;
- FIG. 19 is a plan view illustrating the solder bridge structure taken along line A of FIG. 17 as viewed from above;
- FIG. 20 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of the wiring board in a semiconductor device in the second embodiment of the invention.
- FIG. 21 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in the solder resist film illustrated in FIG. 20 ;
- FIG. 22 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of the wiring board in a semiconductor device in a first modification to the second embodiment of the invention
- FIG. 23 is a plan view illustrating the structure of solder bumps placed over openings in the solder resist film illustrated in FIG. 22 ;
- FIG. 24 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in the solder resist film illustrated in FIG. 22 ;
- FIG. 25 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in a solder resist film of the wiring board in a semiconductor device in a second modification to the second embodiment of the invention
- FIG. 26 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in a solder resist film of the wiring board in a semiconductor device in a third modification to the second embodiment of the invention
- FIG. 27 is a partial sectional view illustrating a procedure for fluxless flip chip bonding in a comparative example
- FIG. 28 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example
- FIG. 29 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example.
- FIG. 30 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example
- FIG. 31 is an enlarged partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example
- FIG. 32 is an enlarged partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example.
- FIG. 33 is an enlarged partial sectional view illustrating the structure of a solder bridge formed during the fluxless flip chip bonding in the comparative example.
- FIG. 1 is a sectional view illustrating an example of the structure of a semiconductor device in the first embodiment of the invention and an enlarged partial sectional view of a flip chip bonded portion;
- FIG. 2 is a manufacturing flowchart illustrating an example of the manufacture on the substrate side in the assembly of the semiconductor device illustrated in FIG. 1 ;
- FIG. 3 is a manufacturing flowchart illustrating an example of flip chip bonding in the assembly of the semiconductor device illustrated in FIG. 1 ;
- FIG. 4 is a manufacturing flowchart illustrating an example of an underfill application and ball mounting in the assembly of the semiconductor device illustrated in FIG. 1 .
- the semiconductor device in the first embodiment is a semiconductor package obtained by placing a semiconductor chip 4 over a substrate by flip chip bonding.
- BGA All Grid Array
- the BGA 1 includes: a wiring board 2 that is a substrate having an upper surface 2 a and a lower surface 2 b located on the opposite side thereto; the semiconductor chip 4 placed over the upper surface 2 a of the wiring board 2 through multiple solder bumps (bump electrodes, solder balls) 5 and having a semiconductor integrated circuit formed therein; underfill 3 filled around each of the solder bumps 5 and around the side surface of the semiconductor chip 4 ; and multiple solder balls 7 as external terminals provided over the lower surface 2 b of the wiring board 2 .
- the solder balls 7 are arranged, for example, in a lattice pattern in the lower surface 2 b of the wiring board 2 .
- electrical signals sent from the semiconductor chip 4 are transmitted to solder balls 7 over the lower surface 2 b of the wiring board 2 through solder bumps 5 or wiring, through hole wiring, or the like, not shown, in the wiring board 2 .
- the semiconductor chip 4 has: a main surface 4 a in which multiple electrode pads 4 c as surface electrodes are respectively formed in openings in a protective film 4 d ; and a back surface 4 b located on the opposite side to the main surface 4 a .
- the semiconductor chip 4 is electrically coupled with the wiring board 2 by flip chip bonding. As illustrated in the enlarged partial sectional view in FIG. 1 , that is, the semiconductor chip 4 is electrically coupled with the electrodes 2 c for flip chip bonding of the wiring board 2 through the solder bumps 5 respectively electrically coupled to the electrode pads 4 c . Since the semiconductor chip 4 is placed over the wiring board 2 by flip chip bonding, it is face-down mounted over the wiring board 2 .
- the upper surface 2 a of the wiring board 2 and the main surface 4 a of the semiconductor chip 4 are opposed to each other; therefore, the back surface 4 b of the semiconductor chip 4 faces upward.
- Electronic components such as chip components 6 are mounted around the semiconductor chip 4 in the upper surface 2 a of the wiring board 2 .
- the chip components 6 are, for example, a chip capacitor and a chip resistor and are solder mounted over the wiring board 2 through solder 8 .
- the wiring board 2 has an upper surface 2 a and a lower surface 2 b located on the opposite side to the upper surface 2 a .
- multiple electrodes 2 c for flip chip bonding are formed in the upper surface 2 a .
- the wiring board 2 is a substrate that underwent wiring formation, surface insulating layer formation, land surface layer processing, and the like. In the description of the first embodiment, attention will be paid mainly to the state of the surfaces of the bumps for chip bonding.
- solder paste for flip chip bonding is applied. That is, to form the bumps for chip bonding, solder paste 10 is applied to the electrodes 2 c for flip chip bonding illustrated in FIG. 1 .
- the solder paste 10 is, for example, a paste material containing flux and solder at a volume ratio of approximately 50%.
- the solder paste 10 is applied to each electrode 2 c for flip chip bonding from above by a print process using a metal mask.
- Step S 3 a reflow/cleaning of Step S 3 is carried out.
- heat treatment is carried out using a nitrogen reflow furnace with the oxygen concentration controlled to, for example, 100 ppm or below.
- Solder bumps (solder balls) 5 a are thereby formed over the predetermined electrodes 2 c for flip chip bonding. Further, flux cleaning is carried out to remove flux.
- Step S 4 a solder paste application of Step S 4 is carried out.
- the solder paste 10 for peripheral element placement is applied only to areas where a peripheral element is to be placed by a print process using a metal mask.
- Step S 5 peripheral element placement & reflow/cleaning of Step S 5 is carried out.
- electronic components such as chip components 6
- the reflow/cleaning flux cleaning
- Step S 6 a flux application of Step S 6 is carried out.
- flux 9 is applied to the solder bumps 5 a over the electrodes 2 c for flip chip bonding.
- Step S 7 a reflow/cleaning of Step S 7 is carried out. That is, the flux 9 is applied to the solder bumps 5 a for flip chip bonding and then reflow and cleaning processing is carried out.
- the following can be implemented by the flux application and reflow/cleaning (flux cleaning) after the completion of the mounting of the chip components 6 : reflow processing can be carried out without the flux 9 left over the solder bumps 5 a for flip chip bonding. Therefore, the thick and nonuniform surface oxide film over the solder bumps 5 a can be turned into a thin and uniform surface oxide film.
- Each of the solder bumps 5 a for flip chip bonding is 80 ⁇ m in bump diameter and 50 ⁇ m in bump height when the bump pitch is, for example, 150 ⁇ m. Since it is necessary to minimize variation in bump height, it is required to supply solder with accuracy. In addition, the bump placement surface must be flat. Therefore, it is desirable to take the procedure shown in the flow in FIG. 2 . That is, it is desirable that the solder bumps 5 a for flip chip bonding should be formed first and then peripheral elements (electronic components), such as chip components 6 , should be placed.
- solder bumps 5 a obtained by subjecting bumps formed beforehand to reflow processing without carrying out anti-oxidation processing, such as flux application, and thereafter applying flux and carrying out the reflow/cleaning again.
- solder bumps (bump electrodes) 5 b of the semiconductor chip 4 and the solder bumps (solder balls) 5 a of the wiring board 2 are (fluxless) flip chip bonded to each other.
- Step S 11 in FIG. 3 a chip bump heat melting & alignment of Step S 11 in FIG. 3 is carried out.
- the wiring board 2 is positioned in a predetermined position in the supporting surface of a bonding stage 19 heated to a temperature close to a solder melting point and placed there.
- the bonding stage 19 is provided with an exhaust system 19 a and is exhausted to vacuum through this exhaust system 19 a to suck and hold the wiring board 2 .
- the back surface 4 b of the semiconductor chip 4 is sucked and held by the suction surface of a bonding head 18 preheated to a predetermined preheat temperature higher than the solder melting point.
- the bonding head 18 is provided with an exhaust system 18 a and is exhausted to vacuum through this exhaust system 18 a to suck and hold the semiconductor chip 4 .
- the semiconductor chip 4 is positioned (aligned) in a predetermined position by the movement of the bonding head 18 in the horizontal direction and in this state, it is positioned above the wiring board 2 . Since the bonding head 18 is heated to the predetermined preheat temperature higher than the solder melting point, in this state, the solder bumps 5 ( 5 b ) formed over the semiconductor chip 4 are melted.
- Step S 12 a chip/substarate bump contacting & pressing of Step S 12 is carried out.
- the bonding head 18 is moved down to place the semiconductor chip 4 over the wiring board 2 in a predetermined position. That is, the semiconductor chip 4 is placed so that the solder bumps 5 a on the substrate side and the solder bumps 5 b on the chip side are aligned with each other. Since the semiconductor chip 4 is sucked to the suction surface of the bonding head 18 , it is moved down in the vertical direction as is positioned in the horizontal direction. The semiconductor chip 4 is held for a predetermined time with a predetermined distance maintained between the wiring board 2 and the semiconductor chip 4 and is thereby flip chip placed over the wiring board 2 .
- solder bumps 5 b formed over the semiconductor chip 4 and the solder bumps 5 a formed over the wiring board 2 are brought into contact with each other. Further, the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side. The solder bumps 5 a on the substrate side are heated by the solder bumps 5 b on the chip side and their temperature becomes equal to or higher than the solder melting point.
- the integrated and melted solder bumps 5 are periodically rhythmically vibrated (scrubbed) either in the horizontal direction X or in the vertical direction Y.
- Step S 14 As shown in the illustration of, a chip releasing of Step S 14 , the suction of the semiconductor chip 4 to the bonding head 18 is canceled and the bonding head 18 is moved up to complete flip chip bonding.
- Step S 15 in FIG. 4 an underfill application of Step S 15 in FIG. 4 is carried out.
- underfill 3 is dripped to the side of the semiconductor chip 4 to fill the gap between the semiconductor chip 4 and the wiring board 2 with the underfill 3 . That is, the underfill 3 is filled to the flip chip bonded portions and it is also supplied to the side surface of the semiconductor chip 4 to cover the periphery of the semiconductor chip 4 with the underfill 3 .
- the flip chip bonded portions and the semiconductor chip 4 are thereby protected.
- Step S 16 an outer ball mounting of Step S 16 is carried out.
- the lower surface 2 b of the wiring board 2 is provided with a predetermined number of solder balls (external terminals) 7 .
- the flux 9 is applied to the solder bumps 5 a for flip chip bonding over the substrate before fluxless flip chip bonding is carried out.
- flip chip bonding is carried out after the reflow/cleaning (flux cleaning) is carried out.
- the flip chip bonding can be achieved with the oxide film over the surfaces of the solder bumps 5 a made relatively thin and uniform.
- the surface oxide film of the solder bumps 5 a can be made uniform by forming the solder bumps 5 a of the solder paste 10 and thereafter applying the flux 9 again and carrying out the reflow/cleaning (flux cleaning) again.
- the surface oxide film of the solder bumps 5 a on the substrate side is made uniform before fluxless flip chip bonding is carried out.
- the shape of solder protrusions outward of solder when the solder bumps 5 a are pressed is spread (concentrically) all around the bumps (balls) by the surface tension of molten solder.
- the solder protrusions take on such a shape that their tips are rounded.
- solder protrusions produced at the time of solder pressing can be provided with an entire circumferential shape (concentric shape) or a rounded shape.
- the gap between chip and substrate where a bridge between adjacent bumps is produced is reduced and it is possible to increase the amount of solder pressing.
- the oxide film over the surfaces of the solder bumps is relatively thin and uniform, the oxide film over the surfaces of the solder bumps is easy to break and it is possible to reduce the amount of solder pressing required for bonding. As a result, it is possible to ensure a large area for pressing solder so that bonding can be achieved.
- the BGA 1 is a semiconductor device having a structure in which chip components 6 are solder mounted around the semiconductor chip 4 . That is, after the solder bumps 5 a for flip chip bonding are formed by the reflow/cleaning, the solder 8 for the chip components 6 are subjected to the reflow/cleaning. At this stage, the solder bumps 5 a are heated and melted without flux and their surface oxide film is increased in thickness. Therefore, the surface oxide film of the solder bumps 5 a is not uniform.
- the flux 9 is applied to the solder bumps 5 a and the reflow/cleaning (flux cleaning) is carried out again before flip chip bonding is carried out Therefore, the surface oxide film of the solder bumps 5 a can be made relatively thin and uniform by the oxide film removing effect of flux before flip chip bonding. That is, the following can be implemented even in the BGA 1 having such a structure that electronic components, such as chip components 6 , are solder mounted around the semiconductor chip 4 : the production of solder bridges can be reduced to enhance the joint reliability in flip chip bonding.
- the melted solder bumps 5 b on the chip side are brought into contact with and pressed into the solder bumps 5 a on the substrate side during flip chip bonding.
- the bumps at least on either side are melted during flip chip bonding, as mentioned above, protruded bumps are prone to be formed at the time of bump pressing.
- the flip chip bonding of the BGA 1 in the first embodiment is carried out after the following procedure is taken: the solder bumps 5 a on the substrate side are subjected to the flux application and the reflow/cleaning again to make uniform the surface oxide film of the solder bumps 5 a . Therefore, the following can be implemented even when the bumps on either side are melted: the solder protrusions can be spread (concentrically) all around the bumps by the surface tension of the molten Solder and the production of solder bridges can be reduced.
- FIG. 5 is a flowchart illustrating the first modification to the assembly of the semiconductor device in the first embodiment of the invention
- FIG. 6 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5
- FIG. 7 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 5
- FIG. 8 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5
- FIG. 9 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 5 .
- the first modification is an example of assembly in which the following procedure is taken: the solder bumps 5 b on the chip side are formed by a printing method and the flux application and the reflow/cleaning are carried out only on the solder bumps 5 a on the substrate side.
- Step S 21 in FIG. 5 A preparation of land-formed wafer of Step S 21 in FIG. 5 is carried out.
- a wafer (semiconductor wafer) 12 including multiple electrode pads 4 c as aluminum electrodes and a protective film 12 a for protecting the surface thereof is prepared by wafer preparation of Step S 41 in FIG. 6 .
- Step S 42 a formation of bump underlaying metal film of Step S 42 is carried out.
- a bump underlaying metal film 12 b is formed over the electrode pads 4 c and protective film 12 a over the surface of the wafer 12 .
- Ti, NiV, Cu, or the like is used for the bump underlaying metal film.
- Step S 43 an etching resist film formation of Step S 43 is carried out.
- an etching resist film 12 c is formed in multiple bump placement portions for flip chip bonding.
- Step S 44 underlaying film etching & resist film removal of Step S 44 is carried out.
- etching is carried out to remove the unnecessary portions of the bump underlaying metal film 12 b and then the etching resist film 12 c is removed. This establishes a state in which the bump underlaying metal film 12 b is formed over each electrode pad 4 c in the wafer 12 .
- solder paste application of Step S 22 in FIG. 5 is carried out.
- solder paste 10 is formed over the bump underlaying metal films 12 b in the bump placement portions by a print process using a printing mask 14 as a metal mask by solder paste printing of Step S 45 in FIG. 7 .
- the printing mask 14 is placed around the bump underlaying metal films 12 b as the bump placement portions and then solder paste 10 is printed over the bump underlaying metal films 12 b by a print process using a squeegee 13 .
- Step S 46 in FIG. 7 a printing mask removal of Step S 46 in FIG. 7 is carried out. At this step, the printing mask 14 over the wafer 12 is removed.
- Step S 23 in FIG. 5 and Step S 47 in FIG. 7 are carried out.
- the solder paste 10 over the wafer 12 is heated and melted at a predetermined temperature by ref lowing and cleaned (flux cleaning) to form multiple solder bumps 5 b.
- Step S 24 in FIG. 5 a chip segmentation of Step S 48 in FIG. 7
- the wafer is diced into a chip size to form semiconductor chips 4 each having multiple solder bumps 5 b placed therein.
- wafer back surface polishing is carried out to a predetermined wafer thickness after or before the formation of the solder bumps 5 b .
- a desired chip thickness can be obtained.
- Step S 31 in FIG. 5 A preparation of land-formed substrate of Step S 31 in FIG. 5 is carried out.
- the following matrix arrayed substrate 11 having a plurality of device forming areas is prepared by a substrate preparation of Step S 51 in FIG. 8 : a matrix arrayed substrate 11 having a plurality of device forming areas as a multilayer wiring board including multiple electrodes 2 c for flip chip bonding as copper lands, a solder resist film 11 a for protecting the surface thereof, and multiple land terminals 11 b formed on the back surface side.
- solder paste 10 is formed over the multiple electrodes 2 c for flip chip bonding by a print process using a printing mask 14 as a metal mask by a solder paste printing of Step S 52 in FIG. 8 .
- the solder paste 10 is, for example, a paste material containing flux and solder at a volume ratio of approximately 50%.
- the printing mask 14 is placed around the electrodes 2 c for flip chip bonding and then the solder paste 10 is printed over the electrodes 2 c for flip chip bonding by a print process using a squeegee 13 .
- Step S 53 in FIG. 8 a printing mask removal of Step S 53 in FIG. 8 is carried out.
- the printing mask 14 over the matrix arrayed substrate 11 having a plurality of device forming areas is removed.
- Step S 33 in FIG. 5 and Step S 54 in FIG. 8 are carried out.
- the solder paste 10 over the electrodes 2 c for flip chip bonding of the matrix arrayed substrate 11 having a plurality of device forming areas is heated and melted at a predetermined temperature by ref lowing and cleaned to form multiple solder bumps 5 a.
- Step S 55 in FIG. 9 a probing of Step S 55 in FIG. 9 is carried out.
- a probe 15 is brought into contact with the multiple solder bumps 5 a over the matrix arrayed substrate 11 having a plurality of device forming areas to conduct electrical testing.
- Step S 34 in FIG. 5 Step S 56 in FIG. 9
- flux 9 is applied (re-applied) so as to cover the multiple solder bumps 5 a provided over the matrix arrayed substrate 11 having a plurality of device forming areas.
- Step S 35 in FIG. 5 flux cleaning of Step S 57 in FIG. 9
- the solder bumps 5 a over the matrix arrayed substrate 11 having a plurality of device forming areas with the flux 9 applied thereto are heated and cleaned (flux cleaning) at a predetermined temperature by reflowing. This makes it possible to eliminate variation in bump height due to a probing mark, thin the surface oxide film sticking to each of the solder bumps 5 a , and make the surface oxide film uniform.
- Step S 58 in FIG. 9 a substrate segmentation of Step S 58 in FIG. 9 is carried out to form wiring boards 2 each having multiple solder bumps 5 a for flip chip bonding placed therein.
- Step S 36 in FIG. 5 a flip chip bonding of Step S 36 in FIG. 5 is carried out.
- flip chip bonding is carried out using the following semiconductor chip and wiring board: a semiconductor chip 4 with multiple solder bumps 5 b placed therein shown in the illustration of Step S 48 in FIG. 7 and a wiring board 2 with multiple solder bumps 5 a placed therein shown in the illustration of Step S 58 in FIG. 9 .
- Step S 11 to Step S 14 in FIG. 3 the same (fluxless) flip chip bonding method as illustrated as Step S 11 to Step S 14 in FIG. 3 is used to flip chip bond the following semiconductor chip and wiring board to each other: the semiconductor chip 4 shown in the illustration of Step S 48 in FIG. 7 and the wiring board 2 shown in the illustration of Step S 58 in FIG. 9 . This completes the assembly.
- FIG. 10 is a flowchart illustrating the second modification to the assembly of the semiconductor device in the first embodiment of the invention
- FIG. 11 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10
- FIG. 12 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated in FIG. 10
- FIG. 13 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10
- FIG. 14 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated in FIG. 10 .
- the solder bumps 5 b on the chip side are formed by plating and the solder bumps 5 a on the substrate side are formed by a micro solder ball placement method. It is an example of assembly in which the flux application and the reflow/cleaning are carried out on the solder bumps 5 a on the substrate side.
- Step S 61 in FIG. 10 A preparation of pad opening-formed wafer of Step S 61 in FIG. 10 is carried out.
- the following wafer (semiconductor wafer) 12 is prepared by a wafer preparation of Step S 81 in FIG. 11 : a wafer in which multiple electrode pads 4 c as bump placement portions and aluminum electrodes and a protective film 12 a exposing the electrode pads 4 c by openings therein are formed.
- Step S 82 a formation of bump underlaying metal film of Step S 82 is carried out.
- a bump underlaying metal film 12 b (UBM) is formed over the entire surface of the wafer 12 by sputtering using the UBM (Under Bump Metal) sputtering of Step S 62 in FIG. 10 . That is, the bump underlaying metal film 12 b is formed over the electrode pads 4 c and protective film 12 a over the surface of the wafer 12 by sputtering.
- UBM Under Bump Metal
- Step S 83 a resist film formation of Step S 83 is carried out.
- plating resist film formation and patterning of Step S 63 in FIG. 10 is carried out. That is, a plating resist film 12 d is applied to the wafer 12 by a spin coat method and openings are formed in positions corresponding to bump placement portions by a photoengraving process.
- Step S 84 a plating film formation of Step S 84 is carried out.
- formation of Ni plating film and solder plating film of Step S 64 in FIG. 10 is carried out. That is, a Ni plating film, not shown, is formed as a solder diffusion barrier over the bump underlaying metal film 12 b and then a solder plating film 12 e is formed as shown in the illustration of Step S 84 in FIG. 11 .
- Step S 85 a resist film removal of Step S 85 is carried out. That is, the portions of the plating resist film 12 d around the solder plating films 12 e are removed.
- Step S 86 in FIG. 12 Step S 65 in FIG. 10
- flux 9 is applied to the multiple solder plating films 12 e over the wafer 12 by a spin coat method.
- Step S 87 a flux cleaning of Step S 87 (reflow/cleaning of Step S 66 in FIG. 10 ) is carried out.
- the solder plating films 12 e over the wafer 12 are heated and melted at a predetermined temperature by ref lowing and cleaned to form multiple solder bumps 5 b.
- Step S 88 an underlaying film etching of Step S 88 is carried out.
- the exposed bump underlaying metal films 12 b other than those located under the solder bumps 5 b are etched using the solder bumps 5 b as a mask and removed by UBM etching of Step S 67 in FIG. 10 .
- Wafer back surface polishing is carried out as required to control the thickness of the wafer 12 to a desired value.
- Step S 68 in FIG. 10 chip segmentation of Step S 89 in FIG. 12
- the wafer is diced into a chip size to form semiconductor chips 4 each having multiple solder bumps 5 b placed therein.
- Step S 71 in FIG. 10 A preparation of land-formed substrate of Step S 71 in FIG. 10 is carried out.
- the following matrix arrayed substrate 11 having a plurality of device forming areas is prepared by a substrate preparation of Step S 91 in FIG. 13 : a matrix arrayed substrate 11 having a plurality of device forming areas as a multilayer wiring board including multiple electrodes 2 c for flip chip bonding as copper lands and a solder resist film 11 a for protecting the surface thereof.
- the copper lands may be coated with a Ni/Au plating, a Ni/Pd/Au plating, a Sn plating, or the like.
- Step S 72 in FIG. 10 a flux paste application of Step S 72 in FIG. 10 is carried out.
- paste-like flux 9 (flux paste) is applied to the multiple electrodes 2 c for flip chip bonding by a print process using a printing mask 14 as a metal mask by a flux printing of Step S 92 in FIG. 13 .
- the paste-like flux 9 is 100% flux.
- Step S 73 in FIG. 10 a micro ball placement of Step S 73 in FIG. 10 is carried out.
- the printing mask 14 is removed and then a ball placement mask 16 is placed in position over the matrix arrayed substrate 11 having a plurality of device forming areas by a solder ball placement of Step S 93 in FIG. 14 .
- the ball placement mask 16 openings are formed in correspondence with the positions of the electrodes 2 c for flip chip bonding as bump placement portions.
- small solder balls 17 as micro balls are shaken into the openings in the ball placement mask 16 . This establishes a state in which a small solder ball 17 is placed over the paste-like flux 9 (flux paste) over each of the electrodes 2 c for flip chip bonding.
- Step S 74 in FIG. 10 and Step S 94 in FIG. 14 are carried out.
- the small solder balls 17 placed over the paste-like flux 9 over the electrodes 2 c for flip chip bonding of the matrix arrayed substrate 11 having a plurality of device forming areas are heated and melted at a predetermined temperature by ref lowing and cleaned (flux cleaning) to form multiple solder bumps 5 a.
- Step S 95 in FIG. 14 a substrate segmentation of Step S 95 in FIG. 14 is carried out to form wiring boards 2 each having multiple solder bumps 5 a for flip chip bonding placed therein.
- Step S 75 in FIG. 10 flip chip bonding is carried out.
- flip chip bonding is carried out using the following semiconductor chip and wiring board: a semiconductor chip 4 with multiple solder bumps 5 b placed therein shown in the illustration of Step S 89 in FIG. 12 and a wiring board 2 with multiple solder bumps 5 a placed therein shown in the illustration of Step S 95 in FIG. 14 .
- Step S 11 to Step S 14 in FIG. 3 the same (fluxless) flip chip bonding method as illustrated as Step S 11 to Step S 14 in FIG. 3 is used to flip chip bond the following semiconductor chip and wiring board to each other: the semiconductor chip 4 shown in the illustration of Step S 89 in FIG. 12 and the wiring board 2 shown in the illustration of Step S 95 in FIG. 14 . This completes the assembly.
- the flux 9 is supplied to the solder bumps 5 a on the substrate side before the semiconductor chip 4 and the wiring board 2 are flip chip bonded to each other. Further, reflow/cleaning (flux cleaning) is carried out before flip chip bonding is carried out. This makes it possible to thin the surface oxide film of the solder bumps 5 a and carry out flip chip bonding with the surface oxide films uniformly formed.
- the other effects obtained by the first modification and the second modification are the same as the other effects obtained by the assembly of the semiconductor device (BGA 1 ) illustrated in FIG. 2 to FIG. 4 ; therefore, the repetitive description thereof will be omitted.
- the measure described below is taken.
- the above effects are obtained by the flip chip bonding procedure in which: the solder bumps 5 b on the chip side and the solder bumps 5 a on the substrate side are brought into contact with each other; and then they are further presses into each other to join the bumps together. Therefore, the steps up to melting and joining of bumps are carried out in a flip chip bonder.
- bumps are pressed into each other by expansion of a bonding tool, a substrate, and the like and the same effects can be obtained even in cases where the procedures described below are taken.
- alignment in, for example, the flow illustrated in FIG.
- a chip bump heat melting &alignment is carried out without melting bumps and thereafter the bonding tool is moved down; and after contact is detected, the bonding tool is heated to carry out bonding.
- the flux 9 is transferred to the solder bumps 5 b on the chip side during flip chip bonding; the solder bumps 5 b on the chip side and the solder bumps 5 a on the substrate side are aligned with each other; then the bonding tool is moved down; and after contact is detected, the bonding tool is heated to carry out bonding.
- FIG. 15 is a manufacturing flowchart illustrating the third modification to the assembly of the semiconductor device in the first embodiment of the invention.
- the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side by two-stage action during flip chip bonding.
- the semiconductor chip 4 supported by the bonding head 18 is placed so that the following is implemented by a chip placement of Step S 101 illustrated in FIG. 15 : the solder bumps 5 a on the substrate side and the solder bumps 5 b on the chip side are opposed to each other over the wiring board 2 . Thereafter, the solder bumps 5 b on the chip side are brought into contact with the solder bumps 5 a on the substrate side. After this contact, the semiconductor chip 4 is pressed into the wiring board 2 by the pressing amount Y 1 as shown by a first pressing in Step S 102 . Further, first scrubbing operation (periodical rhythmical vibration) is carried out with the amplitude X 1 as shown by a first scrubbing of Step S 103 .
- first scrubbing operation peripheral rhythmical vibration
- the semiconductor chip 4 is pressed with the pressing amount Y 2 by a second pressing of Step S 104 and second scrubbing operation is carried out with the amplitude X 2 as shown in the illustration of a second pressing of Step S 105 .
- the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side by two-stage action. At this time, it is desirable to make the pressing amount Y 1 in first pressing smaller than the pressing amount Y 2 in second pressing. That is, Y 1 ⁇ Y 2 .
- solder bumps 5 a , 5 b higher in profile and those lower in profile. To cope with this, the higher solder bumps 5 a , 5 b are pressed first with a smaller pressing amount and scrubbed to bond them together; thereafter, the lower solder bumps 5 a , 5 b are pressed and scrubbed to bond them together.
- solder protrusion may be locally produced in a place where the surface oxide film of molten solder bumps is prone to be broken during bonding. Even in this case, the solder protrusion amount (length) can be suppressed because the pressing amount Y 1 in the first pressing is smaller than the pressing amount Y 2 in the second pressing (Y 1 ⁇ Y 2 ).
- a bridge between adjacent bumps is prone to be produced when the bumps are large in volume (high bumps) and the protrusion amount is large.
- these bumps are scrubbed in the position of the first pressing with the amplitude X 1 so that the local broken areas in the surface oxide film are spread all around the bumps.
- solder protrusion directions 5 d as shown in FIG. 32 are made to extend (concentrically) all around the bumps. This makes it possible to suppress the production of local solder protrusions and prevent the production of a solder bridge between adjacent bumps.
- FIG. 16 is a partial sectional view illustrating the fourth modification to the assembly of the semiconductor device in the first embodiment of the invention.
- solder bumps 5 b are formed only on the chip side in bump bonding. That is, the drawing illustrates solder bump bonding carried out when solder bumps 5 b are provided only in the semiconductor chip 4 and bumps are not provided on the substrate side. Even in this bump bonding, the same effect as in the assembly of the semiconductor device (BGA 1 ) illustrated in FIG. 2 to FIG. 4 and the first modification to the third modification is obtained as long as the following measure is taken in flip chip bonding: after molten solder bumps are brought into contact, they are pressed to break the surface oxide film of the solder bumps 5 b .
- FIG. 17 is an enlarged partial sectional view illustrating the structure of a flip chip bonded portion in a semiconductor device in a comparative example related to the second embodiment of the invention
- FIG. 18 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board with the structure illustrated in FIG. 17
- FIG. 19 is a plan view illustrating the solder bridge structure cut along line A of FIG. 17 as viewed from above.
- FIG. 20 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board in a semiconductor device in the second embodiment of the invention.
- FIG. 21 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over the openings in the solder resist film illustrated in FIG. 20 ; and FIG. 22 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board in a semiconductor device in a first modification to the second embodiment of the invention.
- FIG. 23 is a plan view illustrating the structure of solder bumps placed over the openings in the solder resist film illustrated in FIG. 22 ;
- FIG. 24 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over the openings in the solder resist film illustrated in FIG. 22 ;
- FIG. 25 is a plan view illustrating the directions of solder protrusions obtained when solder bumps are placed over openings in the solder resist film of the wiring board in a semiconductor device in a second modification to the second embodiment of the invention
- FIG. 26 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over openings in the solder resist film of the wiring board in a semiconductor device in a third modification to the second embodiment of the invention.
- the second embodiment is so configured that the production of local solder protrusions is suppressed during flip chip bonding in a semiconductor device (for example, the BGA 1 illustrated in FIG. 1 ) assembled by carrying out flip chip bonding.
- the production of local solder protrusions is suppressed by the structure of a wiring board 2 flip chip bonded with a semiconductor chip.
- solder bumps the following takes place when the oxide film over the surfaces of bumps are thin and uniform: such solder protrusions 5 c as illustrated in FIG. 19 tend to enlarge as the distance between the substrate surface and the chip surface is narrowed.
- FIG. 17 and FIG. 19 illustrating solder bumps 5 show a case where multiple bumps are formed over each of common large metal lands (electrodes 2 c for flip chip bonding) like a power supply and ground.
- the drawings show the boundary between metal lands (electrodes 2 c for flip chip bonding) different in kind, for example, ground and a power supply.
- solder protrusion directions 5 d tend to extend to the direction thereof (toward the recessed portion 2 h ): Therefore, such a land shape that a solder protrusion 5 c is extended to the direction of the shortest pitch (the nearest area) reduces the pressing amount at which a bridge between adjacent bumps and narrows the settable range of pressing amount to reduce the junction margin. As a result, a solder bridge results.
- a solder bridge is prone to be caused when the following shortest parts 2 g are placed in positions where they are opposed to each other between adjacent solder bumps 5 between the bumps in flip chip bonding as illustrated in FIG. 18 : the shortest parts 2 g where the distance between the following patterns is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding as a metal land as viewed in a plane; and the opening pattern (bump placement portion pattern) 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
- the following shortest parts 2 g are placed in positions where they are not opposed to each other between adjacent bumps between the bumps in flip chip bonding: the shortest parts 2 g where the distance between the following patterns is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding in the wiring board 2 as viewed in a plane; and the opening pattern (bump placement portion pattern) 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
- the shortest part 2 g refers to a part where the distance L between the outer shape pattern 2 f and the opening pattern 2 d is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding as viewed in a place and the opening pattern 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
- the shortest parts are placed in positions where the directions 5 d of their respective solder protrusions from adjacent solder bumps are not identical.
- the shortest parts 2 g are arranged so that the solder protrusion directions 5 d are not opposed to each other by shifting the following positions from each other: the position of each midpoint between shortest-pitch (nearest) bumps (opening patterns 2 d ) and the position of each midpoint between lands (outer shape patterns 2 f ).
- the individual shortest parts 2 g are so placed that their identical solder protrusion directions 5 d agree with the diagonal directions (oblique direction) of solder bumps 5 .
- a space between bumps can be additionally provided and this structure is preferable.
- FIG. 25 and FIG. 26 illustrate examples of isolated lands like signal bumps.
- the shortest parts 2 g in electrodes 2 c for flip chip bonding as isolated lands are arranged in such positions that their respective solder protrusion directions 5 d differ from one another between the bumps.
- the shortest parts 2 g in electrodes 2 c for flip chip bonding as isolated lands are arranged in positions where their respective solder protrusion directions 5 d are identical between the bumps.
- the structure in FIG. 26 makes it possible to provide solder with a tendency to protrude in the longest-pitch direction.
- the following shortest parts 2 g are placed in positions where they are not opposed to each other between bumps: the shortest parts where the distance between the following patterns is shortest: the outer shape pattern 2 f of an electrode 2 c for flip chip bonding in the wiring board 2 as viewed in a place and the opening pattern 2 d for the electrode 2 c for flip chip bonding in the solder resist film 2 e as viewed in a plane.
- a means for reducing the production of a solder bridge by lands (electrodes 2 c for flip chip bonding) on the substrate side has been taken as an example. Instead, the means in the second embodiment can also be applied to lands (electrode pads 4 c ) on the chip side.
- flux 9 is applied to solder bumps 5 a on the substrate side and then the reflow/cleaning (flux cleaning) is carried out before flip chip bonding is carried out has been described in relation to the first embodiment.
- This technology may be applied to solder bumps 5 b on the chip side and even in this case, the same effects as in cases where it is applied to solder bumps 5 a on the substrate side can be obtained.
- the following technologies may be combined or may be singly adopted: the technology for the assembly of a semiconductor device described in relation to the first embodiment and illustrated in FIG. 2 to FIG. 4 ; the technologies in the first modification to the fourth modification thereto; the technology related to the structure of a semiconductor device described in relation to the second embodiment; and the technologies in the first modification to the third modification to the second embodiment.
- the invention is favorably applicable to the assembly of an electronic device using flip chip bonding.
Abstract
The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5 a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5 a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.
Description
- The disclosure of Japanese Patent Application No. 2010-236213 filed on Oct. 21, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
- The present invention relates to a semiconductor device and processing technologies therefor and in particular to a technology effectively applicable to flip chip bonding using solder bumps.
- A technique for taking the following measure in a manufacturing process for semiconductor devices (semiconductor packages) is described in, for example, Japanese Unexamined Patent Publication No. 2007-227555 (Patent Document 1): a semiconductor device with molding resin exposed on the ball surface side is flip chip joined to a wiring board and underfill resin is filled between them.
- [Patent Document 1]
- Japanese Unexamined Patent Publication No. 2007-227555
- As one of semiconductor devices, flip chip bonded semiconductor devices are known. In the flip chip bonded semiconductor device, the following are electrically coupled together by flip chip bonding: multiple solder bumps formed over a semiconductor chip (hereafter, also simply referred to as chip) and solder bumps formed over the main surface of a substrate in positions corresponding to them. In flip chip bonded semiconductor devices, for example, the following advantages are obtained: the footprint of a semiconductor chip can be reduced as compared with wire bonded semiconductor devices; the number of surface electrodes of a semiconductor chip can be increased; and the signal speed between a semiconductor chip and a substrate can be enhanced.
- In conjunction with the enhancement of the functionality of semiconductor devices, the number of pins of each semiconductor device has tended to be increased. As a result, the bump pitch over each semiconductor chip has also tended to be narrowed. Consequently, the gap between bumps is also narrow; therefore, the following can take place when flip chip bonding is carried out using flux: when flux is cleaned off, cleaning fluid cannot get into between a chip and a substrate; and cleaning fluid is less prone to be discharged from between a chip and a substrate and this leads to the production of a residue, and as a result, the flux cannot be completely cleaned off.
- Consequently, the present inventors examined fluxless flip chip bonding.
- The drawings from
FIG. 27 toFIG. 30 illustrate the procedure for fluxless flip chip bonding in a comparative example examined by the present inventors; and the drawings fromFIG. 31 toFIG. 33 illustrate how a solder bridge results in solder bump bonding in the comparative example. - As illustrated in
FIG. 27 , first, awiring board 2 is positioned and placed in position over the upper surface of abonding stage 19 heated to a temperature close to a solder melting point. Thebonding stage 19 is provided with anexhaust system 19 a and is exhausted to vacuum through thisexhaust system 19 a and is caused to suck and hold thewiring board 2. - Meanwhile, the back surface of a
semiconductor chip 4 is sucked and held to the lower surface of a bondinghead 18 preheated to a preheat temperature higher than the solder melting point. The bondinghead 18 is provided with anexhaust system 18 a and is exhausted to vacuum through thisexhaust system 18 a and is caused to suck and hold thesemiconductor chip 4. Thesemiconductor chip 4 is positioned (aligned) to a predetermined position by the movement of thebonding head 18 in the horizontal direction and in this state, it is positioned above thewiring board 2. Since thebonding head 18 is heated to the predetermined preheat temperature higher than the solder melting point, in this state, the solder bumps 5 (5 b) formed over thesemiconductor chip 4 are melted. - As illustrated in
FIG. 28 , subsequently, the bondinghead 18 is moved down to place thesemiconductor chip 4 in position over thewiring board 2. Since thesemiconductor chip 4 is sucked to the lower surface of thebonding head 18, it is moved down in the vertical direction as is positioned in the horizontal direction. Thesemiconductor chip 4 is held over thewiring board 2 for a predetermined time with a predetermined gap maintained between them and is thereby flip chip mounted over thewiring board 2. - Thus the solder bumps 5(5 b) formed over the
semiconductor chip 4 and the solder bumps 5(5 a) formed over thewiring board 2 are brought into contact with each other. The solder bumps 5(5 a) on the substrate side are heated from the solder bumps 5(5 b) on the chip side and their temperature rises to the solder melting point or higher. - As illustrated in
FIG. 29 , thereafter, the melted and integratedsolder bumps 5 are periodically rhythmically vibrated (scrubbed) either in the horizontal direction X or in the vertical direction Y. - As a result, the oxide film covering the surfaces of the
solder bumps 5 is broken and taken into thesolder bumps 5 and thus bonding can be carried out without use of flux. As illustrated inFIG. 30 , thereafter, the suction of thesemiconductor chip 4 to the bondinghead 18 is canceled and the bondinghead 18 is moved up to terminate the flip chip bonding. - When either of the
solder bumps 5 on the chip side and thesolder bumps 5 on the substrate side is in a non-melted state and the other is in a melted state in the above-mentioned flip chip bonding, a problem arises. When contacting and pressing are carried out in this state, the following takes place: when the molten solder bumps (solder bumps 5 b) are brought into contact with and pressed into theunmelted solder bumps 5 a as illustrated in, for example,FIG. 31 , the following takes place: the molten solder is concavely deformed by the amount equivalent to this pressing and the unmelted solder is not deformed and becomes convex. As a result, as illustrated inFIG. 32 , the melted solder (solder bumps 5 b) is so deformed as to cover the unmelted solder (solder bumps 5 a) and the temperature of theunmelted solder bumps 5 a is rapidly raised and they are melted. - Thereafter, the
solder bumps 5 a are prevented from being deformed outward by pressing and becomelocal solder protrusions 5 c and are protruded in thesolder protrusion direction 5 d. As a result, a solder bridge becomes prone to be formed between adjacent bumps as illustrated inFIG. 33 . - This is because in fluxless flip chip bonding, an oxide film over the surfaces of the
solder bumps 5 a on the substrate side is nonuniformly formed. When thesolder bumps 5 b on the chip side are pressed, asolder protrusion 5 c may be formed depending on how the above-mentioned oxide film is ripped. That is, the present inventors found that in fluxless flip chip bonding, a solder bridge results (problem). - Patent Document 1 (Japanese Unexamined Patent Publication No. 2007-227555) discloses a fluxless flip chip bonding technique in which the following procedure is taken: the solder balls of a bare chip and the solder balls of a wiring board are brought into contact with each other; they are heated to a temperature higher than the melting point of solder; and ultrasonic vibration is applied to the bare chip to remove the oxide film over the ball surfaces.
- The invention has been made with the above problem taken into account and it is an object of the invention to provide a technology that enables the enhancement of joint reliability in flip chip bonding of a semiconductor device.
- The above and other objects and novel features of the invention will be apparent from the description in this specification and the accompanying drawings.
- The following is a brief description of the gist of the representative elements of the invention laid open in this application:
- A semiconductor device according to a representative embodiment includes: a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; a semiconductor chip placed over the upper surface of the wiring board by flip chip bonding; and multiple external terminals provided in the lower surface of the wiring board. Between adjacent bumps for the flip chip bonding, the shortest parts where the distance between the following patterns is shortest are placed in positions where they are not opposed to each other between the bumps: the outer shape pattern of each the electrode for flip chip bonding as viewed in a plane and the bump placement portion pattern for the electrode for flip chip bonding as viewed in a plane.
- A manufacturing method for a semiconductor device according to a representative embodiment includes the steps of: (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; (c) forming a solder ball over each of the electrodes for flip chip bonding of the wiring board; (d) after the step (c), applying flux to the multiple solder balls and then subjecting the solder balls to reflow/cleaning; and (e) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other.
- Another manufacturing method for a semiconductor device according to a representative embodiment includes the steps of; (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having multiple electrodes for flip chip bonding formed in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; (c) applying flux paste to each of the electrodes for flip chip bonding of the wiring board; (d) placing a solder ball on the flux paste over each of the electrodes for flip chip bonding; (e) after the step (d), subjecting the multiple solder balls to reflow/cleaning; and (f) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other.
- Further another manufacturing method for a semiconductor device according to a representative embodiment includes the steps of: (a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having solder balls formed over multiple electrodes for flip chip bonding in the upper surface; (b) preparing a semiconductor chip with each of multiple bump electrodes formed over an electrode pad; and (c) flip chip bonding the bump electrodes of the semiconductor chip and the solder balls of the wiring board to each other. In the flip chip bonding at the step (c), the semiconductor chip is presssed into the wiring board by two-staged pressing, first pressing and second pressing subsequent to the first pressing, to implement the flip chip bonding.
- The following is a brief description of the gist of the effect obtained by the representative elements of the invention laid open in this application:
- It is possible to reduce the production of solder bridges in flip chip bonding to enhance the joint reliability of the flip chip bonding of a semiconductor device.
-
FIG. 1 is a sectional view illustrating an example of the structure of a semiconductor device in a first embodiment of the invention and an enlarged partial sectional view of a flip chip bonded portion; -
FIG. 2 is a manufacturing flowchart illustrating an example of the structure on the substrate side in the assembly of the semiconductor device illustrated inFIG. 1 ; -
FIG. 3 is a manufacturing flowchart illustrating an example of flip chip bonding in the assembly of the semiconductor device illustrated inFIG. 1 ; -
FIG. 4 is a manufacturing flowchart illustrating an example of an underfill application and a ball mounting in the assembly of the semiconductor device illustrated inFIG. 1 ; -
FIG. 5 is a flowchart illustrating a first modification to the assembly of a semiconductor device in the first embodiment of the invention; -
FIG. 6 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 5 ; -
FIG. 7 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 5 ; -
FIG. 8 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 5 ; -
FIG. 9 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 5 ; -
FIG. 10 is a flowchart illustrating a second modification to the assembly of a semiconductor device in the first embodiment of the invention; -
FIG. 11 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 10 ; -
FIG. 12 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 10 ; -
FIG. 13 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 10 ; -
FIG. 14 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 10 ; -
FIG. 15 is a manufacturing flowchart illustrating a third modification to the assembly of a semiconductor device in the first embodiment of the invention; -
FIG. 16 is a partial sectional view illustrating a fourth modification to the assembly of a semiconductor device in the first embodiment of the invention; -
FIG. 17 is an enlarged partial sectional view illustrating the structure of a flip chip bonded portion in a semiconductor device in a comparative example related to a second embodiment of the invention; -
FIG. 18 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of a wiring board with the structure illustrated inFIG. 17 ; -
FIG. 19 is a plan view illustrating the solder bridge structure taken along line A ofFIG. 17 as viewed from above; -
FIG. 20 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of the wiring board in a semiconductor device in the second embodiment of the invention; -
FIG. 21 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in the solder resist film illustrated inFIG. 20 ; -
FIG. 22 is a plan view illustrating the positions of openings in a solder resist film relative to terminals of the wiring board in a semiconductor device in a first modification to the second embodiment of the invention; -
FIG. 23 is a plan view illustrating the structure of solder bumps placed over openings in the solder resist film illustrated inFIG. 22 ; -
FIG. 24 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in the solder resist film illustrated inFIG. 22 ; -
FIG. 25 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in a solder resist film of the wiring board in a semiconductor device in a second modification to the second embodiment of the invention; -
FIG. 26 is a plan view illustrating the direction of solder protrusions formed when solder bumps are placed over openings in a solder resist film of the wiring board in a semiconductor device in a third modification to the second embodiment of the invention; -
FIG. 27 is a partial sectional view illustrating a procedure for fluxless flip chip bonding in a comparative example; -
FIG. 28 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example; -
FIG. 29 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example; -
FIG. 30 is a partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example; -
FIG. 31 is an enlarged partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example; -
FIG. 32 is an enlarged partial sectional view illustrating the procedure for fluxless flip chip bonding in the comparative example; and -
FIG. 33 is an enlarged partial sectional view illustrating the structure of a solder bridge formed during the fluxless flip chip bonding in the comparative example. - In the following description of embodiments, the description of an identical or a similar part will not be repeated unless specially required.
- In the following description, each embodiment will be divided into multiple sections if necessary for the sake of convenience. Unless explicitly stated otherwise, they are not unrelated to one another and they are in such a relation that one is a modification, details, supplementary explanation, or the like of part or all of the other.
- When mention is made of any number of elements (including a number of pieces, a numeric value, a quantity, a range, and the like) in the following description of embodiments, the number is not limited to that specific number. Unless explicitly stated otherwise or the number is obviously limited to a specific number in principle, the foregoing applies and the number may be above or below that specific number.
- In the following description of embodiments, needless to add, their constituent elements (including elemental steps and the like) are not always indispensable unless explicitly stated otherwise or they are obviously indispensable in principle.
- When the wording of “made up of A,” “comprised of A,” “having A,” or “including A” is used in the following description of embodiments with respect to a constituent element or the like, those including any other element are hot excluded, needless to add. This applies unless it is explicitly stated that only element A is included or other like statement is made. Similarly, when mention is made of the shape, positional relation, or the like of a constituent element or the like in the following description of embodiments, it includes those substantially approximate or analogous to that shape or the like. This applies unless explicitly stated otherwise or it is apparent in principle that some shape or the like does not include those substantially approximate or analogous to that shape or the like. This is the same with the above-mentioned numeric values and ranges.
- Hereafter, detailed description will be given to embodiments of the invention with reference to, the drawings. In all the drawings illustrating embodiments, members having an identical function will be marked with identical reference numerals and the repetitive description thereof will be omitted.
-
FIG. 1 is a sectional view illustrating an example of the structure of a semiconductor device in the first embodiment of the invention and an enlarged partial sectional view of a flip chip bonded portion;FIG. 2 is a manufacturing flowchart illustrating an example of the manufacture on the substrate side in the assembly of the semiconductor device illustrated in FIG. 1;FIG. 3 is a manufacturing flowchart illustrating an example of flip chip bonding in the assembly of the semiconductor device illustrated inFIG. 1 ; andFIG. 4 is a manufacturing flowchart illustrating an example of an underfill application and ball mounting in the assembly of the semiconductor device illustrated inFIG. 1 . - As illustrated in
FIG. 1 , the semiconductor device in the first embodiment is a semiconductor package obtained by placing asemiconductor chip 4 over a substrate by flip chip bonding. In the description of the first embodiment, BGA (Ball Grid Array) 1 will be taken as an example of the semiconductor device. - Description will be given to the configuration of the
BGA 1 illustrated inFIG. 1 . TheBGA 1 includes: awiring board 2 that is a substrate having anupper surface 2 a and alower surface 2 b located on the opposite side thereto; thesemiconductor chip 4 placed over theupper surface 2 a of thewiring board 2 through multiple solder bumps (bump electrodes, solder balls) 5 and having a semiconductor integrated circuit formed therein;underfill 3 filled around each of the solder bumps 5 and around the side surface of thesemiconductor chip 4; andmultiple solder balls 7 as external terminals provided over thelower surface 2 b of thewiring board 2. Thesolder balls 7 are arranged, for example, in a lattice pattern in thelower surface 2 b of thewiring board 2. - Therefore, electrical signals sent from the
semiconductor chip 4 are transmitted tosolder balls 7 over thelower surface 2 b of thewiring board 2 throughsolder bumps 5 or wiring, through hole wiring, or the like, not shown, in thewiring board 2. - The
semiconductor chip 4 has: amain surface 4 a in whichmultiple electrode pads 4 c as surface electrodes are respectively formed in openings in aprotective film 4 d; and aback surface 4 b located on the opposite side to themain surface 4 a. Thesemiconductor chip 4 is electrically coupled with thewiring board 2 by flip chip bonding. As illustrated in the enlarged partial sectional view inFIG. 1 , that is, thesemiconductor chip 4 is electrically coupled with theelectrodes 2 c for flip chip bonding of thewiring board 2 through the solder bumps 5 respectively electrically coupled to theelectrode pads 4 c. Since thesemiconductor chip 4 is placed over thewiring board 2 by flip chip bonding, it is face-down mounted over thewiring board 2. Theupper surface 2 a of thewiring board 2 and themain surface 4 a of thesemiconductor chip 4 are opposed to each other; therefore, theback surface 4 b of thesemiconductor chip 4 faces upward. - Electronic components, such as
chip components 6, are mounted around thesemiconductor chip 4 in theupper surface 2 a of thewiring board 2. Thechip components 6 are, for example, a chip capacitor and a chip resistor and are solder mounted over thewiring board 2 throughsolder 8. - Description will be given to a manufacturing method for the semiconductor device in the first embodiment.
- First, a wiring board preparation of Step S1 in
FIG. 2 is carried out. As illustrated inFIG. 1 , thewiring board 2 has anupper surface 2 a and alower surface 2 b located on the opposite side to theupper surface 2 a. In addition,multiple electrodes 2 c for flip chip bonding are formed in theupper surface 2 a. Thewiring board 2 is a substrate that underwent wiring formation, surface insulating layer formation, land surface layer processing, and the like. In the description of the first embodiment, attention will be paid mainly to the state of the surfaces of the bumps for chip bonding. - Thereafter, a solder paste application of Step S2 is carried out. At this step, solder paste for flip chip bonding is applied. That is, to form the bumps for chip bonding,
solder paste 10 is applied to theelectrodes 2 c for flip chip bonding illustrated inFIG. 1 . Thesolder paste 10 is, for example, a paste material containing flux and solder at a volume ratio of approximately 50%. Thesolder paste 10 is applied to eachelectrode 2 c for flip chip bonding from above by a print process using a metal mask. - Thereafter, a reflow/cleaning of Step S3 is carried out. At this step, heat treatment is carried out using a nitrogen reflow furnace with the oxygen concentration controlled to, for example, 100 ppm or below. Solder bumps (solder balls) 5 a are thereby formed over the
predetermined electrodes 2 c for flip chip bonding. Further, flux cleaning is carried out to remove flux. - Thereafter, a solder paste application of Step S4 is carried out. At this step, for example, the
solder paste 10 for peripheral element placement is applied only to areas where a peripheral element is to be placed by a print process using a metal mask. - Thereafter, peripheral element placement & reflow/cleaning of Step S5 is carried out. At this step, electronic components, such as
chip components 6, are placed over thesolder paste 10 and the reflow/cleaning (flux cleaning) is carried out by the same method as the reflow/cleaning of Step S3 to solder mount thechip components 6 over thewiring board 2. - Thereafter, a flux application of Step S6 is carried out. At this step,
flux 9 is applied to the solder bumps 5 a over theelectrodes 2 c for flip chip bonding. Further, a reflow/cleaning of Step S7 is carried out. That is, theflux 9 is applied to the solder bumps 5 a for flip chip bonding and then reflow and cleaning processing is carried out. - In the assembly of the semiconductor device in the first embodiment, the following can be implemented by the flux application and reflow/cleaning (flux cleaning) after the completion of the mounting of the chip components 6: reflow processing can be carried out without the
flux 9 left over the solder bumps 5 a for flip chip bonding. Therefore, the thick and nonuniform surface oxide film over the solder bumps 5 a can be turned into a thin and uniform surface oxide film. - Each of the solder bumps 5 a for flip chip bonding is 80 μm in bump diameter and 50 μm in bump height when the bump pitch is, for example, 150 μm. Since it is necessary to minimize variation in bump height, it is required to supply solder with accuracy. In addition, the bump placement surface must be flat. Therefore, it is desirable to take the procedure shown in the flow in
FIG. 2 . That is, it is desirable that the solder bumps 5 a for flip chip bonding should be formed first and then peripheral elements (electronic components), such aschip components 6, should be placed. - In this case, that is, the order of the placement of peripheral elements and the formation of
solder bumps 5 a for flip chip bonding is critical. This is the same also when any formation method other than a solder paste print process is adopted to form the solder bumps 5 a for flip chip bonding at Steps S2 and S3. - The same effect is obtained even when flip chip bonding is carried out using the following solder bumps: solder bumps 5 a obtained by subjecting bumps formed beforehand to reflow processing without carrying out anti-oxidation processing, such as flux application, and thereafter applying flux and carrying out the reflow/cleaning again.
- After the
wiring board 2 is prepared by the assembly illustrated inFIG. 2 , flip chip bonding is carried out by the assembly illustrated inFIG. 3 . - First, a
semiconductor chip 4 withmultiple solder bumps 5 b respectively formed over theelectrode pads 4 c illustrated inFIG. 1 is prepared. As illustrated inFIG. 3 , thereafter, the solder bumps (bump electrodes) 5 b of thesemiconductor chip 4 and the solder bumps (solder balls) 5 a of thewiring board 2 are (fluxless) flip chip bonded to each other. - In the flip chip bonding, first, a chip bump heat melting & alignment of Step S11 in
FIG. 3 is carried out. First, thewiring board 2 is positioned in a predetermined position in the supporting surface of abonding stage 19 heated to a temperature close to a solder melting point and placed there. Thebonding stage 19 is provided with anexhaust system 19 a and is exhausted to vacuum through thisexhaust system 19 a to suck and hold thewiring board 2. - Meanwhile, the
back surface 4 b of thesemiconductor chip 4 is sucked and held by the suction surface of abonding head 18 preheated to a predetermined preheat temperature higher than the solder melting point. Thebonding head 18 is provided with anexhaust system 18 a and is exhausted to vacuum through thisexhaust system 18 a to suck and hold thesemiconductor chip 4. Thesemiconductor chip 4 is positioned (aligned) in a predetermined position by the movement of thebonding head 18 in the horizontal direction and in this state, it is positioned above thewiring board 2. Since thebonding head 18 is heated to the predetermined preheat temperature higher than the solder melting point, in this state, the solder bumps 5 (5 b) formed over thesemiconductor chip 4 are melted. - Thereafter, a chip/substarate bump contacting & pressing of Step S12 is carried out. At this step, the
bonding head 18 is moved down to place thesemiconductor chip 4 over thewiring board 2 in a predetermined position. That is, thesemiconductor chip 4 is placed so that the solder bumps 5 a on the substrate side and the solder bumps 5 b on the chip side are aligned with each other. Since thesemiconductor chip 4 is sucked to the suction surface of thebonding head 18, it is moved down in the vertical direction as is positioned in the horizontal direction. Thesemiconductor chip 4 is held for a predetermined time with a predetermined distance maintained between thewiring board 2 and thesemiconductor chip 4 and is thereby flip chip placed over thewiring board 2. - As a result, the solder bumps 5 b formed over the
semiconductor chip 4 and the solder bumps 5 a formed over thewiring board 2 are brought into contact with each other. Further, the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side. The solder bumps 5 a on the substrate side are heated by the solder bumps 5 b on the chip side and their temperature becomes equal to or higher than the solder melting point. - As shown in the illustration of a chip/substrate bump bonding of Step S13, thereafter, the integrated and melted
solder bumps 5 are periodically rhythmically vibrated (scrubbed) either in the horizontal direction X or in the vertical direction Y. - As a result, the oxide film covering the surfaces of the solder bumps 5 is broken and taken into the solder bumps 5 and thus flip chip bonding is achieved.
- As shown in the illustration of, a chip releasing of Step S14, the suction of the
semiconductor chip 4 to thebonding head 18 is canceled and thebonding head 18 is moved up to complete flip chip bonding. - After the completion of flip chip bonding, an underfill application of Step S15 in
FIG. 4 is carried out. At this step, underfill 3 is dripped to the side of thesemiconductor chip 4 to fill the gap between thesemiconductor chip 4 and thewiring board 2 with theunderfill 3. That is, theunderfill 3 is filled to the flip chip bonded portions and it is also supplied to the side surface of thesemiconductor chip 4 to cover the periphery of thesemiconductor chip 4 with theunderfill 3. The flip chip bonded portions and thesemiconductor chip 4 are thereby protected. - Thereafter, an outer ball mounting of Step S16 is carried out. At this step, the
lower surface 2 b of thewiring board 2 is provided with a predetermined number of solder balls (external terminals) 7. - This completes the assembly of the
BGA 1. - According to the
BGA 1 in the first embodiment and the assembly thereof, theflux 9 is applied to the solder bumps 5 a for flip chip bonding over the substrate before fluxless flip chip bonding is carried out. In addition, after the reflow/cleaning (flux cleaning) is carried out, flip chip bonding is carried out. Thus the flip chip bonding can be achieved with the oxide film over the surfaces of the solder bumps 5 a made relatively thin and uniform. - That is, the surface oxide film of the solder bumps 5 a can be made uniform by forming the solder bumps 5 a of the
solder paste 10 and thereafter applying theflux 9 again and carrying out the reflow/cleaning (flux cleaning) again. - As mentioned above, the surface oxide film of the solder bumps 5 a on the substrate side is made uniform before fluxless flip chip bonding is carried out. As a result, the shape of solder protrusions outward of solder when the solder bumps 5 a are pressed is spread (concentrically) all around the bumps (balls) by the surface tension of molten solder. Or, the solder protrusions take on such a shape that their tips are rounded.
- That is, it is possible to prevent the production of
local solder protrusions 5 c and reduce the production of a solder bridge between adjacent bumps during fluxless flip chip bonding. - As a result, it is possible to enhance the joint reliability in flip chip bonding of the BGA 1 (semiconductor device).
- As mentioned above, solder protrusions produced at the time of solder pressing can be provided with an entire circumferential shape (concentric shape) or a rounded shape. As a result, the gap between chip and substrate where a bridge between adjacent bumps is produced is reduced and it is possible to increase the amount of solder pressing. Since the oxide film over the surfaces of the solder bumps is relatively thin and uniform, the oxide film over the surfaces of the solder bumps is easy to break and it is possible to reduce the amount of solder pressing required for bonding. As a result, it is possible to ensure a large area for pressing solder so that bonding can be achieved.
- The
BGA 1 is a semiconductor device having a structure in whichchip components 6 are solder mounted around thesemiconductor chip 4. That is, after the solder bumps 5 a for flip chip bonding are formed by the reflow/cleaning, thesolder 8 for thechip components 6 are subjected to the reflow/cleaning. At this stage, the solder bumps 5 a are heated and melted without flux and their surface oxide film is increased in thickness. Therefore, the surface oxide film of the solder bumps 5 a is not uniform. In theBGA 1 in the first embodiment, however, theflux 9 is applied to the solder bumps 5 a and the reflow/cleaning (flux cleaning) is carried out again before flip chip bonding is carried out Therefore, the surface oxide film of the solder bumps 5 a can be made relatively thin and uniform by the oxide film removing effect of flux before flip chip bonding. That is, the following can be implemented even in theBGA 1 having such a structure that electronic components, such aschip components 6, are solder mounted around the semiconductor chip 4: the production of solder bridges can be reduced to enhance the joint reliability in flip chip bonding. - In the assembly of the
BGA 1 in the first embodiment, the meltedsolder bumps 5 b on the chip side are brought into contact with and pressed into the solder bumps 5 a on the substrate side during flip chip bonding. When the bumps at least on either side are melted during flip chip bonding, as mentioned above, protruded bumps are prone to be formed at the time of bump pressing. - The reason for this is as follows. When molten solder bumps are brought into contact with and pressed into unmelted solder bumps, the molten solder is concavely deformed and the unmelted solder is convexly deformed so that the melted solder covers the unmelted solder. As a result, the temperature of the unmelted solder bumps is rapidly raised and they are prevented from being uniformly deformed outward after melting. As a result, such
local solder protrusions 5 c as illustrated inFIG. 32 are formed and this is likely to lead to solder bridges between adjacent bumps. - The flip chip bonding of the
BGA 1 in the first embodiment is carried out after the following procedure is taken: the solder bumps 5 a on the substrate side are subjected to the flux application and the reflow/cleaning again to make uniform the surface oxide film of the solder bumps 5 a. Therefore, the following can be implemented even when the bumps on either side are melted: the solder protrusions can be spread (concentrically) all around the bumps by the surface tension of the molten Solder and the production of solder bridges can be reduced. - Description will be given to a first modification to the first embodiment.
-
FIG. 5 is a flowchart illustrating the first modification to the assembly of the semiconductor device in the first embodiment of the invention;FIG. 6 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 5 ;FIG. 7 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 5 ;FIG. 8 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 5 ; andFIG. 9 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 5 . - The first modification is an example of assembly in which the following procedure is taken: the solder bumps 5 b on the chip side are formed by a printing method and the flux application and the reflow/cleaning are carried out only on the solder bumps 5 a on the substrate side.
- First, description will be given to the formation of bumps for flip chip bonding on the chip side. A preparation of land-formed wafer of Step S21 in
FIG. 5 is carried out. At this step, a wafer (semiconductor wafer) 12 includingmultiple electrode pads 4 c as aluminum electrodes and aprotective film 12 a for protecting the surface thereof is prepared by wafer preparation of Step S41 inFIG. 6 . - Thereafter, a formation of bump underlaying metal film of Step S42 is carried out. At this step, a bump underlaying
metal film 12 b is formed over theelectrode pads 4 c andprotective film 12 a over the surface of thewafer 12. For example, Ti, NiV, Cu, or the like is used for the bump underlaying metal film. - Thereafter, an etching resist film formation of Step S43 is carried out. At this step, an etching resist
film 12 c is formed in multiple bump placement portions for flip chip bonding. - Thereafter, underlaying film etching & resist film removal of Step S44 is carried out. First, using the etching resist
film 12 c as a mask, etching is carried out to remove the unnecessary portions of the bump underlayingmetal film 12 b and then the etching resistfilm 12 c is removed. This establishes a state in which the bump underlayingmetal film 12 b is formed over eachelectrode pad 4 c in thewafer 12. - Thereafter, solder paste application of Step S22 in
FIG. 5 is carried out. At this step,solder paste 10 is formed over the bump underlayingmetal films 12 b in the bump placement portions by a print process using aprinting mask 14 as a metal mask by solder paste printing of Step S45 inFIG. 7 . At this time, first, theprinting mask 14 is placed around the bump underlayingmetal films 12 b as the bump placement portions and then solderpaste 10 is printed over the bump underlayingmetal films 12 b by a print process using asqueegee 13. - Thereafter, a printing mask removal of Step S46 in
FIG. 7 is carried out. At this step, theprinting mask 14 over thewafer 12 is removed. - Thereafter, reflow/cleaning of Step S23 in
FIG. 5 and Step S47 inFIG. 7 is carried out. At this step, thesolder paste 10 over thewafer 12 is heated and melted at a predetermined temperature by ref lowing and cleaned (flux cleaning) to formmultiple solder bumps 5 b. - Thereafter, a chip dicing of Step S24 in
FIG. 5 (a chip segmentation of Step S48 inFIG. 7 ) is carried out. At this step, the wafer is diced into a chip size to formsemiconductor chips 4 each havingmultiple solder bumps 5 b placed therein. - With respect to the thickness of each
semiconductor chip 4, wafer back surface polishing is carried out to a predetermined wafer thickness after or before the formation of the solder bumps 5 b. Thus a desired chip thickness can be obtained. - Description will be given to the formation of bumps for flip chip bonding on the substrate side. A preparation of land-formed substrate of Step S31 in
FIG. 5 is carried out. At this step, the following matrix arrayedsubstrate 11 having a plurality of device forming areas is prepared by a substrate preparation of Step S51 inFIG. 8 : a matrix arrayedsubstrate 11 having a plurality of device forming areas as a multilayer wiring board includingmultiple electrodes 2 c for flip chip bonding as copper lands, a solder resistfilm 11 a for protecting the surface thereof, andmultiple land terminals 11 b formed on the back surface side. - Thereafter, a solder paste application of Step S32 in
FIG. 5 is carried out. At this step,solder paste 10 is formed over themultiple electrodes 2 c for flip chip bonding by a print process using aprinting mask 14 as a metal mask by a solder paste printing of Step S52 inFIG. 8 . Thesolder paste 10 is, for example, a paste material containing flux and solder at a volume ratio of approximately 50%. First, theprinting mask 14 is placed around theelectrodes 2 c for flip chip bonding and then thesolder paste 10 is printed over theelectrodes 2 c for flip chip bonding by a print process using asqueegee 13. - Thereafter, a printing mask removal of Step S53 in
FIG. 8 is carried out. At this step, theprinting mask 14 over the matrix arrayedsubstrate 11 having a plurality of device forming areas is removed. - Thereafter, reflow/cleaning of Step S33 in
FIG. 5 and Step S54 inFIG. 8 is carried out. At this step, thesolder paste 10 over theelectrodes 2 c for flip chip bonding of the matrix arrayedsubstrate 11 having a plurality of device forming areas is heated and melted at a predetermined temperature by ref lowing and cleaned to formmultiple solder bumps 5 a. - Thereafter, a probing of Step S55 in
FIG. 9 is carried out. At this step, aprobe 15 is brought into contact with themultiple solder bumps 5 a over the matrix arrayedsubstrate 11 having a plurality of device forming areas to conduct electrical testing. - Thereafter, a flux application of Step S34 in
FIG. 5 (Step S56 inFIG. 9 ) is carried out. That is,flux 9 is applied (re-applied) so as to cover themultiple solder bumps 5 a provided over the matrix arrayedsubstrate 11 having a plurality of device forming areas. - Thereafter, reflow/cleaning of Step S35 in
FIG. 5 (flux cleaning of Step S57 inFIG. 9 ) is carried out. That is, the solder bumps 5 a over the matrix arrayedsubstrate 11 having a plurality of device forming areas with theflux 9 applied thereto are heated and cleaned (flux cleaning) at a predetermined temperature by reflowing. This makes it possible to eliminate variation in bump height due to a probing mark, thin the surface oxide film sticking to each of the solder bumps 5 a, and make the surface oxide film uniform. - Thereafter, a substrate segmentation of Step S58 in
FIG. 9 is carried out to formwiring boards 2 each havingmultiple solder bumps 5 a for flip chip bonding placed therein. - Thereafter, a flip chip bonding of Step S36 in
FIG. 5 is carried out. At this step, flip chip bonding is carried out using the following semiconductor chip and wiring board: asemiconductor chip 4 withmultiple solder bumps 5 b placed therein shown in the illustration of Step S48 inFIG. 7 and awiring board 2 withmultiple solder bumps 5 a placed therein shown in the illustration of Step S58 inFIG. 9 . - At this time, the same (fluxless) flip chip bonding method as illustrated as Step S11 to Step S14 in
FIG. 3 is used to flip chip bond the following semiconductor chip and wiring board to each other: thesemiconductor chip 4 shown in the illustration of Step S48 inFIG. 7 and thewiring board 2 shown in the illustration of Step S58 inFIG. 9 . This completes the assembly. - Description will be given to a second modification to the first embodiment.
-
FIG. 10 is a flowchart illustrating the second modification to the assembly of the semiconductor device in the first embodiment of the invention;FIG. 11 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 10 ;FIG. 12 is a manufacturing flowchart illustrating part of the assembly on the chip side in the flow illustrated inFIG. 10 ;FIG. 13 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 10 ; andFIG. 14 is a manufacturing flowchart illustrating part of the assembly on the substrate side in the flow illustrated inFIG. 10 . - In the second modification, the solder bumps 5 b on the chip side are formed by plating and the solder bumps 5 a on the substrate side are formed by a micro solder ball placement method. It is an example of assembly in which the flux application and the reflow/cleaning are carried out on the solder bumps 5 a on the substrate side.
- Description will be given to the formation of bumps for flip chip bonding on the chip side. A preparation of pad opening-formed wafer of Step S61 in
FIG. 10 is carried out. At this step, the following wafer (semiconductor wafer) 12 is prepared by a wafer preparation of Step S81 inFIG. 11 : a wafer in whichmultiple electrode pads 4 c as bump placement portions and aluminum electrodes and aprotective film 12 a exposing theelectrode pads 4 c by openings therein are formed. - Thereafter, a formation of bump underlaying metal film of Step S82 is carried out. At this step, a bump underlaying
metal film 12 b (UBM) is formed over the entire surface of thewafer 12 by sputtering using the UBM (Under Bump Metal) sputtering of Step S62 inFIG. 10 . That is, the bump underlayingmetal film 12 b is formed over theelectrode pads 4 c andprotective film 12 a over the surface of thewafer 12 by sputtering. For example, Ti, Cu, or the like is used for the bump underlaying metal film. - Thereafter, a resist film formation of Step S83 is carried out. At this step, first, plating resist film formation and patterning of Step S63 in
FIG. 10 is carried out. That is, a plating resistfilm 12 d is applied to thewafer 12 by a spin coat method and openings are formed in positions corresponding to bump placement portions by a photoengraving process. - Thereafter, a plating film formation of Step S84 is carried out. At this step, formation of Ni plating film and solder plating film of Step S64 in
FIG. 10 is carried out. That is, a Ni plating film, not shown, is formed as a solder diffusion barrier over the bump underlayingmetal film 12 b and then asolder plating film 12 e is formed as shown in the illustration of Step S84 inFIG. 11 . - Thereafter, a resist film removal of Step S85 is carried out. That is, the portions of the plating resist
film 12 d around thesolder plating films 12 e are removed. - Thereafter, a flux application of Step S86 in
FIG. 12 (Step S65 inFIG. 10 ) is carried out. At this step,flux 9 is applied to the multiplesolder plating films 12 e over thewafer 12 by a spin coat method. - Thereafter, a flux cleaning of Step S87 (reflow/cleaning of Step S66 in
FIG. 10 ) is carried out. At this step, thesolder plating films 12 e over thewafer 12 are heated and melted at a predetermined temperature by ref lowing and cleaned to formmultiple solder bumps 5 b. - Thereafter, an underlaying film etching of Step S88 is carried out. At this step, the exposed bump underlaying
metal films 12 b other than those located under the solder bumps 5 b are etched using the solder bumps 5 b as a mask and removed by UBM etching of Step S67 inFIG. 10 . - Wafer back surface polishing is carried out as required to control the thickness of the
wafer 12 to a desired value. - Thereafter, a chip dicing of Step S68 in
FIG. 10 (chip segmentation of Step S89 inFIG. 12 ) is carried out. At this step, the wafer is diced into a chip size to formsemiconductor chips 4 each havingmultiple solder bumps 5 b placed therein. - Description will be given to the formation of bumps for flip chip bonding on the substrate side. A preparation of land-formed substrate of Step S71 in
FIG. 10 is carried out. At this step, the following matrix arrayedsubstrate 11 having a plurality of device forming areas is prepared by a substrate preparation of Step S91 inFIG. 13 : a matrix arrayedsubstrate 11 having a plurality of device forming areas as a multilayer wiring board includingmultiple electrodes 2 c for flip chip bonding as copper lands and a solder resistfilm 11 a for protecting the surface thereof. The copper lands may be coated with a Ni/Au plating, a Ni/Pd/Au plating, a Sn plating, or the like. - Thereafter, a flux paste application of Step S72 in
FIG. 10 is carried out. At this step, paste-like flux 9 (flux paste) is applied to themultiple electrodes 2 c for flip chip bonding by a print process using aprinting mask 14 as a metal mask by a flux printing of Step S92 inFIG. 13 . The paste-like flux 9 is 100% flux. - Thereafter, a micro ball placement of Step S73 in
FIG. 10 is carried out. At this step, first, theprinting mask 14 is removed and then aball placement mask 16 is placed in position over the matrix arrayedsubstrate 11 having a plurality of device forming areas by a solder ball placement of Step S93 inFIG. 14 . In theball placement mask 16, openings are formed in correspondence with the positions of theelectrodes 2 c for flip chip bonding as bump placement portions. After the placement of the ball placement mask,small solder balls 17 as micro balls are shaken into the openings in theball placement mask 16. This establishes a state in which asmall solder ball 17 is placed over the paste-like flux 9 (flux paste) over each of theelectrodes 2 c for flip chip bonding. - Thereafter, reflow/cleaning of Step S74 in
FIG. 10 and Step S94 inFIG. 14 is carried out. At this step, thesmall solder balls 17 placed over the paste-like flux 9 over theelectrodes 2 c for flip chip bonding of the matrix arrayedsubstrate 11 having a plurality of device forming areas are heated and melted at a predetermined temperature by ref lowing and cleaned (flux cleaning) to formmultiple solder bumps 5 a. - This makes it possible to thin the surface oxide film sticking to each of the solder bumps 5 a and make the surface oxide films uniform.
- Thereafter, a substrate segmentation of Step S95 in
FIG. 14 is carried out to formwiring boards 2 each havingmultiple solder bumps 5 a for flip chip bonding placed therein. - Thereafter, a flip chip bonding of Step S75 in
FIG. 10 is carried out. At this step, flip chip bonding is carried out using the following semiconductor chip and wiring board: asemiconductor chip 4 withmultiple solder bumps 5 b placed therein shown in the illustration of Step S89 inFIG. 12 and awiring board 2 withmultiple solder bumps 5 a placed therein shown in the illustration of Step S95 inFIG. 14 . - At this time, the same (fluxless) flip chip bonding method as illustrated as Step S11 to Step S14 in
FIG. 3 is used to flip chip bond the following semiconductor chip and wiring board to each other: thesemiconductor chip 4 shown in the illustration of Step S89 inFIG. 12 and thewiring board 2 shown in the illustration of Step S95 inFIG. 14 . This completes the assembly. - Also in the first modification and the second modification, as mentioned above, the
flux 9 is supplied to the solder bumps 5 a on the substrate side before thesemiconductor chip 4 and thewiring board 2 are flip chip bonded to each other. Further, reflow/cleaning (flux cleaning) is carried out before flip chip bonding is carried out. This makes it possible to thin the surface oxide film of the solder bumps 5 a and carry out flip chip bonding with the surface oxide films uniformly formed. - Thus as in the assembly of the semiconductor device (BGA 1) illustrated in
FIG. 2 toFIG. 4 , it is possible to suppress the production oflocal solder protrusions 5 c during fluxless flip chip bonding. As a result, it is possible to reduce the production of a solder bridge between adjacent bumps during flip chip bonding. Since the oxide film over the surfaces of the solder bumps is relatively thin and uniform, the oxide film over the surfaces of the solder bumps are easy to break. As a result, it is possible to reduce the amount of solder pressing required for bonding and reduce the occurrence of solder joint failure. - Further, it is possible to enhance the joint reliability in the flip chip bonding.
- The other effects obtained by the first modification and the second modification are the same as the other effects obtained by the assembly of the semiconductor device (BGA 1) illustrated in
FIG. 2 toFIG. 4 ; therefore, the repetitive description thereof will be omitted. - With respect to the flip chip bonding method, the measure described below is taken. The above effects are obtained by the flip chip bonding procedure in which: the solder bumps 5 b on the chip side and the solder bumps 5 a on the substrate side are brought into contact with each other; and then they are further presses into each other to join the bumps together. Therefore, the steps up to melting and joining of bumps are carried out in a flip chip bonder. In this local reflow flip chip bonding, bumps are pressed into each other by expansion of a bonding tool, a substrate, and the like and the same effects can be obtained even in cases where the procedures described below are taken. In a procedure, alignment in, for example, the flow illustrated in
FIG. 3 and a chip bump heat melting &alignment is carried out without melting bumps and thereafter the bonding tool is moved down; and after contact is detected, the bonding tool is heated to carry out bonding. In another procedure, theflux 9 is transferred to the solder bumps 5 b on the chip side during flip chip bonding; the solder bumps 5 b on the chip side and the solder bumps 5 a on the substrate side are aligned with each other; then the bonding tool is moved down; and after contact is detected, the bonding tool is heated to carry out bonding. - Description will be given to a third modification to the first embodiment.
-
FIG. 15 is a manufacturing flowchart illustrating the third modification to the assembly of the semiconductor device in the first embodiment of the invention. - In the third modification, the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side by two-stage action during flip chip bonding.
- More specific description will be given. The
semiconductor chip 4 supported by thebonding head 18 is placed so that the following is implemented by a chip placement of Step S101 illustrated inFIG. 15 : the solder bumps 5 a on the substrate side and the solder bumps 5 b on the chip side are opposed to each other over thewiring board 2. Thereafter, the solder bumps 5 b on the chip side are brought into contact with the solder bumps 5 a on the substrate side. After this contact, thesemiconductor chip 4 is pressed into thewiring board 2 by the pressing amount Y1 as shown by a first pressing in Step S102. Further, first scrubbing operation (periodical rhythmical vibration) is carried out with the amplitude X1 as shown by a first scrubbing of Step S103. - Thereafter, the
semiconductor chip 4 is pressed with the pressing amount Y2 by a second pressing of Step S104 and second scrubbing operation is carried out with the amplitude X2 as shown in the illustration of a second pressing of Step S105. - That is, the solder bumps 5 b on the chip side are pressed into the solder bumps 5 a on the substrate side by two-stage action. At this time, it is desirable to make the pressing amount Y1 in first pressing smaller than the pressing amount Y2 in second pressing. That is, Y1<Y2.
- The reason for this is as follows. There are
solder bumps higher solder bumps lower solder bumps - This makes it possible to suppress the length of such
local solder protrusions 5 c as illustrated inFIG. 32 . More specific description will be given. In a first pressing illustrated inFIG. 15 , a solder protrusion may be locally produced in a place where the surface oxide film of molten solder bumps is prone to be broken during bonding. Even in this case, the solder protrusion amount (length) can be suppressed because the pressing amount Y1 in the first pressing is smaller than the pressing amount Y2 in the second pressing (Y1<Y2). - In general, a bridge between adjacent bumps is prone to be produced when the bumps are large in volume (high bumps) and the protrusion amount is large. To cope with this, these bumps are scrubbed in the position of the first pressing with the amplitude X1 so that the local broken areas in the surface oxide film are spread all around the bumps. Also in the second pressing thereafter carried out, such
solder protrusion directions 5 d as shown inFIG. 32 are made to extend (concentrically) all around the bumps. This makes it possible to suppress the production of local solder protrusions and prevent the production of a solder bridge between adjacent bumps. - In the description of the above pressing of the
semiconductor chip 4, two-stepped pressing action (action in which pressing and scrubbing are divided from each other) has been taken as an example. The same effect can be obtained even by simultaneously carrying out pressing and scrubbing in place of stepped action. - Description will be given to a fourth modification to the first embodiment.
-
FIG. 16 is a partial sectional view illustrating the fourth modification to the assembly of the semiconductor device in the first embodiment of the invention. - In the fourth modification illustrated in
FIG. 16 , solder bumps 5 b are formed only on the chip side in bump bonding. That is, the drawing illustrates solder bump bonding carried out when solder bumps 5 b are provided only in thesemiconductor chip 4 and bumps are not provided on the substrate side. Even in this bump bonding, the same effect as in the assembly of the semiconductor device (BGA 1) illustrated inFIG. 2 toFIG. 4 and the first modification to the third modification is obtained as long as the following measure is taken in flip chip bonding: after molten solder bumps are brought into contact, they are pressed to break the surface oxide film of the solder bumps 5 b. The production of local solder protrusions can be prevented even in the following cases: cases where the wiring board is a chip as in a chip-on-chip structure; cases where a configuration in which bumps are not used on the wiring board side is adopted; and cases where solder bumps are formed only either on the chip side or on the substrate side. As a result, it is possible to reduce the production of a solder bridge between adjacent bumps during flip chip bonding and obtain the same effect as mentioned above. -
FIG. 17 is an enlarged partial sectional view illustrating the structure of a flip chip bonded portion in a semiconductor device in a comparative example related to the second embodiment of the invention;FIG. 18 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board with the structure illustrated inFIG. 17 ; andFIG. 19 is a plan view illustrating the solder bridge structure cut along line A ofFIG. 17 as viewed from above.FIG. 20 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board in a semiconductor device in the second embodiment of the invention;FIG. 21 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over the openings in the solder resist film illustrated inFIG. 20 ; andFIG. 22 is a plan view illustrating the positions of openings in the solder resist film relative to terminals of the wiring board in a semiconductor device in a first modification to the second embodiment of the invention.FIG. 23 is a plan view illustrating the structure of solder bumps placed over the openings in the solder resist film illustrated inFIG. 22 ;FIG. 24 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over the openings in the solder resist film illustrated inFIG. 22 ;FIG. 25 is a plan view illustrating the directions of solder protrusions obtained when solder bumps are placed over openings in the solder resist film of the wiring board in a semiconductor device in a second modification to the second embodiment of the invention; andFIG. 26 is a plan view illustrating the direction of solder protrusions obtained when solder bumps are placed over openings in the solder resist film of the wiring board in a semiconductor device in a third modification to the second embodiment of the invention. - The second embodiment is so configured that the production of local solder protrusions is suppressed during flip chip bonding in a semiconductor device (for example, the
BGA 1 illustrated inFIG. 1 ) assembled by carrying out flip chip bonding. The production of local solder protrusions is suppressed by the structure of awiring board 2 flip chip bonded with a semiconductor chip. - In the description of the second embodiment, the following case will be taken as an example with respect to the solder bridges (bridges between bumps) illustrated in the comparative example in
FIG. 17 andFIG. 19 : cases where the pits and projections (opening pattern) in the insulating film over the substrate surface are so shaped, as viewed in a plane, that the following is implemented: a bridge between adjacent bumps is less prone to be produced because of the relation with the outer shape pattern (land metal shape) of eachelectrode 2 c for flip chip bonding. - In solder bumps, the following takes place when the oxide film over the surfaces of bumps are thin and uniform:
such solder protrusions 5 c as illustrated inFIG. 19 tend to enlarge as the distance between the substrate surface and the chip surface is narrowed. -
FIG. 17 andFIG. 19 illustrating solder bumps 5 show a case where multiple bumps are formed over each of common large metal lands (electrodes 2 c for flip chip bonding) like a power supply and ground. The drawings show the boundary between metal lands (electrodes 2 c for flip chip bonding) different in kind, for example, ground and a power supply. - When there is a recessed
portion 2 h in the solder resistfilm 2 e as an insulating film over the substrate surface, the following may take place depending on, for example, the shape of each metal land (electrode 2 c for flip chip bonding) of the wiring board 2: as illustrated inFIG. 17 , thesolder protrusion directions 5 d tend to extend to the direction thereof (toward the recessedportion 2 h): Therefore, such a land shape that asolder protrusion 5 c is extended to the direction of the shortest pitch (the nearest area) reduces the pressing amount at which a bridge between adjacent bumps and narrows the settable range of pressing amount to reduce the junction margin. As a result, a solder bridge results. - That is, a solder bridge is prone to be caused when the following
shortest parts 2 g are placed in positions where they are opposed to each other betweenadjacent solder bumps 5 between the bumps in flip chip bonding as illustrated inFIG. 18 : theshortest parts 2 g where the distance between the following patterns is shortest: theouter shape pattern 2 f of anelectrode 2 c for flip chip bonding as a metal land as viewed in a plane; and the opening pattern (bump placement portion pattern) 2 d for theelectrode 2 c for flip chip bonding in the solder resistfilm 2 e as viewed in a plane. - In the second embodiment, consequently, the following
shortest parts 2 g are placed in positions where they are not opposed to each other between adjacent bumps between the bumps in flip chip bonding: theshortest parts 2 g where the distance between the following patterns is shortest: theouter shape pattern 2 f of anelectrode 2 c for flip chip bonding in thewiring board 2 as viewed in a plane; and the opening pattern (bump placement portion pattern) 2 d for theelectrode 2 c for flip chip bonding in the solder resistfilm 2 e as viewed in a plane. - Some examples will be taken. With respect to the following patterns in
FIG. 20 , theshortest part 2 g refers to a part where the distance L between theouter shape pattern 2 f and theopening pattern 2 d is shortest: theouter shape pattern 2 f of anelectrode 2 c for flip chip bonding as viewed in a place and theopening pattern 2 d for theelectrode 2 c for flip chip bonding in the solder resistfilm 2 e as viewed in a plane. As illustrated inFIG. 21 , the shortest parts are placed in positions where thedirections 5 d of their respective solder protrusions from adjacent solder bumps are not identical. - That is, the
shortest parts 2 g are arranged so that thesolder protrusion directions 5 d are not opposed to each other by shifting the following positions from each other: the position of each midpoint between shortest-pitch (nearest) bumps (openingpatterns 2 d) and the position of each midpoint between lands (outer shape patterns 2 f). - In the first modification to the second embodiment illustrated in
FIG. 22 toFIG. 24 , the individualshortest parts 2 g are so placed that their identicalsolder protrusion directions 5 d agree with the diagonal directions (oblique direction) of solder bumps 5. In this case, a space between bumps can be additionally provided and this structure is preferable. -
FIG. 25 andFIG. 26 illustrate examples of isolated lands like signal bumps. In the second modification to the second embodiment illustrated inFIG. 25 , theshortest parts 2 g inelectrodes 2 c for flip chip bonding as isolated lands are arranged in such positions that their respectivesolder protrusion directions 5 d differ from one another between the bumps. - In the third modification to the second embodiment illustrated in
FIG. 26 , theshortest parts 2 g inelectrodes 2 c for flip chip bonding as isolated lands are arranged in positions where their respectivesolder protrusion directions 5 d are identical between the bumps. The structure inFIG. 26 makes it possible to provide solder with a tendency to protrude in the longest-pitch direction. - According to the semiconductor device in the second embodiment including the first modification to the third modification, as mentioned above, the following
shortest parts 2 g are placed in positions where they are not opposed to each other between bumps: the shortest parts where the distance between the following patterns is shortest: theouter shape pattern 2 f of anelectrode 2 c for flip chip bonding in thewiring board 2 as viewed in a place and theopening pattern 2 d for theelectrode 2 c for flip chip bonding in the solder resistfilm 2 e as viewed in a plane. This makes it possible to reduce the production of a solder bridge between adjacent bumps during flip chip bonding. - As a result, it is possible to enhance the joint reliability in flip chip bonding of a semiconductor device.
- Up to this point, concrete description has been given to the invention made by the present inventors based on embodiments of the invention. However, the invention is not limited to the above embodiments and can be variously modified without departing from the subject matter thereof, needless to add.
- Some examples will be taken. In the description of the second embodiment, a means for reducing the production of a solder bridge by lands (
electrodes 2 c for flip chip bonding) on the substrate side has been taken as an example. Instead, the means in the second embodiment can also be applied to lands (electrode pads 4 c) on the chip side. - The technology in which
flux 9 is applied tosolder bumps 5 a on the substrate side and then the reflow/cleaning (flux cleaning) is carried out before flip chip bonding is carried out has been described in relation to the first embodiment. This technology may be applied tosolder bumps 5 b on the chip side and even in this case, the same effects as in cases where it is applied tosolder bumps 5 a on the substrate side can be obtained. - The following technologies may be combined or may be singly adopted: the technology for the assembly of a semiconductor device described in relation to the first embodiment and illustrated in
FIG. 2 toFIG. 4 ; the technologies in the first modification to the fourth modification thereto; the technology related to the structure of a semiconductor device described in relation to the second embodiment; and the technologies in the first modification to the third modification to the second embodiment. - The invention is favorably applicable to the assembly of an electronic device using flip chip bonding.
Claims (16)
1. A semiconductor device comprising:
a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having a plurality of electrodes for flip chip bonding formed in the upper surface;
a semiconductor chip placed over the upper surface of the wiring board by flip chip bonding;
a plurality of external terminals provided in the lower surface of the wiring board,
wherein shortest parts where the distance between the outer shape pattern of the electrode for flip chip bonding as viewed in a plane and the bump placement portion pattern for the electrode for flip chip bonding as viewed in a plane is shortest between adjacent bumps for the flip chip bonding are arranged in such positions where the shortest parts are not opposed to each other between the bumps.
2. The semiconductor device of claim 1 ,
wherein the shortest parts are arranged in such positions that the directions of the respective solder protrusions thereof are identical between the bumps.
3. The semiconductor device of claim 1 ,
wherein the shortest parts are arranged in such positions that the directions of the respective solder protrusions thereof differ from one another between the bumps.
4. A manufacturing method for a semiconductor device, comprising the steps of:
(a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having a plurality of electrodes for flip chip bonding formed in the upper surface;
(b) preparing a semiconductor chip having each of plurality of bump electrodes formed over an electrode pad;
(c) forming a solder ball over each of the electrodes for flip chip bonding of the wiring board;
(d) after the step (c), applying flux to the solder balls and then carrying out reflow/cleaning on the solder balls; and
(e) flip chip bonding together the bump electrodes of the semiconductor chip and the solder balls of the wiring board.
5. The manufacturing method for a semiconductor device of claim 4 ,
wherein at the step (c), solder paste is applied to the electrodes for flip chip bonding and then reflow/cleaning is carried out to form the solder balls.
6. The manufacturing method for a semiconductor device of claim 4 ,
wherein when the flip chip bonding is carried out at the step (e), at least any one of the bump electrodes on the chip side and the solder balls on the substrate side is melted before bonding.
7. The manufacturing method for a semiconductor device of claim 4 ,
wherein electronic components are solder mounted around the semiconductor chip in the upper surface of the wiring board.
8. The manufacturing method for a semiconductor device of claim 4 ,
wherein when the flip chip bonding is carried out at the step (e), the flip chip bonding is carried out by pressing the semiconductor chip into the wiring board by two-staged pressing, first pressing and second pressing after the first pressing.
9. The manufacturing method for a semiconductor device of claim 8 ,
wherein the pressing amount in the first pressing is smaller than the pressing amount in the second pressing.
10. A manufacturing method for a semiconductor device, comprising the steps of:
(a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having a plurality of electrodes for flip chip bonding formed in the upper surface;
(b) preparing a semiconductor chip having each of a plurality of bump electrodes formed over an electrode pad;
(c) applying flux paste to each of the electrodes for flip chip bonding of the wiring board;
(d) placing a solder ball over the flux paste over each of the electrodes for flip chip bonding;
(e) after the step (d), carrying out reflow/cleaning on the solder balls; and
(f) flip chip bonding together the bump electrodes of the semiconductor chip and the solder balls of the wiring board.
11. The manufacturing method for a semiconductor device of claim 10 ,
wherein when the flip chip bonding is carried out at the step (f), at least any one of the bump electrodes on the chip side and the solder balls on the substrate side is melted before bonding.
12. The manufacturing method for a semiconductor device of claim 10 ,
wherein electronic components are solder mounted around the semiconductor chip in the upper surface of the wiring board.
13. The manufacturing method for a semiconductor device of claim 10 ,
wherein when the flip chip bonding is carried out at the step (f), the flip chip bonding is carried out by pressing the semiconductor chip into the wiring board by two-staged pressing, first pressing and second pressing after the first pressing.
14. The manufacturing method for a semiconductor device of claim 13 ,
wherein the pressing amount in the first pressing is smaller than the pressing amount in the second pressing.
15. A manufacturing method for a semiconductor device, comprising the steps of:
(a) preparing a wiring board having an upper surface and a lower surface located on the opposite side to the upper surface and having a solder ball formed over a plurality of electrodes for flip chip bonding in the upper surface;
(b) preparing a semiconductor chip having each of a plurality of bump electrodes formed over an electrode pad; and
(c) flip chip bonding together the bump electrodes of the semiconductor chip and the solder balls of the wiring board,
wherein when the flip chip bonding is carried out at the step (c), the flip chip bonding is carried out by pressing the semiconductor chip into the wiring board by two-staged pressing, first pressing and second pressing after the first pressing.
16. The manufacturing method for a semiconductor device of claim 15 ,
wherein the pressing amount in the first pressing is smaller than the pressing amount in the second pressing.
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US15/375,072 US10037966B2 (en) | 2010-10-21 | 2016-12-09 | Semiconductor device and manufacturing method therefor |
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JP2010-236213 | 2010-10-21 | ||
JP2010236213A JP5645592B2 (en) | 2010-10-21 | 2010-10-21 | Manufacturing method of semiconductor device |
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US15/375,072 Active US10037966B2 (en) | 2010-10-21 | 2016-12-09 | Semiconductor device and manufacturing method therefor |
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US15/375,072 Active US10037966B2 (en) | 2010-10-21 | 2016-12-09 | Semiconductor device and manufacturing method therefor |
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US20150048504A1 (en) * | 2013-08-19 | 2015-02-19 | Ambit Microsystems (Zhongshan) Ltd. | Package assembly for chip and method of manufacturing same |
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US20170103963A1 (en) * | 2015-10-09 | 2017-04-13 | International Business Machines Corporation | Micro-scrub process for fluxless micro-bump bonding |
US20180076169A1 (en) * | 2016-09-13 | 2018-03-15 | Rodan (Taiwan) Ltd. | Chip bonding process |
US20180320029A1 (en) * | 2015-11-04 | 2018-11-08 | Lintec Corporation | Curable resin film and first protective film forming sheet |
TWI737312B (en) * | 2019-04-18 | 2021-08-21 | 台灣積體電路製造股份有限公司 | Reflow apparatus and bonding method |
US11370047B2 (en) * | 2013-05-16 | 2022-06-28 | Sony Semiconductor Solutions Corporation | Method of manufacturing mounting substrate and method of manufacturing electronic apparatus |
US11404365B2 (en) * | 2019-05-07 | 2022-08-02 | International Business Machines Corporation | Direct attachment of capacitors to flip chip dies |
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Also Published As
Publication number | Publication date |
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JP5645592B2 (en) | 2014-12-24 |
US10037966B2 (en) | 2018-07-31 |
JP2012089724A (en) | 2012-05-10 |
US20170092614A1 (en) | 2017-03-30 |
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