US20110139192A1 - Surface treatment apparatus and method for semiconductor substrate - Google Patents

Surface treatment apparatus and method for semiconductor substrate Download PDF

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Publication number
US20110139192A1
US20110139192A1 US12/887,332 US88733210A US2011139192A1 US 20110139192 A1 US20110139192 A1 US 20110139192A1 US 88733210 A US88733210 A US 88733210A US 2011139192 A1 US2011139192 A1 US 2011139192A1
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Prior art keywords
semiconductor substrate
supply unit
convex pattern
unit
water
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Abandoned
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US12/887,332
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English (en)
Inventor
Tatsuhiko Koide
Shinsuke Kimura
Yoshihiro Ogawa
Hisashi Okuchi
Hiroshi Tomita
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Toshiba Corp
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Individual
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TOMITA, HIROSHI, OKUCHI, HISASHI, KIMURA, SHINSUKE, KOIDE, TATSUHIKO, OGAWA, YOSHIHIRO
Publication of US20110139192A1 publication Critical patent/US20110139192A1/en
Priority to US14/836,881 priority Critical patent/US10573508B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like

Definitions

  • Embodiments described herein relate generally to a surface treatment apparatus and a surface treatment method for a semiconductor substrate.
  • the process of manufacturing a semiconductor device includes various processes, such as a lithography process, an etching process and an ion implantation process. After completion of each process, a cleaning process and a drying process for removing impurities and residues remaining on a wafer surface to clean the wafer surface are performed before the transfer to the next process.
  • a chemical for the cleaning treatment is supplied onto the surface of the wafer, and then pure water is supplied to perform rinsing. After the rinsing, drying is performed which removes the pure water remaining on the wafer surface and dries the wafer.
  • IPA isopropyl alcohol
  • HFE hydrofluoroether
  • FIG. 1 is a diagram showing a schematic configuration of a surface treatment apparatus of a semiconductor substrate according to a first embodiment of the present invention
  • FIG. 2 is a flowchart explaining a surface treatment method of a semiconductor substrate according to the first embodiment
  • FIG. 3 is a view showing a surface tension of liquid to the pattern
  • FIG. 4A is a view showing a state of a pattern after a drying process in case where a water repellent protective film is not formed;
  • FIG. 4B is a view showing a state of a pattern after a drying process in case where a water repellent protective film is formed
  • FIG. 5 is a diagram showing a schematic configuration of a surface treatment apparatus of a semiconductor substrate according to a second embodiment of the present invention.
  • FIG. 6 is a flowchart explaining a surface treatment method of a semiconductor substrate according to the second embodiment
  • FIG. 7 is a diagram showing a schematic configuration of a surface treatment apparatus of a semiconductor substrate according to a third embodiment of the present invention.
  • FIG. 8 is a flowchart explaining a surface treatment method of a semiconductor substrate according to the third embodiment.
  • FIG. 9 is a schematic constitutional view of a water repelling film removal unit provided in a surface treatment apparatus for a semiconductor substrate according to a fourth embodiment of the present invention.
  • FIG. 10 is a flowchart explaining a surface treatment method of a semiconductor substrate according to the fourth embodiment.
  • FIG. 11A is a sectional view explaining a surface treatment method for a semiconductor substrate according to a modification
  • FIG. 11B is a sectional view showing a step subsequent to FIG. 11A ;
  • FIG. 11C is a sectional view showing a step subsequent to FIG. 11B ;
  • FIG. 11D is a sectional view showing a step subsequent to FIG. 11C ;
  • FIG. 12A is a sectional view showing a step subsequent to FIG. 11D ;
  • FIG. 12B is a sectional view showing a step subsequent to FIG. 12A ;
  • FIG. 12C is a sectional view showing a step subsequent to FIG. 12B ;
  • FIG. 13A is a sectional view showing a side-wall transfer process
  • FIG. 13B is a sectional view showing a step subsequent to FIG. 13A ;
  • FIG. 13C is a sectional view showing a step subsequent to FIG. 13B ;
  • FIG. 13D is a sectional view showing a step subsequent to FIG. 13C ;
  • FIG. 14A is a sectional view showing a step subsequent to FIG. 13D ;
  • FIG. 14B is a sectional view showing a step subsequent to FIG. 14A ;
  • FIG. 14C is a sectional view showing a step subsequent to FIG. 14B ;
  • FIG. 15A is a view showing a surface tension of liquid to the pattern.
  • FIG. 15B is a view showing a configuration in which the whole pattern is tilted.
  • a surface treatment apparatus for a semiconductor substrate includes a holding unit, a first supply unit, a second supply unit, a third supply unit, a drying treatment unit, and a removal unit.
  • the holding unit holds a semiconductor substrate with a surface having a convex pattern formed thereon.
  • the first supply unit supplies a chemical solution to the surface of the semiconductor substrate, to perform cleaning and oxidation.
  • the second supply unit supplies pure water to the surface of the semiconductor substrate, to rinse the semiconductor substrate.
  • the third supply unit supplies a water repelling agent to the surface of the semiconductor substrate, to form a water repellent protective film on the surface of the convex pattern.
  • the drying treatment unit dries the semiconductor substrate.
  • the removal unit removes the water repellent protective film while making the convex pattern remain.
  • the cleaning process has an important role of forming a clean semiconductor wafer surface after cleaning without generating any defect (missing pattern, scratch, thinned pattern, dug substrate, or the like) in a fine pattern structure formed on the semiconductor substrate.
  • any defect missing pattern, scratch, thinned pattern, dug substrate, or the like
  • cleanliness demanded in the cleaning process becomes higher.
  • FIG. 1 shows a schematic configuration of a surface treatment apparatus for a semiconductor substrate according to a first embodiment of the present invention.
  • the surface treatment apparatus includes a treatment bath 101 , a carrier unit 102 , a chemical solution supply unit 103 , a pure water supply unit 104 , an IPA supply unit 105 , a water repelling agent supply unit 106 , a gas supply unit 107 , and a water repelling film removal unit 108 .
  • This surface treatment apparatus is a batch type apparatus that washes and dries a plurality of semiconductor substrates in block.
  • the carrier unit 102 holds and carries a semiconductor substrate W on the surface of which a convex pattern is formed.
  • the carrier unit 102 introduces the semiconductor substrate W into the treatment bath 101 , and carries the semiconductor substrate W to the water repelling film removal unit 108 .
  • the chemical solution supply unit 103 supplies the treatment bath 101 with a chemical solution for washing the semiconductor substrate W.
  • the chemical solution supply unit 103 supplies a highly oxidative chemical solution, such as a solution obtained by increasing a temperature of a mixed solution (SPM) of sulfuric acid and hydrogen peroxide to 80° C. or higher, or sulfuric acid.
  • the chemical solution supply unit 103 may be provided with a heating mechanism (e.g. heater, etc.) for increasing a temperature of the chemical solution.
  • the IPA supply unit 105 supplies the treatment bath 101 with IPA (isopropyl alcohol) for rinsing the semiconductor substrate W.
  • the gas supply unit (drying treatment unit) 107 can supply dry air so as to dry the semiconductor substrate W.
  • the treatment bath 101 can reserve and discharge a liquid supplied from the chemical solution supply unit 103 , the pure water supply unit 104 , the IPA supply unit 105 , the water repelling agent supply unit 106 , or the like.
  • the treatment bath 101 is preferably made up of a Teflon (registered trademark)-based material in order to be capable of treating the highly oxidative chemical solution supplied from the chemical solution supply unit 103 .
  • the water repelling film removal unit 108 can remove the water repellent protective film formed on the convex pattern surface on the semiconductor substrate W, and for example, a dry ashing, ozone-gas treatment, UV light irradiation, or the like is performed.
  • Step S 101 The carrier unit 102 introduces the semiconductor substrate W processed with the convex pattern into the treatment bath 101 .
  • This convex pattern is, for example, a line-and-space pattern.
  • the convex pattern is, for example, a high aspect ratio structure having an aspect ratio of 10 or more.
  • the convex pattern is formed, for example, by RIE (Reactive Ion Etching) method.
  • Step S 102 A highly oxidative chemical solution is supplied from the chemical solution supply unit 103 to the treatment bath 101 , and the semiconductor substrate W is washed. Thereby, a residue generated due to the processing of the convex pattern on the semiconductor substrate W can be removed, and also, the surface can be oxidized.
  • Step S 106 IPA is supplied from the IPA supply unit 105 to the treatment bath 101 , and the silane coupling agent is replaced by IPA.
  • Step S 107 Pure water is supplied from the pure water supply unit 104 to the treatment bath 101 , and an IPA residue is rinsed off.
  • Step S 108 The carrier unit 102 pulls up the semiconductor substrate W from the treatment bath 101 , and the gas supply unit 107 supplies the semiconductor substrate W with dry air for evaporation-drying.
  • FIG. 3 shows a state where a part of patterns 4 formed on the semiconductor substrate W is wet with a liquid 5 .
  • power P that is applied to the pattern 4 is:
  • Step S 109 The carrier unit 102 carries the semiconductor substrate W to the water repelling film removal unit 108 .
  • the water repelling film removal unit 108 removes the water repellent protective film formed on the convex pattern surface on the semiconductor substrate W while making the convex pattern remain.
  • FIG. 4A shows states of the pattern after the drying treatment in the case of not forming the water repellent protective film
  • FIG. 4B shows states of the pattern after the drying treatment in the case of forming the water repellent protective film as thus described.
  • Surface treatment was performed on patterns with three kinds of line heights: 150 nm, 170 nm and 200 nm, and three kinds of pattern widths: normal, fine and extra-fine (normal>fine>extra-fine).
  • pattern collapse occurred in the pattern with the extra-fine line width and the line heights of any of 150 nm, 170 nm and 200 nm. Further, the pattern collapse also occurred in the pattern with the fine line width and the 200-nm line height.
  • forming (and forcibly oxidizing) the semiconductor substrate surface with use of the highly oxidative chemical solution and then forming the water repellent protective film on the substrate surface can prevent collapse of the extra-fine pattern at the time of the drying treatment.
  • FIG. 5 shows a schematic configuration of a surface treatment apparatus for a semiconductor substrate according to a second embodiment of the present invention.
  • the surface treatment apparatus includes a substrate holding/rotation unit 200 , a chemical solution supply unit 210 , a pure water supply unit 211 , an IPA supply unit 212 , a water repelling agent supply unit 213 , and a water repelling film removal unit 214 .
  • This surface treatment apparatus is a single type apparatus that supplies a semiconductor substrate with a treatment solution, to treat the substrate on a one-by-one basis.
  • the substrate holding/rotation unit 200 has a spin cup 201 , which constitutes a process chamber, a rotation axis 202 , a spin base 203 , and a chuck pin 204 .
  • the rotation axis 202 extends in a substantially vertical direction, and the spin base 203 in disc shape is mounted on the top of the rotation axis 202 .
  • the rotation axis 202 and the spin base 203 can be rotated by a motor not shown in the figure.
  • the chuck pin 204 is provided around the edge of the spin base 203 .
  • the substrate holding/rotation unit 200 can rotate the substrate W while holding it almost horizontally
  • the liquid expands in a radial direction of semiconductor the substrate W to the vicinity of the rotational center of the substrate W. Further, the substrate holding/rotation unit 200 can perform spin-drying on the semiconductor substrate W. An extra liquid scattered in the radial direction of the substrate W is captured in the spin cup 201 , and discharged through a waste tube 205 .
  • the chemical solution supply unit 210 supplies the semiconductor substrate W held in the substrate holding/rotation unit 200 with a chemical solution for washing the semiconductor substrate W.
  • the chemical solution supply unit 210 supplies a highly oxidative chemical solution, such as a solution obtained by heating a temperature of a mixed solution (SPM) of sulfuric acid and hydrogen peroxide to 80 (C or higher, or sulfuric acid.
  • SPM mixed solution
  • the pure water supply unit 211 supplies the semiconductor substrate W held in the substrate holding/rotation unit 200 with pure water for rinsing the semiconductor substrate W.
  • the IPA supply unit 212 supplies the semiconductor substrate W held in the substrate holding/rotation unit 200 with IPA for rinsing the semiconductor substrate W.
  • the water repelling agent supply unit 213 supplies the semiconductor substrate W held in the substrate holding/rotation unit 200 with a water repelling agent.
  • the water repelling agent is a chemical solution that forms a water repellent protective film on the surface of a convex pattern, formed on the surface of the semiconductor substrate W, to make the pattern surface water repellent, and for example, hexamethyldisilazane (HMDS), tetramethyl silyl diethylamine (TMSDEA), or the like can be applied.
  • HMDS hexamethyldisilazane
  • TMSDEA tetramethyl silyl diethylamine
  • the water repelling film removal unit 214 can remove the water repellent protective film while making the convex pattern remain.
  • the water repelling film removal unit 214 removes the water repellent protective film, for example, by UV-light irradiation.
  • the water repelling film removal unit 214 is provided above the substrate holding/rotation unit 200 , and is vertically movable.
  • a carrier unit 215 carries the semiconductor substrate W to the substrate holding/rotation unit 200 .
  • a method for performing surface treatment on a semiconductor substrate with use of such a surface treatment apparatus will be described using a flowchart shown in FIG. 6 . It is to be noted that operations of the substrate holding/rotation unit 200 , the chemical solution supply unit 210 , the pure water supply unit 211 , the IPA supply unit 212 , the water repelling agent supply unit 213 and the water repelling film removal unit 214 can be controlled by a controlling unit not shown in the figure.
  • Step S 201 A semiconductor substrate W to be treated, having a plurality of convex patterns in a predetermined area of its surface, is carried by the carrier unit (not shown), and held in the substrate holding/rotation unit 200 .
  • the convex pattern is, for example, a line-and-space pattern. At least part of the convex pattern may be formed by a silicon-containing film.
  • the convex pattern is formed, for example, by RIE (Reactive Ion Etching) method.
  • Step S 202 The semiconductor substrate W is rotated at a predetermined rotational speed, and the chemical solution is supplied from the chemical solution supply unit 210 to the vicinity of the rotational center of the semiconductor substrate W surface.
  • the chemical solution is a highly oxidative chemical solution.
  • the chemical solution Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the chemical solution reaches all parts of the semiconductor substrate W surface, and chemical-solution (washing) treatment is performed on the semiconductor substrate W.
  • Step S 203 Pure water is supplied from the pure water supply unit 211 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the pure water reaches all parts of the semiconductor substrate W surface. Thereby, pure-water rinsing treatment is performed in which the chemical solution remaining on the semiconductor substrate W surface is rinsed off by the pure water. This can remove the processing residue and oxidize the substrate surface.
  • Step S 204 Alcohol such as IPA is supplied from the IPA supply unit 212 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, IPA reaches all parts of the semiconductor substrate W surface. Thereby, alcohol rinsing treatment is performed in which the pure water remaining on the semiconductor substrate W surface is replaced by IPA.
  • Step S 205 A water repelling agent is supplied from the water repelling agent supply unit 213 to the vicinity of the rotational center of the semiconductor substrate W surface.
  • the water repelling agent is, for example, a silane coupling agent.
  • the silane coupling agent Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the silane coupling agent reaches all parts of the semiconductor substrate W surface. Thereby, a protective film with low wettability (water repellent protective film) is formed on the convex pattern surface.
  • This water repellent protective film is formed by generation of an ester-reaction of the silane coupling agent.
  • the number of OH groups on the semiconductor substrate W (convex pattern) is large.
  • Step S 206 Alcohol such as IPA is supplied from the IPA supply unit 212 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, IPA reaches all parts of the semiconductor substrate W surface. Thereby, alcohol rinsing treatment is performed in which the silane coupling agent remaining on the semiconductor substrate W surface is replaced by IPA.
  • Step S 207 Pure water is supplied from the pure water supply unit 211 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the pure water reaches all parts of the semiconductor substrate W surface. Thereby, pure-water rinsing treatment is performed in which the pure water remaining on the semiconductor substrate W surface is replaced by IPA.
  • Step S 208 The substrate holding/rotation unit 200 increases the rotational speed of the semiconductor substrate W to a predetermined spin dry rotational speed, to perform spin dry treatment in which the pure water remaining on the semiconductor substrate W surface is spun off and dried.
  • forming the semiconductor substrate surface with use of the highly oxidative chemical solution and then forming the water repellent protective film on the substrate surface can prevent collapse of the extra-fine pattern at the time of the drying treatment.
  • the number of OH groups on the semiconductor substrate W is increased by the washing treatment with use of the highly oxidative chemical solution in the above first embodiment, it may be increased by irradiating the substrate surface with UV light after being washed with a normal washing chemical solution to further oxidize the substrate surface.
  • FIG. 8 A method for performing surface treatment on a semiconductor substrate with use of such a surface treatment apparatus will be described using a flowchart shown in FIG. 8 .
  • Step S 302 A chemical solution is supplied from the chemical solution supply unit 103 to the treatment bath 101 , and the semiconductor substrate W is washed. Thereby, a residue generated due to the processing of the convex pattern on the semiconductor substrate W can be removed.
  • Step S 306 A silane coupling agent is supplied from the water repelling agent supply unit 106 to the treatment bath 101 , and a protective film with low wettability (water repellent protective film) is formed on the semiconductor substrate W (convex pattern) surface.
  • the number of OH groups on the semiconductor substrate W (convex pattern) is large.
  • Step S 307 IPA is supplied from the IPA supply unit 105 to the treatment bath 101 , and the silane coupling agent is replaced by IPA.
  • Step S 310 The carrier unit 102 carries the semiconductor substrate W to the water repelling film removal unit 108 .
  • the water repelling film removal unit 108 removes the water repellent protective film formed on the convex pattern surface on the semiconductor substrate W while making the convex pattern remain.
  • the number of OH groups on the semiconductor substrate W is increased by the washing treatment with use of the highly oxidative chemical solution in the above second embodiment, it may be increased by irradiating the substrate surface with UV light after being washed with a normal washing chemical solution to further oxidize the substrate surface.
  • the water repelling film removal unit 214 performs UV-light irradiation.
  • the surface treatment apparatus according to the present embodiment has a similar configuration to that of the surface treatment apparatus according to the above second embodiment shown in FIG. 5 .
  • the water repelling film removal unit 214 needs the semiconductor substrate W surface to be in a wet state at the time of irradiation of the substrate surface with UV light for oxidization. Therefore, as shown in FIG. 9 , the water repelling film removal unit 214 includes an outlet 214 a for discharging pure water.
  • the chemical solution supply unit 210 supplies a normal washing chemical solution, such as SPM, SC-1 (Standard Clean 1), or SC-2.
  • the chemical solution supply unit 210 may supply one kind of chemical solution, or may supply a plurality of chemical solutions simultaneously or sequentially.
  • a method for performing surface treatment on a semiconductor substrate with use of the surface treatment apparatus according to the present embodiment will be described using a flowchart shown in FIG. 10 .
  • Step S 402 The semiconductor substrate W is rotated at a predetermined rotational speed, and the chemical solution is supplied from the chemical solution supply unit 210 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the chemical solution reaches all parts of the semiconductor substrate W surface, and chemical-solution (washing) treatment is performed on the semiconductor substrate W. It is possible by this treatment to remove a residue generated by processing of the convex pattern on the semiconductor substrate W.
  • Step S 403 Pure water is supplied from the pure water supply unit 211 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the pure water reaches all parts of the semiconductor substrate W surface. Thereby, pure-water rinsing treatment is performed in which the chemical solution remaining on the semiconductor substrate W surface is rinsed off by the pure water.
  • Step S 404 The water repelling film removal unit 214 moves down, and irradiates the semiconductor substrate W surface with UV light while discharging pure water. Thereby, the substrate surface is further oxidized.
  • Step S 405 Alcohol such as IPA is supplied from the IPA supply unit 212 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, IPA reaches all parts of the semiconductor substrate W surface. Thereby, alcohol rinsing treatment is performed in which the pure water remaining on the semiconductor substrate W surface is replaced by IPA.
  • Step S 406 A water repelling agent is supplied from the water repelling agent supply unit 213 to the vicinity of the rotational center of the semiconductor substrate W surface.
  • the water repelling agent is, for example, a silane coupling agent.
  • the silane coupling agent Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the silane coupling agent reaches all parts of the semiconductor substrate W surface. Thereby, a protective film with low wettability (water repellent protective film) is formed on the convex pattern surface.
  • This water repellent protective film is formed by generation of an ester-reaction of the silane coupling agent.
  • the number of OH groups on the semiconductor substrate W (convex pattern) is large.
  • Step S 407 Alcohol such as IPA is supplied from the IPA supply unit 212 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, IPA reaches all parts of the semiconductor substrate W surface. Thereby, alcohol rinsing treatment is performed in which the silane coupling agent remaining on the semiconductor substrate W surface is replaced by IPA.
  • Step S 408 Pure water is supplied from the pure water supply unit 211 to the vicinity of the rotational center of the semiconductor substrate W surface. Upon receipt of centrifugal force generated by rotation of the semiconductor substrate W, the pure water reaches all parts of the semiconductor substrate W surface. Thereby, pure-water rinsing treatment is performed in which the pure water remaining on the semiconductor substrate W surface is replaced by IPA.
  • Step S 409 The substrate holding/rotation unit 200 increases the rotational speed of the semiconductor substrate W to a predetermined spin dry rotational speed, to perform spin dry treatment in which the pure water remaining on the semiconductor substrate W surface is spun off and dried.
  • Step S 410 The water repelling film removal unit 214 moves down to the vicinity of the semiconductor substrate W. Then, the water repelling film removal unit 214 irradiates the semiconductor substrate W with UV light, to remove the water repellent protective film formed on the convex pattern surface on the semiconductor substrate W while making the convex pattern remain.
  • Performing the surface treatment on a semiconductor substrate according to the present embodiment also makes it possible to obtain a similar effect to the effect of the above first embodiment (cf. FIG. 4 ).
  • irradiating the semiconductor substrate surface with UV light to promote an oxidation reaction and then forming the water repellent protective film on the substrate surface can prevent collapse of the extra-fine pattern at the time of the drying treatment.
  • thinner treatment may be performed to replace IPA by a thinner not containing a hydroxyl group.
  • the thinner used can be a solvent having no hydroxyl group in a compound itself, such as toluene, a solvent that does not generate a hydroxyl group as an intermediate product, or cyclohexanone.
  • the thinner is replaceable by water, the IPA replacement (alcohol rinsing) after the pure-water rinsing may be omitted.
  • a surfactant aqueous surfactant
  • the IPA replacement alcohol rinsing before and after the water repelling treatment can be omitted, thereby eliminating the need to provide the IPA supply units 105 , 212 in the surface treatment apparatus.
  • each of the surface treatment apparatuses according to the first and third embodiments is an overflow type apparatus using a single treatment bath
  • a plurality of treatment baths respectively reserving a chemical solution, pure water, a water repelling agent, and the like may be provided, and the substrate holding/carrier unit 102 may sequentially soak the semiconductor substrate in the respective baths.
  • the water repelling film removal unit may be provided in each of the plurality of substrate holding/rotation units 200 , or one water repelling film removal unit may be made movable above the plurality of substrate holding/rotation units 200 .
  • Ultraviolet-light irradiation for oxidizing the semiconductor substrate W surface may be performed in the middle of the convex pattern processing.
  • FIGS. 11A , 11 B, 11 C, 11 D, 12 A, 12 B, 12 C show an example of such a surface treatment method.
  • a silicon-based member layer 11 is sequentially formed on the semiconductor substrate W.
  • the silicon-based member layer 11 is formed using silicon oxide, polysilicon or the like.
  • the silicon-based member layer 11 may be made up of a plurality of films.
  • a resist layer 14 having a line-and-space pattern is formed on the silicon oxide film 13 by means of a photolithography technique.
  • the resist layer 14 is peeled.
  • dry etching is conducted, to pattern the silicon nitride film 12 .
  • the silicon-based member layer 11 under the silicon nitride film 12 is not processed. Washing is then performed using a chemical solution such as SC-1, SC-2 or SPM, to remove a residue generated due to the dry etching.
  • UV-light irradiation is performed. Therewith, oxidation proceeds on the surface of the silicon oxide film 13 , the side faces of the silicon nitride film 12 , and the like. It is to be noted that the silicon oxide film 13 may be removed before the UV-light irradiation.
  • the surface treatment method according to the above third and fourth embodiments (except for Steps S 304 , S 404 ) are applied.
  • the side faces of the silicon nitride film 12 has been forcibly oxidized by the UV-light irradiation, thereby to facilitate formation of the water repellent protective film and improve a water repellency, thus making it possible to prevent collapse of the extra-fine pattern at the time of the drying treatment.
  • Each of the surface treatment apparatuses in the above first to fourth embodiments is suitable for washing/drying of a semiconductor substrate having a convex pattern formed by side-wall transfer process.
  • the side-wall transfer process is performed in such a manner that, as shown in FIG. 13A , first, a second film 502 is formed on a first film 501 formed on a semiconductor substrate (not shown).
  • a resist 503 having a line-and-space pattern is then formed on the second film 502 .
  • the second film 502 is etched using the resist 503 as a mask, to transfer the pattern.
  • the second film 502 is subjected to slimming treatment, to be reduced in width by the order of one half so as to be processed into core members 504 .
  • the resist 503 is removed before or after the slimming treatment.
  • the slimming treatment is preformed by wetting treatment or drying treatment, or in combination of the wetting treatment and the drying treatment.
  • a third member 505 is formed so as to cover the upper faces and the side faces of the core members 504 by means of CVD (Chemical Vapor Deposition), or the like.
  • the third member 505 is formed of a material capable of taking a large etching selection ratio with respect to the core member 504 .
  • the third member 505 is dry-etched until the upper face of the core member 504 is exposed. Dry-etching is performed on an etching condition having selectivity with respect to the core member 504 . Thereby, the third member 505 remains in the shape of a spacer along the side faces of the core member 504 . In the third member 505 that remains at this time, a top end 505 a is located in contact with the top of the side face of the core member 504 , and an upper side part takes a shape projectingly curved toward the outside of the core member 504 .
  • the core member 504 is removed by wet etching treatment.
  • the third member 505 is formed in an asymmetric shape where spaces with a distance between the tops of adjacent two patterns (opening width size of the space pattern) being small and spaces with the distance being large are alternately present.
  • the force P applied to the pattern 4 depends on a vertical component of the surface tension ⁇ . Therefore, as shown in FIG. 15A , by making a structure such that the top of the pattern is inclined, namely an angle formed by the side face of the top of the pattern with respect to the substrate surface is different from an angle formed by the side face of the bottom of the pattern with respect to the substrate surface, it is possible to make the vertical component of the surface tension ⁇ small, so as to reduce the force applied to the pattern.
  • Such a structure can be formed by making a temperature low at the time of performing RIE treatment on the pattern. Further, as shown in FIG. 15B , in a case where the pattern is configured of a mask material 1501 and a pattern material 1502 , a similar configuration can be obtained by performing RIE treatment on the condition of a selectivity between the mask material 1501 and the pattern material 1502 being low or on the condition of the selectivity being the same.

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110186088A1 (en) * 2010-01-31 2011-08-04 Miller Kenneth C Substrate nest with drip remover
US8399357B2 (en) 2010-10-06 2013-03-19 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US8772164B2 (en) 2011-12-15 2014-07-08 Kabushiki Kaisha Toshiba Method for forming interconnection pattern and semiconductor device
US20140213064A1 (en) * 2013-01-25 2014-07-31 Kabushiki Kaisha Toshiba Semiconductor manufacturing apparatus and manufacturing method of semiconductor device
IT201900002485A1 (it) * 2019-02-20 2020-08-20 Protim S R L Procedimento di rivestimento di pezzi
CN113394074A (zh) * 2020-03-11 2021-09-14 长鑫存储技术有限公司 半导体结构的处理方法
US20230098810A1 (en) * 2021-09-24 2023-03-30 SCREEN Holdings Co., Ltd. Substrate processing method and substrate processing apparatus

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6770887B2 (ja) 2016-12-28 2020-10-21 株式会社Ｓｃｒｅｅｎホールディングス 基板処理装置および基板処理システム
WO2020004047A1 (ja) * 2018-06-27 2020-01-02 東京エレクトロン株式会社 基板洗浄方法、基板洗浄システムおよび記憶媒体
US11094527B2 (en) 2018-10-10 2021-08-17 International Business Machines Corporation Wet clean solutions to prevent pattern collapse

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767789A (en) * 1995-08-31 1998-06-16 International Business Machines Corporation Communication channels through electrically conducting enclosures via frequency selective windows
US6698439B2 (en) * 2000-07-03 2004-03-02 Tokyo Electron Limited Processing apparatus with sealing mechanism
US20040211756A1 (en) * 2003-01-30 2004-10-28 Semiconductor Leading Edge Technologies, Inc. Wet etching apparatus and wet etching method using ultraviolet light
US20040226582A1 (en) * 2003-05-12 2004-11-18 Joya Satoshi Apparatus and method for substrate processing
US20050176254A1 (en) * 2004-01-15 2005-08-11 Tomoyuki Takeishi Pattern forming method and manufacturing method of semiconductor device
US20070077768A1 (en) * 2005-09-29 2007-04-05 Tokyo Electron Limited Substrate processing method
US20070111541A1 (en) * 2005-11-17 2007-05-17 Masayuki Endo Barrier film material and pattern formation method using the same
US20070295365A1 (en) * 2006-06-27 2007-12-27 Katsuhiko Miya Substrate processing method and substrate processing apparatus
US20080008973A1 (en) * 2006-07-10 2008-01-10 Tomohiro Goto Substrate processing method and substrate processing apparatus
US20080295868A1 (en) * 2007-06-04 2008-12-04 Hitachi Kokusai Electric Inc. Manufacturing method of a semiconductor device and substrate cleaning apparatus
US20090311874A1 (en) * 2008-06-16 2009-12-17 Hiroshi Tomita Method of treating surface of semiconductor substrate

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105683B2 (ja) 1992-04-23 1994-12-21 株式会社ソルテック レジストパターン形成方法
JPH05326464A (ja) * 1992-05-15 1993-12-10 Dainippon Screen Mfg Co Ltd 基板表面の気相洗浄方法
JPH07142349A (ja) 1993-11-16 1995-06-02 Mitsubishi Electric Corp 現像工程におけるフォトレジストパターンの倒れを防止する方法
JP2910546B2 (ja) * 1993-12-28 1999-06-23 日本電気株式会社 反射板の製造方法
JPH07273083A (ja) 1994-03-30 1995-10-20 Nippon Telegr & Teleph Corp <Ntt> 微細パターン形成法
US6451512B1 (en) * 2000-05-01 2002-09-17 Advanced Micro Devices, Inc. UV-enhanced silylation process to increase etch resistance of ultra thin resists
JP3866130B2 (ja) 2001-05-25 2007-01-10 大日本スクリーン製造株式会社 基板処理装置および基板処理方法
JP2005026265A (ja) 2003-06-30 2005-01-27 Nec Kansai Ltd クリーニング機構付きプローバ及びそのクリーニング方法
JP2005294789A (ja) * 2004-03-10 2005-10-20 Toshiba Corp 半導体装置及びその製造方法
US7585614B2 (en) * 2004-09-20 2009-09-08 International Business Machines Corporation Sub-lithographic imaging techniques and processes
JP4936659B2 (ja) * 2004-12-27 2012-05-23 株式会社東芝 半導体装置の製造方法
JP4612424B2 (ja) * 2005-01-12 2011-01-12 富士通セミコンダクター株式会社 基板処理方法および半導体装置の製造方法
JP4895256B2 (ja) 2005-02-23 2012-03-14 東京エレクトロン株式会社 基板の表面処理方法
JP5247999B2 (ja) * 2005-09-29 2013-07-24 東京エレクトロン株式会社 基板処理方法およびコンピュータ読取可能な記憶媒体
JP4866165B2 (ja) * 2006-07-10 2012-02-01 大日本スクリーン製造株式会社 基板の現像処理方法および基板の現像処理装置
US7851232B2 (en) * 2006-10-30 2010-12-14 Novellus Systems, Inc. UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
JP4818140B2 (ja) * 2007-01-31 2011-11-16 東京エレクトロン株式会社 基板の処理方法及び基板処理装置
JP4803821B2 (ja) * 2007-03-23 2011-10-26 大日本スクリーン製造株式会社 基板処理装置
JP2009088253A (ja) * 2007-09-28 2009-04-23 Toshiba Corp 微細構造体の製造方法および微細構造体の製造システム
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2009177069A (ja) 2008-01-28 2009-08-06 Toshiba Corp 半導体装置の製造方法
PL2149961T3 (pl) * 2008-07-30 2014-08-29 Askoll Holding Srl Sposób wytwarzania stojana silnika elektrycznego i silnika elektrycznego
US20100122711A1 (en) * 2008-11-14 2010-05-20 Advanced Micro Devices, Inc. wet clean method for semiconductor device fabrication processes

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767789A (en) * 1995-08-31 1998-06-16 International Business Machines Corporation Communication channels through electrically conducting enclosures via frequency selective windows
US6698439B2 (en) * 2000-07-03 2004-03-02 Tokyo Electron Limited Processing apparatus with sealing mechanism
US20040211756A1 (en) * 2003-01-30 2004-10-28 Semiconductor Leading Edge Technologies, Inc. Wet etching apparatus and wet etching method using ultraviolet light
US20040226582A1 (en) * 2003-05-12 2004-11-18 Joya Satoshi Apparatus and method for substrate processing
US20050176254A1 (en) * 2004-01-15 2005-08-11 Tomoyuki Takeishi Pattern forming method and manufacturing method of semiconductor device
US7482281B2 (en) * 2005-09-29 2009-01-27 Tokyo Electron Limited Substrate processing method
US20070077768A1 (en) * 2005-09-29 2007-04-05 Tokyo Electron Limited Substrate processing method
US20070111541A1 (en) * 2005-11-17 2007-05-17 Masayuki Endo Barrier film material and pattern formation method using the same
US20070295365A1 (en) * 2006-06-27 2007-12-27 Katsuhiko Miya Substrate processing method and substrate processing apparatus
US20080008973A1 (en) * 2006-07-10 2008-01-10 Tomohiro Goto Substrate processing method and substrate processing apparatus
US20080295868A1 (en) * 2007-06-04 2008-12-04 Hitachi Kokusai Electric Inc. Manufacturing method of a semiconductor device and substrate cleaning apparatus
US20090311874A1 (en) * 2008-06-16 2009-12-17 Hiroshi Tomita Method of treating surface of semiconductor substrate
US20100075504A1 (en) * 2008-06-16 2010-03-25 Hiroshi Tomita Method of treating a semiconductor substrate

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110186088A1 (en) * 2010-01-31 2011-08-04 Miller Kenneth C Substrate nest with drip remover
US8399357B2 (en) 2010-10-06 2013-03-19 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US8772164B2 (en) 2011-12-15 2014-07-08 Kabushiki Kaisha Toshiba Method for forming interconnection pattern and semiconductor device
US20140213064A1 (en) * 2013-01-25 2014-07-31 Kabushiki Kaisha Toshiba Semiconductor manufacturing apparatus and manufacturing method of semiconductor device
TWI557795B (zh) * 2013-01-25 2016-11-11 東芝股份有限公司 半導體製造設備及半導體裝置之製造方法
US11862484B2 (en) * 2013-01-25 2024-01-02 Kioxia Corporation Semiconductor manufacturing apparatus and manufacturing method of semiconductor device
IT201900002485A1 (it) * 2019-02-20 2020-08-20 Protim S R L Procedimento di rivestimento di pezzi
CN113394074A (zh) * 2020-03-11 2021-09-14 长鑫存储技术有限公司 半导体结构的处理方法
US20230098810A1 (en) * 2021-09-24 2023-03-30 SCREEN Holdings Co., Ltd. Substrate processing method and substrate processing apparatus
US11958087B2 (en) * 2021-09-24 2024-04-16 SCREEN Holdings Co., Ltd. Substrate processing method and substrate processing apparatus

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