US20100275995A1 - Bifacial solar cells with back surface reflector - Google Patents

Bifacial solar cells with back surface reflector Download PDF

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Publication number
US20100275995A1
US20100275995A1 US12/456,398 US45639809A US2010275995A1 US 20100275995 A1 US20100275995 A1 US 20100275995A1 US 45639809 A US45639809 A US 45639809A US 2010275995 A1 US2010275995 A1 US 2010275995A1
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Prior art keywords
back surface
layer
contact grid
front surface
depositing
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Martin Kaes
Peter Borden
Kamel Ounadjela
Andreas Kraenzl
Alain Blosse
Fritz G. Kirscht
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Silicor Materials Inc
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Silicor Materials Inc
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Assigned to CALISOLAR, INC. reassignment CALISOLAR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BLOSSE, ALAIN, OUNADJELA, KAMEL, BORDEN, PETER, KAES, MARTIN, KIRSCHT, FRITZ G., KRAENZL, ANDREAS
Priority to US12/456,398 priority Critical patent/US20100275995A1/en
Application filed by Silicor Materials Inc filed Critical Silicor Materials Inc
Priority to EP10770047.8A priority patent/EP2425457A4/en
Priority to JP2012508467A priority patent/JP2012525703A/ja
Priority to CN201080019116XA priority patent/CN102549765A/zh
Priority to PCT/US2010/001175 priority patent/WO2010126572A2/en
Publication of US20100275995A1 publication Critical patent/US20100275995A1/en
Assigned to GOLD HILL CAPITAL 2008, LP reassignment GOLD HILL CAPITAL 2008, LP SECURITY AGREEMENT Assignors: CALISOLAR INC.
Assigned to SILICON VALLEY BANK reassignment SILICON VALLEY BANK SECURITY AGREEMENT Assignors: CALISOLAR INC.
Assigned to Silicor Materials Inc. reassignment Silicor Materials Inc. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CALISOLAR INC.
Assigned to SILICOR MARTERIALS, INC. FKA CALISOLAR INC. reassignment SILICOR MARTERIALS, INC. FKA CALISOLAR INC. RELEASE Assignors: SILICON VALLEY BANK
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0684—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells double emitter cells, e.g. bifacial solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates generally to solar cells and, in particular, to an improved structure and manufacturing process for a bifacial solar cell.
  • Bifacial solar cells may use any of a variety of different designs to achieve higher efficiencies than those typically obtained by a conventional, monofacial solar cell.
  • One such design is shown in U.S. Pat. No. 5,665,175 which discloses a BSC configuration with first and second active regions formed on the front and back surfaces of the BSC, respectively, the two regions separated by a distance ⁇ .
  • the distance ⁇ allows a leakage current to flow between the first and second active regions, thus allowing a solar cell panel utilizing such bifacial cells to continue to operate even if one or more individual solar cells become shaded or defective.
  • U.S. Pat. No. 7,495,167 discloses an n + pp + structure and a method of producing the same.
  • the p + layer formed by boron diffusion, exhibits a lifetime close to that of the initial level of the substrate.
  • the '167 patent teaches that after phosphorous gettering, the cell must be annealed at a temperature of 600° C. or less for one hour or more.
  • the cell then undergoes a final heat treatment step in which the cell is fired at a temperature of around 700° C. or less for one minute or less.
  • U.S. Patent Application Publication No. 2005/0056312 discloses an alternative technique for achieving two or more p-n junctions in a single solar cell, the disclosed technique using transparent substrates (e.g., glass or quartz substrates).
  • the BSC includes two thin-film polycrystalline or amorphous cells formed on opposing sides of a transparent substrate. Due to the design of the cell, the high temperature deposition of the absorber layers can be completed before the low temperature deposition of the window layers, thus avoiding degradation or destruction of the p-n junctions.
  • the present invention provides a simplified manufacturing process and the resultant bifacial solar cell (BSC), the simplified manufacturing process reducing manufacturing costs.
  • the BSC utilizes a combination of a back surface contact grid and an overlaid blanket metal reflector. Additionally, a doped amorphous silicon layer is interposed between the contact grid and the blanket layer.
  • the manufacturing method is comprised of the steps of depositing a dopant of a first conductivity type onto the back surface of a silicon substrate to form a back surface doped region where the silicon substrate is of the same conductivity type as the dopant, depositing a back surface dielectric layer over the back surface doped region, forming an active area of a second conductivity type on the front surface of the silicon substrate, etching the active area, depositing a front surface passivation and AR dielectric layer onto the active area, applying and firing front and back surface contact grids, depositing a layer of doped amorphous silicon onto the back surface contact grid and the back surface dielectric, depositing a layer of metal over the doped amorphous silicon layer, and isolating the front active area.
  • the method may further comprise the step of depositing a conductive interface layer between the doped amorphous silicon layer and the metal layer.
  • a manufacturing method is provided that is comprised of the steps of depositing a boron doped layer onto the back surface of a p-type silicon substrate, depositing a back surface dielectric over the boron doped layer, diffusing phosphorous onto the front surface of the silicon substrate to form an n + layer and a front surface junction, removing the phosphor-silicate glass formed during the diffusion step (e.g., by etching with HF), depositing a front surface passivation and AR dielectric layer onto the n + layer, applying front and back surface contact grids, firing the front and back surface contact grids, depositing a boron doped layer of amorphous silicon onto the back surface grid and the back surface dielectric, depositing a metal layer onto the boron doped amorphous silicon layer, and isolating the front surface junction using, for example, a laser scriber.
  • the method may further comprise the step of depositing a conductive interface layer, for example comprised of ITO or ZnO:Al, between the boron doped amorphous silicon layer and the metal layer.
  • a conductive interface layer for example comprised of ITO or ZnO:Al
  • the front and back surface contact grid firing steps may be performed simultaneously. Alternately, the back surface contact grid applying and firing steps may be performed prior to, or after, the front surface contact grid applying and firing steps.
  • the boron doped layer depositing step can be formed by depositing a boron doped silicon dioxide layer using CVD, depositing a boron doped polysilicon layer using CVD, depositing a boron doped amorphous silicon layer using PE-CVD, spray coating a boric acid solution onto the back surface of the substrate, or spray/wipe coating a boron-doped spin-on glass onto the back surface of the substrate.
  • the phosphorous diffusing step may be performed at a temperature of approximately 850° C. for a duration of approximately 10 to 20 minutes.
  • the back surface dielectric depositing step may be performed after the step of applying the back surface contact grid.
  • a bifacial solar cell is provided that is comprised of a silicon substrate of a first conductivity type with a front surface active region of a second conductivity type and a back surface doped region of the first conductivity type, dielectric layers deposited on the front surface active region and on the back surface doped region, a front surface contact grid applied to the front surface dielectric layer which alloys through the front surface dielectric to the active region during firing, a back surface contact grid applied to the back surface dielectric layer which alloys through the back surface dielectric to the back surface doped region during firing, an amorphous silicon layer doped with a dopant of a first conductivity type deposited on the back surface contact grid and back surface dielectric, and a blanket metal layer deposited on the doped amorphous silicon layer.
  • the BSC may further comprise a groove on the front surface of the silicon substrate, the groove isolating the front surface junction.
  • the BSC may further comprise a conductive interface layer, for example comprised of ITO or ZnO:Al, interposed between the doped amorphous silicon layer and the metal layer.
  • the silicon substrate may be comprised of p-type silicon, the active region may be comprised of n + material resulting from a phosphorous diffusion step, and the doped region and the amorphous silicon layer may further comprise a boron dopant.
  • the silicon substrate may be comprised of n-type silicon, the active region may be comprised of p + material resulting from a boron diffusion step, and the doped region and the amorphous silicon layer may further comprise a phosphorous dopant.
  • the manufacturing method is comprised of the steps of forming an active area of a second conductivity type on the front surface of a silicon substrate of a first conductivity type, etching the front surface of the silicon substrate, depositing a front surface passivation and AR dielectric layer onto the active area, depositing a back surface dielectric layer over the back surface of the silicon substrate, applying and firing front and back surface contact grids, depositing a layer of doped amorphous silicon onto the back surface contact grid and the back surface dielectric, and depositing a layer of metal over the doped amorphous silicon layer.
  • the method may further comprise the step of removing a back surface junction formed during the active area forming step.
  • the method may further comprise the step of depositing a conductive interface layer between the doped amorphous silicon layer and the metal layer.
  • the manufacturing method is comprised of the steps of diffusing phosphorous onto the front surface of a silicon substrate to form an n + layer and a front surface junction and onto the back surface to form a back surface junction, removing the phosphor-silicate glass formed during the diffusion step (e.g., by etching with HF), depositing a passivation and AR dielectric layer on the front surface and a back surface dielectric onto the back surface, applying and firing front and back surface contact grids, and depositing a metal layer onto the back surface contact grid and back surface dielectric.
  • the front and back surface contact grid firing steps may be performed simultaneously.
  • the back surface contact grid applying and firing steps may be performed prior to, or after, the front surface contact grid applying and firing steps.
  • the method may further comprise the step of removing the back surface junction and isolating the front surface junction.
  • a back surface metal grid may be applied, for example by screen printing or deposition using a shadow mask, after removing the back surface junction and prior to depositing the dielectric layer on the back surface.
  • the back surface grid applying step may be performed after removing the back surface junction and prior to depositing the dielectric layer on the back surface.
  • the manufacturing method is comprised of the steps of depositing a back surface dielectric onto the back surface of a silicon substrate of a first conductivity type, forming an active area of a second conductivity type on the front surface of the silicon substrate, etching the front surface of the silicon substrate, depositing a front surface passivation and AR dielectric layer onto the active area, applying and firing front and back surface contact grids, depositing a layer of doped amorphous silicon onto the back surface contact grid and the back surface dielectric, depositing a layer of metal over the doped amorphous silicon layer, and isolating the front surface junction, for example using a laser scriber.
  • the method may further comprise the step of depositing a conductive interface layer between the doped amorphous silicon layer and the metal layer.
  • the manufacturing method is comprised of the steps of depositing a dielectric layer on the back surface of a silicon substrate, diffusing phosphorous onto the front surface of the substrate to form an n + layer and a front surface junction, removing the phosphor-silicate glass formed during the diffusion step (e.g., by etching with HF), depositing a front surface passivation and AR dielectric layer, applying and firing front and back surface contact grids, depositing a boron doped layer of amorphous silicon onto the back surface contact grid and back surface dielectric, depositing a metal layer onto the boron doped amorphous silicon layer, and isolating the front surface junction, for example using a laser scriber.
  • the method may further comprise the step of depositing a conductive interface layer, for example comprised of ITO or ZnO:Al, between the boron doped amorphous silicon layer and the metal layer.
  • a conductive interface layer for example comprised of ITO or ZnO:Al
  • the front and back surface contact grid firing steps may be performed simultaneously. Alternately, the back surface contact grid applying and firing steps may be performed prior to, or after, the front surface contact grid applying and firing steps.
  • a bifacial solar cell (BSC) is provided that is comprised of a silicon substrate with a front surface active region of a first conductivity type, dielectric layers deposited on the front surface active region and on the back surface of the silicon substrate, a back surface contact grid applied to the back surface dielectric which alloys through the back surface dielectric to the back surface of the silicon substrate during firing, an amorphous silicon layer doped with a dopant of the first conductivity type deposited on the back surface contact grid and back surface dielectric, and a blanket metal layer deposited on the doped amorphous silicon layer.
  • BSC bifacial solar cell
  • the BSC may further comprise a conductive interface layer, for example comprised of ITO or ZnO:Al, interposed between the doped amorphous silicon layer and the metal layer.
  • the silicon substrate may be comprised of p-type silicon, the active region may be comprised of n + material resulting from a phosphorous diffusion step, and the amorphous silicon layer may further comprise a boron dopant.
  • the silicon substrate may be comprised of n-type silicon, the active region may be comprised of p + material resulting from a boron diffusion step, and the amorphous silicon layer may further comprise a phosphorous dopant.
  • the BSC may further comprise a metal grid pattern deposited directly onto the back surface of the silicon substrate and interposed between the silicon substrate and the back surface dielectric layer.
  • the BSC may further comprise a groove on the front surface of the silicon substrate, the groove isolating the front surface junction.
  • FIG. 1 illustrates a preferred embodiment of a BSC in accordance with the invention
  • FIG. 2 illustrates the process flow for the BSC of FIG. 1 ;
  • FIG. 3 illustrates an alternate embodiment of the BSC of FIG. 1 ;
  • FIG. 4 illustrates the process flow for the BSC of FIG. 3 ;
  • FIG. 5 illustrates an alternate fabrication process for the BSC of FIG. 1 ;
  • FIG. 6 illustrates an alternate preferred embodiment of a BSC in accordance with the invention
  • FIG. 7 illustrates the process flow for the BSC of FIG. 6 ;
  • FIG. 8 illustrates an alternate preferred embodiment of a BSC in accordance with the invention
  • FIG. 9 illustrates the process flow for the BSC of FIG. 8 ;
  • FIG. 10 illustrates an alternate fabrication process for the BSC of FIG. 6 ;
  • FIG. 11 illustrates an alternate embodiment of the BSC of FIG. 8 .
  • FIG. 12 illustrates the process flow for the BSC of FIG. 11 .
  • a conventional mono-facial solar cell includes a grid-shaped electrode on the front surface and a solid electrode covering the entire back surface.
  • the electrode structure is designed to allow light to enter not only from the front surface, but also from the back surface.
  • the solid electrode covering the back surface in the mono-facial cell is replaced by a grid electrode in the BSC.
  • the grid-shaped back surface electrode allows light, e.g., indirect light, to enter from the rear.
  • bifacial solar cells are provided that combine a non-continuous, e.g., grid-shaped, back surface electrode with a back surface reflector, thereby obtaining the advantage of improved efficiency.
  • FIG. 1 illustrates a cross-sectional view of a preferred BSC structure fabricated in accordance with the procedure described in FIG. 2 .
  • Silicon substrate 101 may be of either p- or n-type. In the exemplary device and process illustrated in FIGS. 1 and 2 , a p-type substrate is used.
  • substrate 101 is prepared using any of a variety of well-known substrate preparatory processes (step 201 ).
  • saw and handling induced damage is removed via an etching process, for example using a nitric and hydrofluoric (HF) acid mixture.
  • the bottom surface of substrate 101 is doped, thereby forming a back surface doped region 103 (step 203 ).
  • region 103 is doped with the same doping type as substrate 101 . Increasing the doping level of region 103 , compared to substrate 101 , lowers the contact resistance. Additionally, doped region 103 reduces back surface recombination, a problem that is exacerbated by the inclusion of a back surface reflector.
  • region 103 is doped with a different doping type than that of substrate 101 .
  • Region 103 can be formed using any of a variety of techniques. Exemplary techniques include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced CVD (PE-CVD), spray coating, and spin coating. Accordingly, and assuming a p-type substrate and a p-type region 103 , this region can be formed by depositing a boron doped polysilicon layer using CVD; depositing a boron doped silicon dioxide or amorphous silicon layer using PE-CVD; spray/spin coating a boric acid solution or doped spin-on glass onto the back surface of substrate 101 ; or by other means.
  • CVD chemical vapor deposition
  • PE-CVD plasma enhanced CVD
  • spray coating and spin coating. Accordingly, and assuming a p-type substrate and a p-type region 103 , this region can be formed by depositing a boron doped polysilicon layer using CVD; depositing a boron doped silicon dioxide or amorphous silicon layer using PE-CVD
  • a dielectric layer 105 is deposited on the back surface of substrate 101 , specifically on top of doped region 103 as shown (step 205 ).
  • layer 105 is comprised of silicon nitride or silicon dioxide or a silicon dioxide/silicon nitride stack, preferably deposited using PE-CVD techniques at a temperature of 300° C. to 400° C., and has a thickness of approximately 76 nanometers for silicon nitride or 100 nanometers for silicon oxide.
  • an active region of a conductivity type different from that of the substrate is formed on the front surface of substrate 101 .
  • n + layer 107 is formed using phosphoryl chloride (POCl 3 ), where the diffusion is performed at a diffusion temperature in the range of 825° C. to 890° C., preferably at a temperature of approximately 850° C., for 10 to 20 minutes in a nitrogen atmosphere (step 207 ).
  • POCl 3 phosphoryl chloride
  • boron from region 103 is diffused into the back surface of substrate 101 to form a back surface field (BSF).
  • the phosphor-silicate glass (PSG) formed during diffusion step 207 is then etched away, for example using a hydrofluoric (HF) etch at or near room temperature for 1 to 5 minutes (step 209 ).
  • the front side junction has a depth of 0.3 to 0.6 microns and a surface doping concentration of about 8 ⁇ 10 21 /cm 3 .
  • a front surface passivation and anti-reflection (AR) dielectric layer 109 is deposited, preferably comprised of silicon nitride or silicon oxynitride or a stack of materials of the silicon oxide/silicon nitride system.
  • layer 109 is comprised of an approximately 76 nanometer thick layer of silicon nitride.
  • layer 109 is comprised of approximately 10 nanometers of SiO 2 under 70 nanometers of Si 3 N 4 .
  • layer 109 is deposited at a temperature of 300° C. to 400° C.
  • contact grids are applied to the front and back surfaces of BSC 100 (step 213 ), for example using a screen printing process.
  • front contact grid 111 is comprised of silver while back contact grid 113 is comprised of an aluminum-silver mixture.
  • both the front and back contact grids are aligned and use the same contact size and spacing, with electrodes being approximately 100 microns wide, 15 microns thick and spaced approximately 2.5 millimeters apart.
  • the back contact grid uses a finer spacing in order to lessen resistance losses from lateral current flow in the substrate.
  • a contact firing step 215 is performed, preferably at a peak temperature of 750° C.
  • the back reflector may be deposited directly over back surface dielectric layer 105 and contacts 113 , preferably a layer 115 of amorphous silicon is applied first to the back surface (step 217 ).
  • Layer 115 is preferably thin to minimize infrared absorption and series resistance, on the order of 5 to 40 nanometers thick, and deposited using a technique such as PE-CVD.
  • Layer 115 is heavily doped, preferably at a level of 10 19 /cm 3 or greater, with the same dopant type as substrate 101 , i.e., p-type dopant in exemplary structure which uses a p-type substrate.
  • boron is used as the dopant.
  • the blanket metal layer 117 is deposited on the back surface of the structure (step 219 ), metal layer 117 providing both a back surface reflector and means for making an electrical connection with contacts 113 .
  • metal layer 117 is 1 to 10 microns thick, with a thinner layer preferred to minimize wafer bowing.
  • layer 115 is transparent to the long wavelength photons that reach the reflective layer 117 .
  • the front junction is isolated, for example using a laser scriber to form a groove on the front cell surface around the periphery of the cell (step 221 ).
  • Blanket metal layer 117 is preferably deposited using either physical vapor deposition (PVD) or screen printing, although it will be appreciated that other techniques can be used.
  • layer 117 has a high red reflectance, thus extending the photon path length in region 101 and increasing the absorption of photons with a wavelength near the bandgap.
  • low cost metals are preferred, such as aluminum.
  • silver bus bars, a nickel vanadium coating or other materials can be added to the back surface of layer 117 to further enable soldering of back contacts.
  • FIGS. 3 and 4 illustrate an alternate embodiment utilizing a minor modification of the previously described device structure and process.
  • a thin conductive interface layer 301 is added between silicon layer 115 and back surface reflector layer 117 (step 401 ).
  • Layer 301 prevents the metal of layer 117 , e.g., aluminum, mixing with the silicon of layer 115 , thereby helping to maintain the high reflectivity of layer 117 .
  • Exemplary materials for layer 301 include indium tin oxide (ITO) and aluminum-doped zinc oxide (ZnO:Al).
  • the thickness of layer 301 is chosen to provide an optical match between the back surface and the metal layer 117 in the near infrared when taken in combination with the thickness of back surface dielectric layer 105 .
  • the thickness of a ZnO:Al layer 301 should be approximately 35 nanometers thick.
  • FIG. 5 illustrates an alternate process for fabricating cell 100 .
  • the phosphorous is diffused into the front surface of substrate 101 (step 207 ) to create the n + layer 107 and the p-n junction, thereby skipping back surface dielectric deposition step 205 .
  • the PSG is etched away (step 209 ) and front surface dielectric 109 is deposited (step 211 ).
  • the front surface contacts 111 and the back surface contacts are then applied (step 213 ), followed by the deposition of back surface dielectric layer 105 (step 501 ).
  • back surface dielectric layer 105 is preferably comprised of silicon nitride or silicon dioxide or a silicon dioxide/silicon nitride stack. If desired, the order of steps 211 , 213 and 501 can be altered, for example applying the back contact grid 113 first, followed by deposition of back surface dielectric layer 105 , followed by the application of the front contact grid 111 , and then followed by the deposition of the front surface dielectric layer 109 .
  • amorphous silicon layer 115 is deposited (step 217 ), followed by the deposition of blanket reflective layer 117 (step 219 ), all as previously described.
  • blanket reflective layer 117 if desired conductive interface layer 301 may be added between silicon layer 115 and back surface reflector layer 117 .
  • FIGS. 6 and 7 illustrate an alternate embodiment that eliminates doped region 103 .
  • front and back surface junctions are formed.
  • phosphorous is diffused onto the front surface of substrate 101 as previously described, creating n + layer 107 and a p-n junction at the interface of substrate 101 and n + layer 107 (step 701 ).
  • phosphorous is also diffused onto the back surface of substrate 101 , creating n + layer 601 and a floating junction.
  • step 701 is performed using phosphoryl chloride (POCl 3 ) with a diffusion temperature in the range of 825° C.
  • Active region diffusing step 701 is followed by a PSG (assuming phosphorous) etching step 209 , preferably using an HF etch at or near room temperature for 1 to 5 minutes.
  • PSG assuming phosphorous
  • a front surface passivation and anti-reflection (AR) dielectric layer 603 is deposited as well as a back surface passivation and AR dielectric layer 605 .
  • layers 603 and 605 are comprised of silicon nitride with an index of refraction of 2.07 and a layer thickness of approximately 76 nanometers.
  • layers 603 and 605 are comprised of silicon oxynitride.
  • layers 603 and 605 are comprised of a stack of two layers of different composition, for example 10 nanometers of silicon dioxide and 70 nanometers of silicon nitride. Layers 603 and 605 are preferably deposited at a temperature of 300° C. to 400° C.
  • front and back surface contact grids are applied (step 213 ) and fired (step 215 ), followed by deposition of blanket reflective layer 117 (step 219 ), all as previously described.
  • preferably front contact grid 111 is comprised of silver while back contact grid 113 is comprised of aluminum.
  • Contact firing step 215 is preferably performed at a peak temperature of 750° C. for 3 seconds in air.
  • contacts 111 alloy through passivation and AR dielectric coating 603 to n + layer 107 .
  • Contacts 113 alloy through passivation and AR dielectric coating 605 and back diffused layer 601 to form contact to substrate 101 .
  • a diode forms between back diffused layer 601 and contact 113 so that current does not flow from the back diffused layer into the contact and the back diffusion is floating. This isolates the back surface from the bulk 101 since there is zero current into a floating junction.
  • conductive interface layer 301 may be added between silicon layer 115 and back surface reflector layer 117 . This embodiment can also separate the contact grid deposition process and firing of the front and back surface contact grids as previously described.
  • FIGS. 8 and 9 illustrate an alternate embodiment in which the floating junction on the back surface of the substrate is removed.
  • the back surface of substrate 101 is etched (step 901 ), thereby removing the back surface junction and providing isolation for the front junction.
  • step 901 uses an isotropic wet silicon etch such as a mixture of nitric acid and HF acid.
  • the back surface contact grid is comprised of an aluminum-silver mixture.
  • FIG. 10 illustrates an alternate process for fabricating cell 600 .
  • dielectric layer 605 is applied to the back surface of substrate 101 (step 1001 ).
  • dielectric layer 603 is comprised of silicon nitride or silicon oxynitride. Applying dielectric layer 605 prior to diffusing the front surface n + layer 107 (step 701 ) prevents the formation of a back surface junction.
  • front surface passivation and AR dielectric layer 603 is deposited (step 1003 ), followed by applying (step 213 ) and firing (step 215 ) of the contact grids, deposition of amorphous silicon layer 115 (step 217 ), and deposition of back surface reflector 117 (step 219 ).
  • the front junction is isolated, for example using a laser scriber to form a groove on the front cell surface around the periphery of the cell (step 1005 ).
  • This embodiment may also include conductive interface layer 301 between silicon layer 115 and back surface reflector layer 117 and, additionally, may separate the contact grid deposition and firing of the front and back surface contact grids as previously described.
  • FIGS. 11 and 12 illustrate a variation of BFC 800 .
  • a metal grid 1101 is applied directly onto the back surface of cell 101 (step 1201 ), thereby reducing contact resistance.
  • Step 1201 is preferably performed after the back surface of substrate 101 has been etched to remove the back surface junction and isolate the front junction (step 901 ).
  • Step 1201 is performed using either a deposition process with a shadow mask, or using a screen printing process.
  • metal grid 1101 is comprised of aluminum.
  • contact grids 111 and 113 are applied and fired, either together or separately as previously described. Back surface contact grid 113 is registered to metal grid 1101 .
  • contact grid 113 alloys to metal grid 1101 .
  • amorphous silicon layer 115 is deposited (step 217 ), followed by the deposition of blanket reflective layer 117 (step 219 ), all as previously described.
  • blanket reflective layer 117 step 219
  • conductive interface layer 301 may be added between silicon layer 115 and back surface reflector layer 117 .
  • the process eliminates the steps of applying and firing the back surface contact grid 113 .
  • metal grid 1101 fires through the overlaid dielectric layer, thereby allowing metal layer 117 to connect to metal grid 1101 .
  • an n-type substrate may also be used with the invention.
  • an n-type dopant such as phosphorous
  • a p-type dopant such as boron
  • an n-type dopant e.g., phosphorous
  • identical element symbols used on multiple figures refer to the same component/processing step, or components/processing steps of equal functionality.

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US12/456,398 US20100275995A1 (en) 2009-05-01 2009-06-15 Bifacial solar cells with back surface reflector
EP10770047.8A EP2425457A4 (en) 2009-05-01 2010-04-19 BIFACEE SOLAR CELLS COMPRISING A REAR FACE REFLECTOR
JP2012508467A JP2012525703A (ja) 2009-05-01 2010-04-19 裏面反射体を備える両面型太陽電池
CN201080019116XA CN102549765A (zh) 2009-05-01 2010-04-19 具有后表面反射器的双面太阳能电池
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100275983A1 (en) * 2009-05-01 2010-11-04 Calisolar, Inc. Bifacial solar cells with overlaid back grid surface
US20120048365A1 (en) * 2010-08-27 2012-03-01 Daeyong Lee Solar cell and manufacturing method thereof
US20120318345A1 (en) * 2011-06-20 2012-12-20 Yoonsil Jin Solar cell
US20130133741A1 (en) * 2010-10-05 2013-05-30 Mitsubishi Electric Corporation Photovoltaic device and manufacturing method thereof
US20130139881A1 (en) * 2010-10-20 2013-06-06 Mitsubishi Electric Corporation Photovoltaic device and manufacturing method thereof
US20130199606A1 (en) * 2012-02-06 2013-08-08 Applied Materials, Inc. Methods of manufacturing back surface field and metallized contacts on a solar cell device
CN103247715A (zh) * 2012-02-10 2013-08-14 信越化学工业株式会社 太阳能电池及其制造方法
US20140057413A1 (en) * 2012-08-23 2014-02-27 Michael Xiaoxuan Yang Methods for fabricating devices on semiconductor substrates
US20140158193A1 (en) * 2011-08-09 2014-06-12 Solexel, Inc. Structures and methods of formation of contiguous and non-contiguous base regions for high efficiency back-contact solar cells
US20140230894A1 (en) * 2012-02-29 2014-08-21 Bakersun Bifacial crystalline silicon solar panel with reflector
WO2016122731A1 (en) * 2015-01-26 2016-08-04 1366 Technologies, Inc. Method for creating a semiconductor wafer having profiled doping and wafers and solar cell components having a profiled field, such as drift and back surface
CN107104161A (zh) * 2012-02-29 2017-08-29 贝克阳光公司 具有反射器的双面晶体硅太阳能板
US11145509B2 (en) 2019-05-24 2021-10-12 Applied Materials, Inc. Method for forming and patterning a layer and/or substrate
US11189739B1 (en) * 2020-11-19 2021-11-30 Jinko Green Energy (shanghai) Management Co., Ltd. Solar cell

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3770974A1 (en) * 2009-09-18 2021-01-27 Shin-Etsu Chemical Co., Ltd. Solar cell, method for manufacturing solar cell, and solar cell module
TW201121066A (en) * 2009-12-14 2011-06-16 Ind Tech Res Inst Bificial solar cell
DE102010025983A1 (de) * 2010-03-03 2011-09-08 Centrotherm Photovoltaics Ag Solarzelle mit dielektrischer Rückseitenverspiegelung und Verfahren zu deren Herstellung
KR101661768B1 (ko) * 2010-09-03 2016-09-30 엘지전자 주식회사 태양전지 및 이의 제조 방법
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KR101699299B1 (ko) 2011-03-29 2017-01-24 엘지전자 주식회사 양면 수광형 태양전지
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CN102437246B (zh) * 2011-12-20 2013-12-25 日地太阳能电力股份有限公司 一种晶体硅太阳能电池的制备方法
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KR101329855B1 (ko) * 2012-01-31 2013-11-14 현대중공업 주식회사 양면수광형 태양전지의 제조방법
KR101335082B1 (ko) * 2012-02-01 2013-12-03 현대중공업 주식회사 양면수광형 태양전지의 제조방법
KR20130096822A (ko) 2012-02-23 2013-09-02 엘지전자 주식회사 태양 전지 및 그 제조 방법
KR20140022515A (ko) 2012-08-13 2014-02-25 엘지전자 주식회사 태양 전지
EP2701204B1 (en) * 2012-08-24 2021-02-24 Industrial Technology Research Institute Solar cell module
TWI484115B (zh) * 2012-08-31 2015-05-11 George Uh-Schu Liau 光電盒
KR101372305B1 (ko) * 2012-09-21 2014-03-14 영남대학교 산학협력단 태양전지 셀 및 이의 제조방법
US20140238478A1 (en) * 2013-02-28 2014-08-28 Suniva, Inc. Back junction solar cell with enhanced emitter layer
US20140361407A1 (en) * 2013-06-05 2014-12-11 SCHMID Group Silicon material substrate doping method, structure and applications
CN103367545A (zh) * 2013-07-08 2013-10-23 浙江晶科能源有限公司 一种在太阳电池背面利用激光同步实现局域接触和局域掺杂的方法
US10217893B2 (en) * 2013-09-16 2019-02-26 Special Materials Research And Technology, Inc. (Specmat) Methods, apparatus, and systems for passivation of solar cells and other semiconductor devices
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KR101627029B1 (ko) * 2014-02-20 2016-06-03 제일모직주식회사 Ibc 태양전지의 제조방법
DE102014105358A1 (de) * 2014-04-15 2015-10-15 Solarworld Innovations Gmbh Solarzelle und Verfahren zum Herstellen einer Solarzelle
US20160072000A1 (en) * 2014-09-05 2016-03-10 David D. Smith Front contact heterojunction process
CN105405924B (zh) * 2014-11-28 2017-11-03 南昌大学 一种晶体硅基太阳电池用的高方阻掺杂晶硅层的制备方法
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CN114127959A (zh) * 2019-05-29 2022-03-01 索拉昂德有限公司 双面光伏电池制造工艺
TWI718703B (zh) * 2019-10-09 2021-02-11 長生太陽能股份有限公司 太陽能電池及其製造方法

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468853A (en) * 1982-05-13 1984-09-04 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a solar cell
US4994879A (en) * 1988-11-25 1991-02-19 Agency Of Industrial Science & Technology Photoelectric transducer with light path of increased length
US5665175A (en) * 1990-05-30 1997-09-09 Safir; Yakov Bifacial solar cell
US6096968A (en) * 1995-03-10 2000-08-01 Siemens Solar Gmbh Solar cell with a back-surface field
US20040063326A1 (en) * 2002-07-01 2004-04-01 Interuniversitair Microelektronica Centrum (Imec) Semiconductor etching paste and the use thereof for localized etching of semiconductor substrates
US20050016585A1 (en) * 2001-11-26 2005-01-27 Adolf Munzer Manufacturing a solar cell with backside contacts
US20050022863A1 (en) * 2003-06-20 2005-02-03 Guido Agostinelli Method for backside surface passivation of solar cells and solar cells with such passivation
US20050056312A1 (en) * 2003-03-14 2005-03-17 Young David L. Bifacial structure for tandem solar cells
US20050133084A1 (en) * 2003-10-10 2005-06-23 Toshio Joge Silicon solar cell and production method thereof
US20070137699A1 (en) * 2005-12-16 2007-06-21 General Electric Company Solar cell and method for fabricating solar cell
US20070175508A1 (en) * 2005-11-08 2007-08-02 Lg Chem, Ltd. Solar cell of high efficiency and process for preparation of the same
US20080257399A1 (en) * 2007-04-19 2008-10-23 Industrial Technology Research Institute Bifacial thin film solar cell and method for making the same
US20090211627A1 (en) * 2008-02-25 2009-08-27 Suniva, Inc. Solar cell having crystalline silicon p-n homojunction and amorphous silicon heterojunctions for surface passivation
US20100027598A1 (en) * 2007-02-13 2010-02-04 Yusuke Kanahashi Software radio transceiver
US20100275983A1 (en) * 2009-05-01 2010-11-04 Calisolar, Inc. Bifacial solar cells with overlaid back grid surface
US20120000517A1 (en) * 2008-02-25 2012-01-05 Ju-Hwan Yun Solar cell and method for manufacturing the same

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4166919A (en) * 1978-09-25 1979-09-04 Rca Corporation Amorphous silicon solar cell allowing infrared transmission
DE3815512C2 (de) * 1988-05-06 1994-07-28 Deutsche Aerospace Solarzelle und Verfahren zu ihrer Herstellung
JP2994735B2 (ja) * 1990-11-27 1999-12-27 シャープ株式会社 太陽電池
JPH08111537A (ja) * 1994-10-07 1996-04-30 Sharp Corp 太陽電池
JP3342339B2 (ja) * 1997-02-28 2002-11-05 三洋電機株式会社 半導体集積回路およびその製造方法
JP2999985B2 (ja) * 1997-11-25 2000-01-17 シャープ株式会社 太陽電池
JP2000138386A (ja) * 1998-11-04 2000-05-16 Shin Etsu Chem Co Ltd 太陽電池の製造方法およびこの方法で製造された太陽電池
JP2001044470A (ja) * 1999-07-30 2001-02-16 Hitachi Ltd 太陽電池および太陽電池の製造方法並びに集光型太陽電池モジュール
JP4812147B2 (ja) * 1999-09-07 2011-11-09 株式会社日立製作所 太陽電池の製造方法
JP2002076400A (ja) * 2000-08-30 2002-03-15 Shin Etsu Handotai Co Ltd 太陽電池セルおよび太陽電池セルの製造方法
JP2002198546A (ja) * 2000-12-27 2002-07-12 Kyocera Corp 太陽電池素子の形成方法
JP2002353475A (ja) * 2001-05-29 2002-12-06 Kyocera Corp 太陽電池素子
JP2003209271A (ja) * 2002-01-16 2003-07-25 Hitachi Ltd 太陽電池およびその製造方法
JP4593980B2 (ja) * 2004-03-29 2010-12-08 京セラ株式会社 光電変換装置とこれを用いた太陽電池素子、並びに太陽電池モジュール
EP1763086A1 (en) * 2005-09-09 2007-03-14 Interuniversitair Micro-Elektronica Centrum Photovoltaic cell with thick silicon oxide and silicon nitride passivation and fabrication method
US7375378B2 (en) * 2005-05-12 2008-05-20 General Electric Company Surface passivated photovoltaic devices
US7824579B2 (en) * 2005-06-07 2010-11-02 E. I. Du Pont De Nemours And Company Aluminum thick film composition(s), electrode(s), semiconductor device(s) and methods of making thereof
JP2007096040A (ja) * 2005-09-29 2007-04-12 Sharp Corp 太陽電池の製造方法および太陽電池
US20070107773A1 (en) 2005-11-17 2007-05-17 Palo Alto Research Center Incorporated Bifacial cell with extruded gridline metallization
CN101336465B (zh) * 2005-11-24 2011-07-06 新南创新私人有限公司 小面积丝网印刷金属接点结构及方法
NL2000248C2 (nl) 2006-09-25 2008-03-26 Ecn Energieonderzoek Ct Nederl Werkwijze voor het vervaardigen van kristallijn-silicium zonnecellen met een verbeterde oppervlaktepassivering.
WO2008045511A2 (en) * 2006-10-11 2008-04-17 Gamma Solar Photovoltaic solar module comprising bifacial solar cells
DE102007012277A1 (de) * 2007-03-08 2008-09-11 Gebr. Schmid Gmbh & Co. Verfahren zur Herstellung einer Solarzelle sowie damit hergestellte Solarzelle
JP2009059833A (ja) * 2007-08-31 2009-03-19 Hitachi Ltd 太陽電池
CN100573928C (zh) * 2007-10-08 2009-12-23 苏州阿特斯阳光电力科技有限公司 一种制造太阳能电池的磷扩散方法
WO2009052511A2 (en) * 2007-10-18 2009-04-23 Belano Holdings, Ltd. Mono-silicon solar cells

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468853A (en) * 1982-05-13 1984-09-04 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a solar cell
US4994879A (en) * 1988-11-25 1991-02-19 Agency Of Industrial Science & Technology Photoelectric transducer with light path of increased length
US5665175A (en) * 1990-05-30 1997-09-09 Safir; Yakov Bifacial solar cell
US6096968A (en) * 1995-03-10 2000-08-01 Siemens Solar Gmbh Solar cell with a back-surface field
US20050016585A1 (en) * 2001-11-26 2005-01-27 Adolf Munzer Manufacturing a solar cell with backside contacts
US20040063326A1 (en) * 2002-07-01 2004-04-01 Interuniversitair Microelektronica Centrum (Imec) Semiconductor etching paste and the use thereof for localized etching of semiconductor substrates
US20050056312A1 (en) * 2003-03-14 2005-03-17 Young David L. Bifacial structure for tandem solar cells
US20050022863A1 (en) * 2003-06-20 2005-02-03 Guido Agostinelli Method for backside surface passivation of solar cells and solar cells with such passivation
US20050133084A1 (en) * 2003-10-10 2005-06-23 Toshio Joge Silicon solar cell and production method thereof
US7495167B2 (en) * 2003-10-10 2009-02-24 Hitachi, Ltd. Silicon solar cell and production method thereof
US20070175508A1 (en) * 2005-11-08 2007-08-02 Lg Chem, Ltd. Solar cell of high efficiency and process for preparation of the same
US20070137699A1 (en) * 2005-12-16 2007-06-21 General Electric Company Solar cell and method for fabricating solar cell
US20100027598A1 (en) * 2007-02-13 2010-02-04 Yusuke Kanahashi Software radio transceiver
US20080257399A1 (en) * 2007-04-19 2008-10-23 Industrial Technology Research Institute Bifacial thin film solar cell and method for making the same
US20090211627A1 (en) * 2008-02-25 2009-08-27 Suniva, Inc. Solar cell having crystalline silicon p-n homojunction and amorphous silicon heterojunctions for surface passivation
US20120000517A1 (en) * 2008-02-25 2012-01-05 Ju-Hwan Yun Solar cell and method for manufacturing the same
US20100275983A1 (en) * 2009-05-01 2010-11-04 Calisolar, Inc. Bifacial solar cells with overlaid back grid surface
US8298850B2 (en) * 2009-05-01 2012-10-30 Silicor Materials Inc. Bifacial solar cells with overlaid back grid surface
US20130056061A1 (en) * 2009-05-01 2013-03-07 Silicor Material Inc. Bifacial solar cells with overlaid back grid surface
US8404970B2 (en) * 2009-05-01 2013-03-26 Silicor Materials Inc. Bifacial solar cells with back surface doping

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Kim et al. "Advanced front and rear metallization for thin and high efficiency crystalline silicon solar cells". Presentation 2CV.4.15. 22nd European photovoltaic solar energy conference and exhibition, Milan, 2007. *

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100275983A1 (en) * 2009-05-01 2010-11-04 Calisolar, Inc. Bifacial solar cells with overlaid back grid surface
US20100275984A1 (en) * 2009-05-01 2010-11-04 Calisolar, Inc. Bifacial solar cells with back surface doping
US8298850B2 (en) 2009-05-01 2012-10-30 Silicor Materials Inc. Bifacial solar cells with overlaid back grid surface
US8404970B2 (en) * 2009-05-01 2013-03-26 Silicor Materials Inc. Bifacial solar cells with back surface doping
US20120048365A1 (en) * 2010-08-27 2012-03-01 Daeyong Lee Solar cell and manufacturing method thereof
US10121915B2 (en) * 2010-08-27 2018-11-06 Lg Electronics Inc. Solar cell and manufacturing method thereof
US20130133741A1 (en) * 2010-10-05 2013-05-30 Mitsubishi Electric Corporation Photovoltaic device and manufacturing method thereof
US20130139881A1 (en) * 2010-10-20 2013-06-06 Mitsubishi Electric Corporation Photovoltaic device and manufacturing method thereof
US20120318345A1 (en) * 2011-06-20 2012-12-20 Yoonsil Jin Solar cell
US20140158193A1 (en) * 2011-08-09 2014-06-12 Solexel, Inc. Structures and methods of formation of contiguous and non-contiguous base regions for high efficiency back-contact solar cells
US20130199606A1 (en) * 2012-02-06 2013-08-08 Applied Materials, Inc. Methods of manufacturing back surface field and metallized contacts on a solar cell device
US9871156B2 (en) * 2012-02-10 2018-01-16 Shin-Etsu Chemical Co., Ltd. Solar cell and method of manufacturing the same
CN103247715A (zh) * 2012-02-10 2013-08-14 信越化学工业株式会社 太阳能电池及其制造方法
US20130206229A1 (en) * 2012-02-10 2013-08-15 Shin-Etsu Chemical Co., Ltd. Solar cell and method of manufacturing the same
US20140230894A1 (en) * 2012-02-29 2014-08-21 Bakersun Bifacial crystalline silicon solar panel with reflector
US9379270B2 (en) * 2012-02-29 2016-06-28 Bakersun Bifacial crystalline silicon solar panel with reflector
CN107104161A (zh) * 2012-02-29 2017-08-29 贝克阳光公司 具有反射器的双面晶体硅太阳能板
US9196503B2 (en) * 2012-08-23 2015-11-24 Michael Xiaoxuan Yang Methods for fabricating devices on semiconductor substrates
US20140057413A1 (en) * 2012-08-23 2014-02-27 Michael Xiaoxuan Yang Methods for fabricating devices on semiconductor substrates
WO2016122731A1 (en) * 2015-01-26 2016-08-04 1366 Technologies, Inc. Method for creating a semiconductor wafer having profiled doping and wafers and solar cell components having a profiled field, such as drift and back surface
US10439095B2 (en) 2015-01-26 2019-10-08 1366 Technologies, Inc. Methods for creating a semiconductor wafer having profiled doping and wafers and solar cell components having a profiled field, such as drift and back surface
US10770613B2 (en) 2015-01-26 2020-09-08 1366 Technologies Inc. Methods for creating a semiconductor wafer having profiled doping and wafers and solar cell components having a profiled field, such as drift and back surface
US11145509B2 (en) 2019-05-24 2021-10-12 Applied Materials, Inc. Method for forming and patterning a layer and/or substrate
US11189739B1 (en) * 2020-11-19 2021-11-30 Jinko Green Energy (shanghai) Management Co., Ltd. Solar cell
US11990555B2 (en) 2020-11-19 2024-05-21 Jinko Green Energy (shanghai) Management Co., Ltd. Solar cell

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