US20100188542A1 - Imaging device and image sensor chip - Google Patents

Imaging device and image sensor chip Download PDF

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Publication number
US20100188542A1
US20100188542A1 US12/692,037 US69203710A US2010188542A1 US 20100188542 A1 US20100188542 A1 US 20100188542A1 US 69203710 A US69203710 A US 69203710A US 2010188542 A1 US2010188542 A1 US 2010188542A1
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Prior art keywords
analog
data
column
pixel
pixel array
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English (en)
Inventor
Toshitaka Mizuguchi
Katsuyoshi Yamamoto
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIZUGUCHI, TOSHITAKA, YAMAMOTO, KATSUYOSHI
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Publication of US20100188542A1 publication Critical patent/US20100188542A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • Embodiments discussed herein relate to an imaging device.
  • ADC Analog-Digital Converter
  • an imaging device includes a pixel array that includes a plurality of pixels, a data read circuit that sequentially reads the data of a given line from the pixel array, a plurality of column analog-digital converters that perform analog-digital conversion on the data from the data read circuit, and a control signal generating circuit that generates a control signal to control the analog-digital conversion.
  • FIG. 1 illustrates an exemplary imaging device
  • FIG. 2 illustrates an exemplary operation timing diagram
  • FIG. 3 illustrates an exemplary imaging element
  • FIG. 4 illustrates an exemplary operation timing diagram
  • FIG. 5 illustrates an exemplary imaging device
  • FIG. 6 illustrates an exemplary image sensor chip
  • FIG. 7 illustrates an exemplary image sensor chip
  • FIG. 8 illustrates an exemplary operation timing diagram
  • FIG. 9 illustrates an exemplary an image sensor chip
  • FIG. 10 illustrates an exemplary operation timing diagram.
  • FIG. 1 illustrates an exemplary imaging device.
  • a reference numeral 1 designates a pixel array
  • a reference numeral 10 designates a pixel
  • reference numerals 11 to 14 designate sub-pixels (pixel).
  • a reference numeral 20 designates a preamplifier (Pre AMP) and a Correlated Double Sampling (CDS) circuit
  • the reference numeral 30 designates a column Analog-Digital Converter (column ADC)
  • a reference numeral 40 designates a ramp signal generating circuit.
  • the pixel 10 may include, for example, the red sub-pixel 11 , the green sub-pixels 12 and 13 , and the blue sub-pixel 14 .
  • the pixel 10 may include a two-by-two matrix of sub-pixels.
  • the column ADC 30 converts analog data of pixels in a column direction, such as analog data of pixels in one line, which is supplied from the preamplifier and correlated double sampling circuit 20 , into 14-bit data based on a ramp signal RMP from the ramp signal generating circuit 40 .
  • FIG. 2 illustrates an exemplary operation timing diagram.
  • the operation timing diagram of FIG. 2 may refer to the timing of the imaging element of FIG. 1 .
  • the column ADC 30 reads the analog data at an initial timing of one horizontal time 1 H every column line, and performs analog-digital conversion based on the ramp signal RMP.
  • the column ADC 30 supplies the digital data in final timing of one horizontal time 1 H.
  • the preamplifier and correlated double sampling circuit 20 reads signals from the pixel array 1 , the signals are supplied to the column ADC 30 , and the analog-digital conversion is performed based on the ramp signal RMP (column ADC method).
  • one column line and two analog-digital conversion blocks may be coupled by a switching element.
  • the red and blue pixels may be processed by one of the analog-digital conversion blocks.
  • the green pixel may be processed by the other analog-digital conversion block.
  • the analog-digital conversion blocks may include sampling processing, amplifying processing, or conversion processing.
  • the outputs from one pixel string may be fed into at least two ADCs and the two ADCs may perform in parallel.
  • the conversion speed of the column ADC may be enhanced for the increased number of pixels and the speed enhancement in the imaging device, and a high resolution and a high frame rate of the output data may be obtained.
  • FIG. 3 illustrates an exemplary imaging element.
  • a reference numeral 1 designates a pixel array
  • a reference numeral 10 designates a pixel
  • reference numerals 11 to 14 designate sub-pixels, for example, a pixel.
  • a reference numeral 20 designates a preamplifier (Pre AMP) and Correlated Double Sampling (CDS) circuit
  • reference numerals 31 to 38 designate column Analog-Digital Converters (column ADCs)
  • a reference numeral 40 designates a ramp signal generating circuit.
  • Pre AMP preamplifier
  • CDS Correlated Double Sampling
  • reference numerals 31 to 38 designate column Analog-Digital Converters (column ADCs)
  • a reference numeral 40 designates a ramp signal generating circuit.
  • the pixel 10 may include, for example, the red sub-pixel 11 , the green sub-pixels 12 and 13 , and the blue sub-pixel 14 .
  • the pixel 10 may include the two-by-two matrix of sub-pixels, and the green sub-pixels 12 and 13 may be provided in diagonal positions of the two-by-two configuration.
  • the preamplifier and correlated double sampling circuit (Pre AMP+CDS) 20 and the eight column ADCs 31 to 38 are disposed on one side of the pixel array 1 in which the pixel, for example, the sub-pixels, are disposed in a matrix shape.
  • the column ADC 30 converts the analog data of pixels in a column direction, such as the analog data of pixels in one line, into digital data, which is supplied from the preamplifier and correlated double sampling circuit 20 , into 14-bit data based on the ramp signal RMP from the ramp signal generating circuit 40 .
  • FIG. 4 illustrates an exemplary operation timing diagram.
  • the operation timing diagram of FIG. 4 may represent the timing of the imaging element of FIG. 3 .
  • the analog data from the eight column lines may be analog-digital converted as a unit.
  • the eight column lines for example, the analog data of first to eighth column lines, are read by the eight corresponding column ADCs 31 to 38 .
  • the analog data of the first column line is read and retained by the column ADC 31 through the preamplifier and correlated double sampling circuit 20 .
  • the analog data of the second column line is read and retained by the column ADC 32 .
  • the analog data of the seventh column line is read and retained by the column ADC 37 .
  • the analog data of the eighth column line is read and retained by the column ADC 38 .
  • the pieces of analog data of first to eighth column lines are read and retained by the column ADCs 31 to 38 .
  • the analog data of eight column lines are read by the eight column ADCs 31 to 38 .
  • the analog-digital conversion is performed on the retained analog data based on the common ramp signal RMP.
  • the analog-digital conversion may contemporaneously be performed on the analog data.
  • the analog-digital converted data are output based on the ramp signal RMP supplied every eight horizontal times.
  • the analog data of the ninth column line is read and retained by the column ADCs 31 , and similar processing is repeated.
  • the column ADCs 31 to 38 perform the analog-digital conversion in seven horizontal times.
  • the high-speed analog-digital conversion may be performed with a low-cost ADC, for example.
  • the noise and the power consumption may be reduced.
  • FIG. 5 illustrates an exemplary imaging device.
  • eight column ADCs include a first group of column ADCs 311 to 314 that are provided on an upper side of the pixel array 1 and a second group of column ADCs 321 to 324 that are provided on a lower side of the pixel array 1 .
  • a first preamplifier and correlated double sampling circuit (Pre AMP+CDS) 21 may be provided between the pixel array 1 and the upper-side first group of column ADCs.
  • a second preamplifier and correlated double sampling circuit 22 may be provided between the pixel array 1 and the lower-side second group of column ADCs.
  • the pixel 10 may include, for example, the red sub-pixel 11 , the green sub-pixels 12 and 13 , and the blue sub-pixel 14 .
  • the pixel 10 may include the two-by-two matrix of sub-pixels, and the green sub-pixels 12 and 13 may be provided at the diagonal positions of the two-by-two configuration.
  • the column ADCs 311 to 314 provided on the upper side of the pixel array 1 may perform the analog-digital conversion of the data detected by the red sub-pixels 11 and green sub-pixels 12 , which are located in the odd-numbered lines.
  • the column ADCs 321 to 324 provided on the lower side of the pixel array 1 may perform the analog-digital conversion of the data detected by the green sub-pixel 13 and blue sub-pixel 14 , which are located in the even-numbered lines.
  • the analog-digital converted red and green data may be output from the column ADCs 311 to 314 .
  • the analog-digital converted green and blue data may be output from the column ADCs 321 to 324 .
  • the preamplifiers and correlated double sampling circuits 21 and 22 provided on the upper and lower sides of the pixel array 1 contemporaneously read the data corresponding to the column ADCs 311 to 314 and 321 to 324 provided on the upper and lower sides of the pixel array 1 .
  • the ramp signal generating circuit 40 supplies a common ramp signal RMP every eight horizontal time period to the column ADCs 311 to 314 and 321 to 324 provided on the upper and lower sides of the pixel array 1 .
  • the pixel 10 may include the two-by-two matrix of four sub-pixels like the previous embodiment, or the pixel 10 may include sub-pixels having another configuration.
  • FIG. 6 illustrates an exemplary image sensor chip.
  • the image sensor chip of FIG. 6 may include an imaging device.
  • An image sensor chip 100 includes the pixel array 1 , an internal-voltage generating circuit and ramp signal generating circuit 400 , a preamplifier and correlated double sampling circuit (Pre AMP+CDS) 200 , a column ADC circuit string 300 , and a shift register string 310 .
  • Pre AMP+CDS preamplifier and correlated double sampling circuit
  • the image sensor chip 100 may also include a driver string 510 , a pixel control circuit string 520 , a shift register string 530 , a timing generator 600 , and a digital signal processor (DSP) 700 .
  • the driver string 510 , the pixel control circuit string 520 , and the shift register string 530 may include a driver circuit.
  • the internal-voltage generating circuit and ramp signal generating circuit 400 generates an internal voltage such as a reset voltage VR to be supplied to the imaging element, for example, a circuit 110 corresponding to the sub-pixel 11 .
  • the internal-voltage generating circuit and ramp signal generating circuit 400 also generates the ramp signal RMP.
  • the pixel read circuit string 200 reads the data in the column direction of the pixel array 1 , which is selected by the driver string 510 (for example, the data of the sub-pixel of every column line), and the pixel read circuit string 200 supplies the data to the column ADC circuit string 300 .
  • the pixel read circuit string 200 and the column ADC circuit string 300 may correspond to the preamplifier and correlated double sampling circuit 20 and eight column ADCs 31 to 38 of FIG. 3 .
  • the shift register string 310 shifts and supplies the analog-digital converted data by the column ADC circuit string 300 .
  • the driver string 510 may select all of the lines of the pixel array 1 in one horizontal time 1 H in accordance with the outputs of the shift register string 530 and pixel control circuit string 520 .
  • the image sensor chip 100 includes the timing generator 600 that supplies a timing signal to the circuit block, and the digital signal processor 700 that controls the entire image sensor chip 100 .
  • FIG. 7 illustrates an exemplary image sensor chip.
  • the circuit of FIG. 7 may be a main part of the image sensor chip of FIG. 6 .
  • the imaging element for example, the circuit 110 corresponding to the sub-pixel 11 , includes four nMOS transistors Tr 1 to Tr 4 and a photodiode PD.
  • the photodiode PD detects light incident through a color filter (for example, a red filter).
  • a reset signal RST is supplied to a gate of the transistor Tr 1 .
  • a trigger signal TG is supplied to a gate of the transistor Tr 2 .
  • a selection signal SLCT is supplied to a gate of the transistor Tr 4 .
  • a gate of the transistor Tr 3 is coupled to a common connection node of the transistors Tr 1 and Tr 2 .
  • the preamplifier and correlated double sampling circuit 20 includes two differential amplifiers AMP 1 and AMP 2 , a capacitor C 2 , and a switch Sw 2 .
  • the preamplifier and correlated double sampling circuit 20 receives the analog signal from the imaging element circuit 110 through a switch Sw 1 .
  • a capacitor C 1 having one end thereof grounded, is provided in the input of the preamplifier and correlated double sampling circuit 20 .
  • the column ADC for example, the column ADC 31 , may include a counter 311 , a latch 312 , a differential amplifier AMP 3 , a capacitor C 3 , and three switches Sw 3 to Sw 5 .
  • the plural imaging element circuits 110 included in the selected line in the pixel array 1 supply the signals detected by the photodiodes PD to the preamplifier and correlated double sampling circuit 20 through the corresponding read signal line SL and the switch Sw 1 .
  • the ramp signal RMP is declined with a given gradient according to the analog-digital conversion of the column ADC 31 .
  • the ramp signal RMP is supplied to a node n 1 through the switch Sw 4 .
  • the latch 312 latches the output of the counter 311 according to the output of the differential amplifier AMP 3 , and retains the latched counter value as a digital value of the analog-digital conversion result.
  • the retained signal may be output every eight lines.
  • the signals SLCT, RST, and TG supplied to the imaging element circuit 110 may be the control signals of the sub-pixels (pixel).
  • the signals for controlling the switching of the switches Sw 1 and Sw 2 may be the control signal of the preamplifier and correlated double sampling circuit 20
  • the signals for controlling the switching of the switches Sw 3 to Sw 5 may be the control signal of the column ADC 31 .
  • FIG. 8 illustrates an exemplary operation timing diagram.
  • the operation timing diagram of FIG. 8 may represent the timing of the circuit of FIG. 7 .
  • the analog data is read from the imaging element circuit 110 (N read operation, S+N read operation), and the analog-digital conversion (ADC) is performed on the analog data.
  • N read operation N read operation
  • S+N read operation S+N read operation
  • ADC analog-digital conversion
  • the circuit of FIG. 7 may read the analog signal from the sub-pixel 11 , for example, from the photodiode PD, based on one of the pixel control signals SLCT, RST, and TG according to the timing illustrated in FIG. 8 .
  • the correlated double sampling (CDS) processing is performed using the switching control signals to the switches Sw 1 and Sw 2
  • the analog-digital conversion is performed using the switching control signals to the switches Sw 3 to Sw 5 .
  • the capacitor C 3 coupled to a node n 2 , retains the signal.
  • the signals of eight lines from the sub-pixels are read in one horizontal time 1 H, the analog-digital conversion is performed on the read signals in seven horizontal times 7 H, and the signals are output.
  • Another configuration or operation of the circuit of FIG. 7 may be a configuration or an operation, for example, as disclosed in Japanese Laid-open Patent Publication No. 2006-21745.
  • the image sensor chip of FIG. 7 performs the CDS processing on the analog signal read from the pixel array 1 and analog-digital converts the CDS-processed signal to the analog signal.
  • the CDS processing may be performed using the analog signal read from the pixel array 1 after the analog-digital conversion is performed.
  • FIG. 9 illustrates an exemplary image sensor chip.
  • the CDS processing is performed after the analog-digital conversion is performed.
  • a preamplifier (Pre AMP) 250 amplifies the analog signal read from the pixel array 1 , and the column ADC circuit string 300 performs the analog-digital conversion on the analog signal.
  • the digital data converted by the column ADC circuit string 300 may be supplied to a DSP chip 750 located outside the image sensor chip 150 through a timing generator and data output buffer 350 .
  • the DSP chip 750 may include the Image Signal Processor (ISP).
  • the DSP chip 750 may write a noise level in a frame memory 800 to perform the correlated double sampling (CDS) processing.
  • the DSP chip 750 and the frame memory 800 may include the correlated double sampling (CDS) circuit.
  • the DSP chip 750 and the frame memory 800 which includes the CDS circuit, may be provided outside the image sensor chip 150 .
  • the DSP chip 750 and the frame memory 800 may be provided inside the image sensor chip 150 .
  • the CDS circuits 750 and 800 may be provided at an output side of the column ADC circuit string 300 that performs the analog-digital conversion on the analog signal read from the pixel array 1 .
  • FIG. 10 illustrates an exemplary operation timing diagram.
  • the operation timing diagram of FIG. 10 may represent the timing of the image sensor chip of FIG. 9 .
  • the pixel (sub-pixels) may be reset (pixel preceding reset). After the pixel is reset, the exposure operation may be performed, and the exposed signal may be read during the pixel signal read.
  • the noise level is read during the pixel preceding reset, and the column ADC string 300 performs the analog-digital conversion on the noise level data.
  • the digital-converted data is written in the frame memory 800 .
  • the pixel signal is read, and the DSP chip 750 performs the correlated double sampling.
  • the CDS circuit may be provided in front of the column ADC, or may be provided at an output side of the column ADC.

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JP2009018069A JP5365223B2 (ja) 2009-01-29 2009-01-29 撮像装置、撮像装置の信号処理方法およびイメージセンサチップ
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US20130270420A1 (en) * 2012-04-13 2013-10-17 Samsung Electronics Co., Ltd. Correlated double sampling circuit and image sensor including the same
CN103379292A (zh) * 2012-04-27 2013-10-30 索尼公司 信号处理设备及方法、成像设备和固态成像元件
US20220201233A1 (en) * 2018-12-06 2022-06-23 Canon Kabushiki Kaisha Photoelectric conversion device and imaging system

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US20130270420A1 (en) * 2012-04-13 2013-10-17 Samsung Electronics Co., Ltd. Correlated double sampling circuit and image sensor including the same
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