US20100109013A1 - Thin film transistor, method of manufacturing the same, and organic light emitting diode display device including the same - Google Patents

Thin film transistor, method of manufacturing the same, and organic light emitting diode display device including the same Download PDF

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US20100109013A1
US20100109013A1 US12/588,973 US58897309A US2010109013A1 US 20100109013 A1 US20100109013 A1 US 20100109013A1 US 58897309 A US58897309 A US 58897309A US 2010109013 A1 US2010109013 A1 US 2010109013A1
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layer
gate
interconnection
semiconductor layer
source
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US12/588,973
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Ji-Su Ahn
Sung-Chul Kim
Beong-Ju Kim
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Samsung Display Co Ltd
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Samsung Mobile Display Co Ltd
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Assigned to SAMSUNG MOBILE DISPLAY CO., LTD. reassignment SAMSUNG MOBILE DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AHN, JI-SU, KIM, BEONG-JU, KIM, SUNG-CHUL
Publication of US20100109013A1 publication Critical patent/US20100109013A1/en
Priority to US13/431,630 priority Critical patent/US8404529B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Non-limiting example embodiments relate to a thin film transistor (“TFT”), a method of manufacturing the same, and an organic light emitting diode (“OLED”) display device including the same. More particularly, non-limiting example embodiments relate to a TFT, which can prevent generated Joule heating from generating an arc during a conventional crystallization process.
  • TFT thin film transistor
  • OLED organic light emitting diode
  • Annealing methods used during a crystallization process generally include a furnace annealing method using a heat treatment furnace, a rapid thermal annealing (“RTA”) method using radiant heat, e.g., a halogen lamp, etc., a laser annealing method using a laser, an annealing method using Joule heating, and so on.
  • RTA rapid thermal annealing
  • an appropriate annealing method for the crystallization process is determined based on characteristics of material and process contemplated. Some of the factors to be considered in the selection of an appropriate annealing method are a range of an annealing temperature, uniformity of the annealing temperature, a heating rate, a cooling rate, purchase price, and maintenance cost.
  • a selection of annealing method becomes very limited when high temperature annealing or high rate annealing only in a local region of a material is needed.
  • the laser annealing method can rapidly anneal a surface of a material
  • the laser annealing method has only limited applicability since the applicability of the heat treatment is determined by a wavelength of a laser and the kind of materials requiring the heat treatment.
  • the laser annealing method requires expensive equipment, and thus, increasing maintenance cost.
  • the RTA method is widely applied to a semiconductor manufacturing process. With current technology, however, RTA method can be applied only to a silicon wafer having a diameter of 300 mm or less. The RTA method cannot be applied to a silicon wafer having a diameter larger than 300 mm because RTA method cannot uniformly anneal the silicon wafer having a diameter larger than 300 mm. Further, since a maximum heating rate of the heat treatment is 400° C./sec, it is hard to use the RTA method in a process requiring a higher heating rate than 400° C./sec.
  • Non-limiting example embodiments are therefore directed to a TFT, a method of manufacturing the same, and an OLED display device including the same, which substantially overcome one or more of the disadvantages of the related art.
  • a TFT including a substrate having a pixel portion and an interconnection portion, a buffer layer on the substrate; a gate electrode and a gate interconnection on the buffer layer, wherein the gate electrode is located at the pixel portion and the gate interconnection is located at the interconnection portion, a gate insulating layer on the entire substrate, a semiconductor layer on the gate electrode, source and drain electrodes electrically connected to the semiconductor layer, and a metal pattern disposed on the gate interconnection.
  • the metal pattern and the source and drain electrodes may include the same material.
  • the source and drain electrodes and the metal pattern may include one or more of molybdenum (Mo), chromium (Cr), tungsten (W), molybdenum-tungsten (MoW), aluminum (Al), aluminum-neodymium (Al—Nd), titanium (Ti), titanium nitride (TiN), copper (Cu), a molybdenum (Mo) alloy, an aluminum (Al) alloy, and a copper (Co) alloy. These may be used alone or in a combination thereof.
  • the TFT may further include an impurity-doped silicon layer formed between the semiconductor layer and the source and drain electrodes.
  • An insulating layer may be formed on the gate insulating layer.
  • the gate interconnection may be in direct contact with the metal pattern.
  • the TFT may further include the semiconductor layer, which may be a polysilicon layer.
  • a method of manufacturing a thin film transistor including providing a substrate having a pixel portion and a peripheral portion, forming a buffer layer on the substrate, forming a gate electrode and a gate interconnection on the buffer layer, wherein the gate electrode is located at the pixel portion and a gate interconnection is located at the peripheral portion, forming a gate insulating layer on the gate electrode and the gate interconnection, forming an amorphous semiconductor layer and patterning the amorphous semiconductor layer to form a semiconductor layer pattern on the gate electrode of the pixel portion, forming a metal layer on the substrate to be electrically connected to the semiconductor layer pattern and the gate interconnection, applying an electric field to the metal layer to crystallize the semiconductor layer pattern to form a semiconductor layer, and patterning the metal layer to form source and drain electrodes electrically connected to the semiconductor layer of the pixel portion and a metal pattern on the gate interconnection.
  • the metal pattern may be in direct contact with the gate interconnection.
  • the electric current may be generated by applying an electrical field of about 100 V/cm 2 to about 10,000 V/cm 2 to the metal layer.
  • the metal layer may be formed on the substrate to a thickness of about 50 nm to about 200 nm.
  • the metal layer may include one or more of molybdenum (Mo), chromium (Cr), tungsten (W), molybdenum-tungsten (MoW), aluminum (Al), aluminum-neodymium (Al—Nd), titanium (Ti), titanium nitride (TiN), copper (Cu), a molybdenum (Mo) alloy, an aluminum (Al) alloy, and a copper (Co) alloy. These may be used alone or in a combination thereof.
  • the impurity-doped silicon layer may be formed between the semiconductor layer and the source and drain electrodes.
  • an OLED display device including OLEDs configured to emit light, and TFTs coupled to the OLEDs, each TFT including a substrate having a pixel portion and an interconnection portion, a buffer layer on the substrate, a gate electrode and a gate interconnection portion on the buffer layer, wherein the gate electrode is located at the pixel portion and the gate interconnection is located at the interconnection portion, a gate insulating layer on the substrate, a semiconductor layer on the gate electrode, source and drain electrodes electrically connected to the semiconductor layer, an insulating layer on the substrate, a first electrode, source and drain electrodes, an organic layer and a second layer on the insulating layer, wherein the first electrode is electrically connected to the source and drain electrodes, the organic layer and the second layer, and a metal pattern on the gate interconnection.
  • the metal pattern may include the same material as the source and drain electrodes.
  • the source and drain electrodes and the metal pattern may include one or more of molybdenum (Mo), chromium (Cr), tungsten (W), molybdenum-tungsten (MoW), aluminum (Al), aluminum-neodymium (Al—Nd), titanium (Ti), titanium nitride (TiN), copper (Cu), a molybdenum (Mo) alloy, an aluminum (Al) alloy, and a copper (Co) alloy. These may be used alone or in a combination thereof.
  • the OLED display device may further include an impurity-doped silicon layer between the semiconductor layer and the source and drain electrodes.
  • the semiconductor layer may be a polysilicon layer.
  • the OLED display device may further include an insulating layer on the gate insulating layer.
  • the gate interconnection may be in direct contact with the metal pattern.
  • FIGS. 1A to 1E illustrate cross-sectional views of stages in a method of manufacturing a TFT in accordance with a non-limiting example embodiment of the present invention.
  • FIG. 2 illustrates a cross-sectional view of an OLED display device in accordance with a non-limiting example embodiment of the present invention.
  • Non-limiting example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the non-limiting example embodiments set forth herein. Rather, these non-limiting example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
  • each of the expressions “at least one,” “one or more,” and “and/or” are open-ended expressions that are both conjunctive and disjunctive in operation.
  • each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C” and “A, B, and/or C” includes the following meanings: A alone; B alone; C alone; both A and B together; both A and C together; both B and C together; and all three of A, B, and C together.
  • FIGS. 1A to 1E illustrate cross-sectional views of stages in a method of manufacturing a TFT in accordance with a non-limiting example embodiment of the present invention.
  • a substrate 100 including a pixel portion a and an interconnection portion “b” is prepared, and a buffer layer 110 is formed on the substrate 100 .
  • the substrate 100 may include, e.g., a transparent material such as glass or plastic.
  • the buffer layer 110 may prevent or reduce diffusion of moisture or impurities generated from the substrate 100 , and/or may adjust a heat transfer rate during crystallization to facilitate crystallization of the amorphous silicon layer.
  • the buffer layer 110 may be formed in a single layer or in a multi-layer structure including an insulating layer, e.g., a silicon oxide layer or a silicon nitride layer.
  • the gate electrode metal layer 120 a may be a single layer including aluminum or an aluminum alloy, e.g., aluminum-neodymium (Al—Nd), or a multi-layer in which an aluminum alloy is deposited on a chromium (Cr) or molybdenum (Mo) alloy. These may be used alone or in a combination thereof.
  • Al—Nd aluminum-neodymium
  • Mo molybdenum
  • the gate electrode metal layer 120 a is patterned to form a gate electrode 120 located at the pixel portion of the substrate 100 and a gate interconnection 125 located at the interconnection portion “b” of the substrate 100 .
  • a gate insulating layer 130 may be formed on the substrate 100 .
  • the gate insulating layer 130 may be a silicon oxide layer, a silicon nitride layer, or a combination thereof.
  • an amorphous semiconductor layer 140 ′ (not shown), e.g., amorphous silicon, may be formed on the substrate 100 having the gate electrode 120 , and then, patterned to form a semiconductor layer pattern 140 a corresponding to the gate electrode 120 .
  • a portion of the gate insulating layer 130 in the interconnection portion “b” of the substrate may be removed to form an opening 130 a to partially expose the gate interconnection 125 .
  • a metal layer 150 a may be formed on the substrate 100 . Then, an electric field is applied to heat the metal layer 150 a . As the result, heat of the heated metal layer 150 a is transferred to crystallize the semiconductor layer pattern 140 a formed using an amorphous semiconductor layer (not shown) disposed thereunder, and a semiconductor layer 140 is thereby formed of, e.g., a polysilicon.
  • the metal layer 150 a is directly connected to the semiconductor layer 140 , it is more advantageous to crystallization.
  • the metal layer 150 a is directly connected to the gate interconnection 125 , it is possible to prevent generation of arc during crystallization and reduce defective goods.
  • an electric field of about 100 V/cm 2 to about 10,000 V/cm 2 is applied for about 1 ⁇ sec to about 1 sec.
  • the electric field of less than about 100 V/cm 2 may not generate sufficient current for Joule heating to perform crystallization, while the electric field of more than about 10,000 V/cm 2 may generate a local arc.
  • the electric field when the electric field is applied for less than about 1 ⁇ sec, the crystallization may not be readily performed due to the insufficient Joule heating.
  • the electric field is applied for more than about 1 sec, so much heat may be generated that the substrate may be bent, or may form a defect along the edge as heat transfers during crystallization.
  • the metal layer 150 a may be patterned to form source and drain electrodes 150 s and 150 d .
  • metal pattern 150 c may remain in the opening 130 a and connected to the gate interconnection 125 in the interconnection portion “b” of the substrate.
  • a silicon layer (not shown) doped with N-type or P-type impurities may be further disposed between the semiconductor layer 140 and the source and drain electrodes 150 s and 150 d.
  • the metal layer 150 a may have a thickness sufficient to form the source and drain electrodes 150 s and 150 d , preferably, about 50 nm to about 200 nm. When the thickness is less than about 50 nm, the metal layer 150 a may not be uniformly formed, and thus, heat transfer may not be even, resulting uneven crystallization. When the thickness of the metal layer 150 a is greater than about 200 nm, the source and drain electrodes 150 s and 150 d may not be thick enough for a thin film device. Therefore, when the layer 150 a is patterned to form the source and drain electrodes, the electrode having a thickness of 200 nm or less, but greater than 50 nm, is appropriate for an electrode used in a TFT.
  • the metal layer 150 a may include one or more of molybdenum (Mo), chromium (Cr), tungsten (W), molybdenum-tungsten (MoW), aluminum (Al), aluminum-neodymium (Al—Nd), titanium (Ti), titanium nitride (TiN), copper (Cu), a molybdenum (Mo) alloy, an aluminum (Al) alloy, and a copper (Co) alloy. These may be used alone or in a combination thereof.
  • FIG. 2 illustrates a cross-sectional view of an OLED device having a TFT in accordance with a non-limiting example embodiment of the present invention.
  • an insulating layer 170 may be formed on the substrate 100 including the TFT formed in accordance with the non-limiting example embodiment described in FIG. 1E .
  • the insulating layer 170 may be an inorganic layer, e.g., a silicon oxide layer, a silicon nitride layer, and silicate on glass, or an organic layer, e.g., polyimide, benzocyclobutene series resin, and acrylate.
  • the insulating layer 170 may be formed in a stacked structure of the inorganic layer and the organic layer.
  • the insulating layer 170 may be etched to form a via-hole exposing the source or drain electrode 150 s or 150 d .
  • a first electrode 180 may be connected to one of the source and drain electrodes 150 s and 150 d through the via-hole.
  • the first electrode 180 may be an anode or a cathode.
  • the anode may be a transparent conductive layer including, e.g., indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).
  • the cathode may include, e.g., Mg, Ca, Al, Ag, Ba, or an alloy thereof. These may be used alone or in a combination thereof.
  • a pixel defining layer 185 having an opening exposing a portion of the surface of the first electrode 180 may be formed on the first electrode 180 , and an organic layer 190 including an emission layer is formed on the exposed first electrode 180 .
  • the organic layer 190 may further include at least one of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron injection layer, and an electron transport layer.
  • a second layer 195 may be formed on the organic layer 190 , thereby completing an OLED display device in accordance with a non-limiting example embodiment of the present invention.
  • a rapid annealing method that applies an electrical field to a conductive layer and generates Joule heat, it may be possible to rapidly anneal a selected material by transferring high heat. This is desirable, as the rapid annealing method may have a much higher heating rate than that of the conventional RTA method. Such a rapid annealing method, however, may introduce physical defects to the substrate from an arc generated during the Joule heating. Thus, according to non-limiting example embodiments, as the result of a metal layer being directly connected to the gate interconnection, an occurrence of an arc caused by Joule heat during the crystallization operation may be prevented. Thus, defects may be reduced, and production yield may be improved.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Recrystallisation Techniques (AREA)
US12/588,973 2008-11-04 2009-11-04 Thin film transistor, method of manufacturing the same, and organic light emitting diode display device including the same Abandoned US20100109013A1 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
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US20120181544A1 (en) * 2011-01-14 2012-07-19 Yeon-Hwa Lee Organic light-emitting display device
US8643019B2 (en) 2010-12-08 2014-02-04 Samsung Display Co., Ltd. Organic light emitting display device and manufacturing method for the same
US20140103308A1 (en) * 2012-10-12 2014-04-17 Samsung Display Co., Ltd. Organic light emitting diode and organic light emitting diode display
US20140332759A1 (en) * 2013-05-13 2014-11-13 Infineon Technologies Dresden Gmbh Electrode, an electronic device, and a method for manufacturing an optoelectronic device
US20150147839A1 (en) * 2013-11-26 2015-05-28 Infineon Technologies Dresden Gmbh Method for manufacturing a semiconductor device

Families Citing this family (7)

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Publication number Priority date Publication date Assignee Title
KR101056427B1 (ko) * 2009-08-13 2011-08-11 삼성모바일디스플레이주식회사 박막트랜지스터의 제조방법 및 그를 포함하는 유기전계발광표시장치의 제조방법
KR101041144B1 (ko) * 2009-08-13 2011-06-13 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법 및 그를 포함하는 유기전계발광표시장치
US9698173B2 (en) * 2014-08-24 2017-07-04 Royole Corporation Thin film transistor, display, and method for fabricating the same
CN105140178B (zh) * 2015-07-24 2018-03-27 深圳市华星光电技术有限公司 有机薄膜晶体管阵列基板及其制作方法
TWI601301B (zh) * 2015-07-31 2017-10-01 友達光電股份有限公司 光學偵測裝置及其製作方法
KR102708594B1 (ko) * 2016-09-07 2024-09-23 삼성디스플레이 주식회사 표시 장치
KR20200089789A (ko) * 2019-01-17 2020-07-28 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933296A (en) * 1985-08-02 1990-06-12 General Electric Company N+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays
US5156986A (en) * 1990-10-05 1992-10-20 General Electric Company Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
US5362660A (en) * 1990-10-05 1994-11-08 General Electric Company Method of making a thin film transistor structure with improved source/drain contacts
US5602047A (en) * 1996-06-13 1997-02-11 Industrial Technology Research Institute Process for polysilicon thin film transistors using backside irradiation and plasma doping
US6197624B1 (en) * 1997-08-29 2001-03-06 Semiconductor Energy Laboratory Co., Ltd. Method of adjusting the threshold voltage in an SOI CMOS
US20070075313A1 (en) * 2005-09-30 2007-04-05 Won-Kyu Kwak Flat panel display device
US20090042342A1 (en) * 2006-03-03 2009-02-12 Ensiltech Co., Ltd. Method for crystallization of amorphous silicon by joule heating

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01259322A (ja) * 1988-04-11 1989-10-17 Hitachi Ltd 薄膜半導体スイッチング素子マトリックス基板とその製造方法及びそれを用いた画像表示装置
JP3573778B2 (ja) * 1993-03-12 2004-10-06 株式会社東芝 液晶表示装置
JPH10319438A (ja) * 1997-05-23 1998-12-04 Sharp Corp アクティブマトリクス基板、その製造方法およびその欠陥修正方法
JP3031300B2 (ja) * 1997-06-20 2000-04-10 日本電気株式会社 液晶表示装置の製造方法
KR100729942B1 (ko) * 2004-09-17 2007-06-19 노재상 도전층을 이용한 실리콘 박막의 어닐링 방법 및 그로부터제조된 다결정 실리콘 박막
WO2006098513A1 (ja) * 2005-03-18 2006-09-21 National University Corporation Tokyo University Of Agriculture And Technology 熱処理方法及び半導体の結晶化方法
JP5100070B2 (ja) * 2005-09-22 2012-12-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5416881B2 (ja) * 2005-10-18 2014-02-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4277874B2 (ja) * 2006-05-23 2009-06-10 エプソンイメージングデバイス株式会社 電気光学装置の製造方法
KR101275009B1 (ko) * 2006-06-09 2013-06-13 주식회사 엔씰텍 주울 가열에 의한 급속 열처리시 아크 발생을 방지하는방법
KR101245225B1 (ko) * 2006-06-22 2013-03-19 엘지디스플레이 주식회사 박막트랜지스터 기판 및 그 제조 방법
JP5578509B2 (ja) * 2006-09-06 2014-08-27 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ エラストマ基板に伸縮性コンポーネントを接着する方法
KR100822216B1 (ko) * 2007-04-09 2008-04-16 삼성에스디아이 주식회사 박막 트랜지스터 기판, 이를 포함한 유기 발광 표시장치 및유기 발광 표시장치의 제조방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933296A (en) * 1985-08-02 1990-06-12 General Electric Company N+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays
US5156986A (en) * 1990-10-05 1992-10-20 General Electric Company Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration
US5362660A (en) * 1990-10-05 1994-11-08 General Electric Company Method of making a thin film transistor structure with improved source/drain contacts
US5602047A (en) * 1996-06-13 1997-02-11 Industrial Technology Research Institute Process for polysilicon thin film transistors using backside irradiation and plasma doping
US6197624B1 (en) * 1997-08-29 2001-03-06 Semiconductor Energy Laboratory Co., Ltd. Method of adjusting the threshold voltage in an SOI CMOS
US20070075313A1 (en) * 2005-09-30 2007-04-05 Won-Kyu Kwak Flat panel display device
US7838880B2 (en) * 2005-09-30 2010-11-23 Samsung Mobile Display Co., Ltd. Flat panel display device
US20090042342A1 (en) * 2006-03-03 2009-02-12 Ensiltech Co., Ltd. Method for crystallization of amorphous silicon by joule heating

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8643019B2 (en) 2010-12-08 2014-02-04 Samsung Display Co., Ltd. Organic light emitting display device and manufacturing method for the same
US20120181544A1 (en) * 2011-01-14 2012-07-19 Yeon-Hwa Lee Organic light-emitting display device
US8624259B2 (en) * 2011-01-14 2014-01-07 Samsung Display Co., Ltd. Organic light-emitting display device
US20140103308A1 (en) * 2012-10-12 2014-04-17 Samsung Display Co., Ltd. Organic light emitting diode and organic light emitting diode display
US9029897B2 (en) * 2012-10-12 2015-05-12 Samsung Display Co., Ltd. Organic light emitting diode and organic light emitting diode display
US20140332759A1 (en) * 2013-05-13 2014-11-13 Infineon Technologies Dresden Gmbh Electrode, an electronic device, and a method for manufacturing an optoelectronic device
US9419181B2 (en) * 2013-05-13 2016-08-16 Infineon Technologies Dresden Gmbh Electrode, an electronic device, and a method for manufacturing an optoelectronic device
US20150147839A1 (en) * 2013-11-26 2015-05-28 Infineon Technologies Dresden Gmbh Method for manufacturing a semiconductor device

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US8404529B2 (en) 2013-03-26
CN101740565A (zh) 2010-06-16
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TWI462301B (zh) 2014-11-21

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