US20090298397A1 - Method of grinding semiconductor wafers and device for grinding both surfaces of semiconductor wafers - Google Patents

Method of grinding semiconductor wafers and device for grinding both surfaces of semiconductor wafers Download PDF

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Publication number
US20090298397A1
US20090298397A1 US12/470,961 US47096109A US2009298397A1 US 20090298397 A1 US20090298397 A1 US 20090298397A1 US 47096109 A US47096109 A US 47096109A US 2009298397 A1 US2009298397 A1 US 2009298397A1
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United States
Prior art keywords
wafers
grinding
semiconductor wafers
area
centers
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Abandoned
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US12/470,961
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English (en)
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Yasunori Yamada
Yuichi Kakizono
Kazushige Takaishi
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Sumco Corp
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Sumco Corp
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Assigned to SUMCO CORPORATION reassignment SUMCO CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAKIZONO, YUICHI, TAKAISHI, KAZUSHIGE, YAMADA, YASUNORI
Publication of US20090298397A1 publication Critical patent/US20090298397A1/en
Abandoned legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/28—Work carriers for double side lapping of plane surfaces

Definitions

  • the present invention relates to a grinding method and a grinding device for semiconductor wafers. More particularly, it relates to a wafer grinding method and a wafer grinding device suited to large silicon wafers having a diameter of about 450 mm that employ a carrier to simultaneously grind both sides of a wafer between upper and lower surface plates.
  • workpieces semiconductor wafers
  • the number of workpieces varies based on factors such as increasing productivity relating to device size, work diameter and the like; specifications that take into account the work track and permeation of abrasive solution; and the like.
  • Planetary gear-type devices can be employed in such grinding of both surfaces of semiconductor wafers.
  • outer circumference sagging peripheral sagging
  • a method seeking to improve flatness through carrier design is proposed in Japanese Unexamined Patent Publication (KOKAI) No. 2002-254299, which is expressly incorporated herein by reference in its entirety.
  • This method is a technique (fixed dimension polishing) in which the thickness of a carrier is controlled with a high degree of precision so as to approach the final thickness of the work, to disperse stress acting on the outer circumference portion of the work into the carrier to obtain a flat work.
  • the present inventors conducted extensive research into the relation between semiconductor wafers as works and the stress that acts on the carrier holding the semiconductor wafers.
  • PCD circle radius
  • the spacing of the holes as the radius of a circle passing through the center of the holes in the carrier, and/or in which the spacing between works, was set to within a prescribed range, it was possible to evenly disperse the pressure from the surface plates in the surface of the wafers to prevent peripheral sagging of wafers without diminishing productivity and without shortening the service life of the carrier.
  • the solution that was discovered was in the form of a device for polishing both surfaces of semiconductor wafers including a pair of upper and lower rotating surface plates; a sun gear provided in a rotating center portion between the upper and lower rotating surface plates; a ring-shaped inner-toothed gear positioned on an outer circumference portion between the upper and lower rotating surface plates; and a carrier composed of a planetary gear, the planetary gear meshing with the inner-toothed gear and sun gear and being positioned between the upper and lower rotating surface plates, wherein the carrier has multiple holes serving as holes receiving wafers being polished, and centers of the multiple holes are positioned on a circumference of a single circle, with a ratio of an area of a circle passing through the centers of the multiple holes to an area of one of the wafers being polished greater than or equal to 1.33 but less than 2.0, and the above device is described in Japanese Unexamined Patent Publication (KOKAI) No. 2009-4616, published on Jan. 8, 2009, which is expressly incorporated herein by reference in its
  • a method of grinding semiconductor wafers including simultaneously polishing both surfaces of multiple semiconductor wafers being polished by rotating the multiple semiconductor wafers between a pair of upper and lower rotating surface plates in a state where the multiple semiconductor wafers are held on a carrier so that centers of the multiple semiconductor wafers are positioned on a circumference of a single circle, wherein a ratio of an area of a circle passing through the centers of the multiple semiconductor wafers to an area of one of the multiple semiconductor wafers is greater than or equal to 1.33 but less than 2.0, was also invented and a patent application relating to the above method was filed (identical to the above).
  • the size of the silicon wafers cut from single crystals of silicon is increasing in an about 10-year cycle. Device manufacturers hope to increase device manufacturing efficiency by increasing the size of the silicon wafers. In light of these circumstances, the manufacturing of silicon wafers with diameters of about 450 mm, about 1.5 times the current diameter of 300 mm, is planned for the near future.
  • Polishing of silicon wafers 450 mm in diameter will involve polishing of an area that is double or more that of conventional silicon wafers equal to or less than 300 mm in diameter. Thus, difficulty is anticipated in obtaining silicon wafers with the same flatness as in the past while maintaining production efficiency by the same method as before.
  • a non limiting aspect of the present invention provides for a method and device permitting the obtaining with good production efficiency of silicon wafers having the same degree of flatness as in the past despite an increased diameter.
  • the present inventors conducted extensive research into grinding large-diameter 450 mm silicon wafers—the next generation of silicon wafers—by adapting the semiconductor wafer polishing device of the above-cited patent application for use in grinding with fixed abrasive grains. As a result, it was discovered that conventional conditions for employing fixed abrasive grains caused clogging, precluding continuous grinding for extended periods. The present inventors conducted an extensive investigation into solving such clogging, and discovered a solution. A non-limiting feature of present invention was devised on that basis.
  • a first non-limiting aspect of the present invention relates to a method of grinding semiconductor wafers including:
  • a ratio of an area of a circle passing through the centers of the multiple semiconductor wafers to an area of one of the multiple semiconductor wafers is greater than or equal to 1.33 but less than 2.0;
  • a rotational speed of the multiple semiconductor wafers falls within a range of 5 to 80 rpm
  • the grinding of the multiple semiconductor wafers with the rotating surface plates are conducted with fixed abrasive grains in the presence of an alkali solution.
  • the alkali solution may have a pH ranging from 12 to 15.
  • the semiconductor wafers may have a diameter ranging from 400 to 500 mm.
  • the ratio of an area of a circle passing through the centers of the multiple semiconductor wafers to an area of one of the multiple semiconductor wafers may be greater than or equal to 1.33 but less than or equal to 1.5.
  • a second non-limiting aspect of the present invention relates to a device for grinding both surfaces of semiconductor wafers including:
  • a sun gear provided in a rotating center portion between the upper and lower rotating surface plates
  • a carrier composed of a planetary gear, the planetary gear meshing with the inner-toothed gear and sun gear and being positioned between the upper and lower rotating surface plates;
  • the carrier has multiple holes serving as holes receiving wafers being ground, and
  • centers of the multiple holes are positioned on a circumference of a single circle, with a ratio of an area of a circle passing through the centers of the multiple holes to an area of one of the wafers being ground greater than or equal to 1.33 but less than 2.0.
  • the ratio of an area of a circle passing through the centers of the multiple holes to an area of one of the wafers being ground may be greater than or equal to 1.33 but less than or equal to 1.5.
  • a non-limiting feature of present invention can provide a method and device permitting the obtaining with high production efficiency of silicon wafers having the same flatness as in the past despite an increased diameter.
  • FIG. 1 is a front view descriptive of an implementation embodiment of the semiconductor wafer grinding device according to the present invention
  • FIG. 2 is a plan view along section line A-A in FIG. 1 ;
  • FIG. 3 is a plan view descriptive of an implementation embodiment of the semiconductor wafer grinding method according to a non-limiting feature of the present invention and of the disposition of holes in a carrier.
  • a reference to a compound or component includes the compound or component by itself, as well as in combination with other compounds or components, such as mixtures of compounds.
  • the first non-limiting aspect of the present invention relates to a method of grinding semiconductor wafers including simultaneously grinding both surfaces of multiple semiconductor wafers being ground by rotating the multiple semiconductor wafers between a pair of upper and lower rotating surface plates in a state where the multiple semiconductor wafers are held on a carrier so that centers of the multiple semiconductor wafers are positioned on a circumference of a single circle, wherein a ratio of an area of a circle passing through the centers of the multiple semiconductor wafers to an area of one of the multiple semiconductor wafers is greater than or equal to 1.33 but less than 2.0; a rotational speed of the multiple semiconductor wafers falls within a range of 5 to 80 rpm; and the grinding of the multiple semiconductor wafers with the rotating surface plates are conducted with fixed abrasive grains in the presence of an alkali solution.
  • the method of grinding semiconductor wafers according to a non-limiting feature of the present invention can be carried out, for example, with the devise for grinding both surfaces of semiconductor wafers according to the second non-limiting aspect of the present invention.
  • the device includes a pair of upper and lower rotating surface plates including fixed abrasive grains; a sun gear provided in a rotating center portion between the upper and lower rotating surface plates; a ring-shaped inner-toothed gear positioned on an outer circumference portion between the upper and lower rotating surface plates; a carrier composed of a planetary gear, the planetary gear meshing with the inner-toothed gear and sun gear and being positioned between the upper and lower rotating surface plates; and an alkali solution feeding part, wherein the carrier has multiple holes serving as holes receiving wafers being ground, and centers of the multiple holes are positioned on a circumference of a single circle, with a ratio of an area of a circle passing through the centers of the multiple holes to an area of one of the wafers being ground greater than or equal to 1.33
  • the semiconductor wafer grinding method As for the semiconductor wafer grinding method according to a non-limiting feature of the present invention, details regarding the fact that the positions at which the wafers are held within the carrier are disposed so that the centers of the multiple wafers are positioned on a circumference of a single circle and the fact that the ratio of an area of a circle passing through the centers of the multiple wafers to an area of one of the multiple wafers is greater than or equal to 1.33 but less than 2.0 will be described, with the details of the above grinding device further below.
  • wafers are ground by rotating surface plates using fixed abrasive grains.
  • the rotational speed of the wafers being ground falls within a range of 5 to 80 rpm.
  • the above range of the rotational speed of the wafers being ground is specified for the following reasons.
  • the rotational speed of the wafers being ground is less than 5 rpm, grinding rate becomes low.
  • 80 rpm is exceeded, the wafer may jump.
  • wafers can be ground with fixed abrasive grains without lowering of the grinding rate and jumping of the wafer.
  • grinding debris is generated by the fixed abrasive grains.
  • grinding efficiency decreases.
  • grinding by rotating surface plates is conducted in the presence of an alkali solution.
  • the alkali solution employed in this process desirably has a pH of 12 to 15, which is more strongly alkaline than the alkali solution conventionally employed in lapping with free abrasive grains. The reason for using a strongly alkaline solution is to facilitate dissolution of Si (silicon) during processing.
  • the alkali solution is continuously or intermittently fed onto the surfaces ground by the rotating surface plates.
  • the quantity of alkali solution that is fed can be suitably determined by taking into account the rotational speed of the wafers being ground, the coarseness of the fixed abrasive grains, and the like; for example, 1 to 3 L/minute can be employed.
  • Examples of the alkali solution are hydroxides of alkali metals (Li, Na, K).
  • the surface plates employed to grind the semiconductor wafers may include grid-like pellets on surfaces of fixed abrasive grains facing the wafer surfaces.
  • Examples of such grinding-use surface plates are metal bonded grindstones and resin bonded grindstones containing diamond as the abrasive grain.
  • FIG. 1 is a front view describing the semiconductor wafer grinding device
  • FIG. 2 is a plan view along section line A-A in FIG. 1 .
  • the semiconductor wafer grinding device can be equipped with a horizontally supported ring-shaped lower surface plate (rotating surface plate) 1 , a ring-shaped upper surface plate (rotating surface plate) 2 opposing lower surface plate 1 from above, a sun gear 3 positioned to the inside of ring-shaped lower surface plate 1 , and a ring-shaped inner-toothed gear 4 positioned outside lower surface plate 1 .
  • a motor 11 drives rotation of lower surface plate 1 .
  • Upper surface plate 2 is suspended via a joint 6 from a cylinder 5 , and is driven to rotate in the opposite direction by a separate motor from the motor 11 driving lower surface plate 1 .
  • An alkali solution feeding part also referred to as a feeder, including a tank 7 for feeding alkali solution between upper surface plate 2 and lower surface plate 1 , is also provided.
  • Both sun gear 3 and inner-toothed gear 4 are independently driven to rotate by a motor 12 separate from the motors driving the surface plates.
  • Fixed abrasive grains are provided on the opposing surfaces of lower surface plate 1 and upper surface plate 2 .
  • Multiple carriers 8 are set on lower surface plate 1 so as to surround sun gear 3 .
  • the various carriers 8 that are set in place mesh to the inside with sun gear 3 and to the outside with inner-toothed gear 4 .
  • Holes 9 receiving semiconductor wafers (works or workpieces) 10 are provided eccentrically in each of the carriers 8 .
  • the thickness of each of carriers 8 is set to be either identical to the target value for the final finished thickness of wafers 10 , or to be slightly smaller.
  • multiple carriers 8 are set onto lower surface plate 1 with upper surface plate 2 in a raised state, and wafers 10 are set in holes 9 in each of the carriers 8 .
  • Upper surface plate 2 is lowered, and a prescribed pressure is applied to each of wafers 10 .
  • each of lower surface plate 1 , upper surface plate 2 , sun gear 3 , and inner-toothed gear 4 is rotated at a prescribed speed in a prescribed direction.
  • multiple carriers 8 between upper surface plate 1 and lower surface plate 2 undergo planetary motion, in which they revolve around sun gear 3 , while rotating.
  • the wafers 10 held on each of carriers 8 contact the fixed abrasive grains above and below in the presence of the alkali solution, simultaneously grinding both the upper and lower surfaces thereof.
  • the grinding conditions can be set so that both surfaces of wafers 10 are uniformly ground and all of multiple wafers 10 are uniformly ground.
  • the torque of motor 11 driving lower surface plate 1 or the torque of the motor driving upper surface plate 2 , can be monitored.
  • this torque drops by a preset ratio—10 percent, for example—after having assumed a stable level, upper surface plate 2 can be raised to finish grinding.
  • the final finished thickness of wafers 10 can be stably managed with high precision to be slightly thinner than or identical to the thickness of the carrier before grinding.
  • the material of the carriers 8 desirably has high resistance to abrasion and a low coefficient of friction with the fixed abrasive grains, and is desirably highly chemically resistant, for example, in pH 12 to 15 alkali solutions.
  • carrier materials satisfying such conditions are stainless steel, epoxy resin, phenol resin, and polyimide resin.
  • Further examples include but are not limited to FRPs (fiber-reinforced plastics) including such resins reinforced with a fiber such as glass fiber, carbon fiber, or aramid fiber. Since carriers 8 are employed to hold wafers 10 , they cannot decrease much in strength.
  • FIG. 3 is a plan view descriptive of the semiconductor wafer grinding method and disposition of holes in the carrier in the present implementation embodiment.
  • Multiple holes 9 are provided as shown in FIG. 3 in a carrier 8 ; there are three such spots in the present implementation embodiment.
  • the centers C 9 of each of the three holes 9 are positioned on the circumference of a circle P that is concentric with carrier 8 and disposed at equal intervals on circle P so as to be rotationally symmetric about a point relative to center CP (the center of carrier 8 ) of circle P.
  • the size of holes 9 is such that the ratio of the area of circle P passing through centers C 9 of holes 9 to the area of one of holes 9 , each of which is nearly equal in area to wafers 10 , is greater than or equal to 1.33 but less than 2.0, preferably greater than or equal to 1.33 but less than or equal to 1.5.
  • the radius R of circle P and the radius r of hole 9 are set so that:
  • the lower limit of the range specified by this area ratio need only be greater than or equal to 1.3333 . . . , and may be greater than or equal to 1.334.
  • a ratio of the area of circle P passing through the centers C 9 of holes 9 in carrier 8 to the area of one of holes 9 that falls below the above range is undesirable in that only two holes 9 can be provided within a carrier 8 , the wafers processed in a single carrier 8 cannot be uniformly processed, and no effect is realized in preventing sagging of wafers 10 .
  • An upper limit of the above ratio of areas of greater than or equal to 2 is undesirable in that when holes 9 are provided in three spots in carrier 8 , the distance between wafers 10 becomes excessive and no effect is realized in preventing sagging of wafers 10 .
  • An upper limit of the above ratio of areas of greater than or equal to 2 is undesirable in that when four or more holes 9 are provided in carrier 8 , the pressure that concentrates is not adequately dispersed, precluding a preventive effect on sagging of wafers 10 . Although sagging can be prevented when the upper limit of the above ratio of areas is set to greater than 1.5 but less than 2, less than or equal to 1.5 is desirable for obtaining finished product wafers of adequate flatness.
  • wafer 10 and hole 9 can be roughly identical. When wafer 10 is 200 mm in diameter, hole 9 can be 201 mm in diameter, and when wafer 10 is 300 mm in diameter, hole 9 can be 302 mm in diameter.
  • the use of carriers 8 , in which holes 9 are formed, to grind both surfaces of wafers 10 makes it possible to prevent peripheral sagging in wafers 10 and to manufacture polished wafers of a high degree of flatness.
  • reducing the distance between semiconductor wafers 10 that are being ground on both surfaces to bring wafers 10 close together makes it possible to grind each of the wafers 10 positioned in holes 9 in three spots on a single carrier 8 in a manner approaching that achieved when grinding a single wafer 10 .
  • it is possible to keep the length over which pressure concentrates to just part of the total length of the perimeter of a single wafer 10 that is, to reduce the concentration of pressure in the perimeter portion of wafer 10 from flexible pads on the surfaces of surface plates 1 and 2 due to the difference in thickness of wafer 10 and carrier 8 , resulting in reduction of portions significantly ground in the perimeter portion of wafer 10 .
  • three carriers 8 are configured. However, greater or fewer suitable numbers of carriers 8 are possible. Additionally, so long as the disposition of holes 9 or wafers 10 in each carrier 8 is configured as set forth above, various configurations of the grinding device are possible.
  • Wafer 10 can be a silicon wafer or a wafer of some other semiconducting material.
  • a non-limiting feature of present invention can be applied to wafers with diameters of 200 mm, 300 mm, as well as 450 mm or the like.
  • the method and device according to a non-limiting feature of the present invention are particularly suited to the grinding of large silicon wafers 400 to 500 mm in diameter.
  • Grinding devices configured as in the above implementation embodiment and carriers of different ratios of areas of circle P and holes 9 were prepared. These carriers were used to grind semiconductor wafers (silicon wafers) 10 and the flatness thereof was measured after grinding.
  • Wafer subjected to grinding 450 mm silicon wafer Grinding device: 20B dual-surface grinder made by Speed Fam Fixed abrasive grains: Diamond Alkali solution: pH 14 Grinding pressure: 200 g/cm 2 Carrier: Made of stainless steel Number of wafers ground: 5 carriers respectively having 3 holes (total 15 wafer batch) Area ratios of circle P to hole 9: 138%, 144%, 150%, 163%
  • TTV total thickness variation (micrometers)
  • ADE electrostatic capacitance surface flatness measuring device
  • the present invention is useful in the field of semiconductor wafer manufacturing.
US12/470,961 2008-05-28 2009-05-22 Method of grinding semiconductor wafers and device for grinding both surfaces of semiconductor wafers Abandoned US20090298397A1 (en)

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JP2008-139963 2008-05-28
JP2008139963A JP2009285768A (ja) 2008-05-28 2008-05-28 半導体ウェーハの研削方法および研削装置

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US8882565B2 (en) 2010-03-31 2014-11-11 Siltronic Ag Method for polishing a semiconductor wafer
US20150165585A1 (en) * 2012-06-25 2015-06-18 Sumco Corporation Method and apparatus for polishing work
US20170069502A1 (en) * 2014-03-14 2017-03-09 Shin-Etsu Handotai Co., Ltd. Manufacturing method of carrier for double-side polishing apparatus, carrier for double-side polishing apparatus, and double-side polishing method
CN109926873A (zh) * 2019-01-25 2019-06-25 辽宁科技大学 一种用于非导磁薄板类零件的研磨抛光装置及方法
CN111261542A (zh) * 2018-11-30 2020-06-09 有研半导体材料有限公司 一种碱腐蚀去除晶圆表面损伤的装置与方法
CN113231957A (zh) * 2021-04-29 2021-08-10 金华博蓝特电子材料有限公司 基于双面研磨设备的晶片研磨工艺及半导体晶片
CN113894635A (zh) * 2021-11-03 2022-01-07 安徽格楠机械有限公司 基于自学习的智能硅基晶圆超精密研磨抛光机

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CN117532480B (zh) * 2023-11-14 2024-04-16 苏州博宏源机械制造有限公司 一种晶圆双面抛光机的太阳轮调节装置

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Publication number Priority date Publication date Assignee Title
US8882565B2 (en) 2010-03-31 2014-11-11 Siltronic Ag Method for polishing a semiconductor wafer
DE102010063179A1 (de) 2010-12-15 2012-06-21 Siltronic Ag Verfahren zur gleichzeitigen Material abtragenden Bearbeitung beider Seiten mindestens dreier Halbleiterscheiben
KR101300343B1 (ko) 2010-12-15 2013-08-28 실트로닉 아게 적어도 3개의 반도체 웨이퍼의 양면을 동시에 재료 제거 처리하는 방법
US8801500B2 (en) 2010-12-15 2014-08-12 Siltronic Ag Method for the simultaneous material-removing processing of both sides of at least three semiconductor wafers
US20150165585A1 (en) * 2012-06-25 2015-06-18 Sumco Corporation Method and apparatus for polishing work
US9289876B2 (en) * 2012-06-25 2016-03-22 Sumco Corporation Method and apparatus for polishing work
US20170069502A1 (en) * 2014-03-14 2017-03-09 Shin-Etsu Handotai Co., Ltd. Manufacturing method of carrier for double-side polishing apparatus, carrier for double-side polishing apparatus, and double-side polishing method
CN111261542A (zh) * 2018-11-30 2020-06-09 有研半导体材料有限公司 一种碱腐蚀去除晶圆表面损伤的装置与方法
CN109926873A (zh) * 2019-01-25 2019-06-25 辽宁科技大学 一种用于非导磁薄板类零件的研磨抛光装置及方法
CN113231957A (zh) * 2021-04-29 2021-08-10 金华博蓝特电子材料有限公司 基于双面研磨设备的晶片研磨工艺及半导体晶片
CN113894635A (zh) * 2021-11-03 2022-01-07 安徽格楠机械有限公司 基于自学习的智能硅基晶圆超精密研磨抛光机

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