US20070146021A1 - Frequency divider - Google Patents
Frequency divider Download PDFInfo
- Publication number
- US20070146021A1 US20070146021A1 US10/576,554 US57655404A US2007146021A1 US 20070146021 A1 US20070146021 A1 US 20070146021A1 US 57655404 A US57655404 A US 57655404A US 2007146021 A1 US2007146021 A1 US 2007146021A1
- Authority
- US
- United States
- Prior art keywords
- flip
- input
- flop
- frequency divider
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
- H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/54—Ring counters, i.e. feedback shift register counters
- H03K23/542—Ring counters, i.e. feedback shift register counters with crossed-couplings, i.e. Johnson counters
Definitions
- the invention relates to a frequency divider.
- Frequency dividers are well-known and widely-used devices in applications as Phase Locked Loops (PLLs), prescalers, digital receivers. Normally a frequency divider requires flip-flops coupled in a convenient manner for obtaining a desired frequency division.
- PLLs Phase Locked Loops
- prescalers prescalers
- digital receivers Normally a frequency divider requires flip-flops coupled in a convenient manner for obtaining a desired frequency division.
- the actual trends in semiconductor technology is shrinking transistors size for improving the speed of the circuits and downsize the supply voltages for the integrated circuits for reducing a dissipation power of the chips.
- U.S. Pat. No. 6,424,194 describes ultra high-speed circuits using current-controlled CMOS (C 3 MOS) logic fabricated in conventional CMOS process technology.
- C 3 MOS current-controlled CMOS
- An entire family of logic elements including inverters/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C 3 MOS techniques.
- Optimum balance between power consumption and speed for each circuit application is achieved by combining C 3 MOS logic with low power conventional CMOS logic.
- the combined C 3 MOS/CMOS logic allows greater integration of circuits such as high-speed transceivers used in fiber optic communication systems.
- circuits presented in the above-mentioned patent still use at least two stacked transistors, which make them less suitable for relative low-voltage (1.2, 0.9 or 0.7 V) supply applications.
- the threshold voltages of the upper transistors increase due to the back-bias effect.
- the upper transistors do not have maximum gain and maximum speed of operation.
- the frequency divider comprises a first flip-flop having a first clock input for receiving a clock signal, a first data input and a first output.
- the divider further comprises a second flip-flop having a second clock input for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input, a second data input coupled to the first output.
- the second flip-flop further comprises a second output and a third output, the second and third outputs (Q 2 , Qa 2 ) providing signals that are mutually in anti-phase.
- the third output is coupled to the first data input.
- a period of the clock signal is of the same order of magnitude as a delay through an inverted stage of the divider.
- a prior art frequency divider is shown in FIG. 2 . It comprises first and second flip-flops, each flip-flop, each of them being implemented as shown in FIG. 1 .
- transistors M 1 and M 2 implement a R-S flip-flop, which is controlled by a clock signal having two components that are mutually in anti-phase Cl and Cl , respectively.
- An input signal D is inputted via a controlled inverter M 5 , M 6 to an input of the flip-flop.
- Two flip-flops of this kind are coupled as in FIG. 2 for providing a frequency divider.
- the controlled inverter M 5 , M 6 delays the signal with a time delay depending on its geometry and on the technology used for its implementation.
- the signals whose frequency needs to be divided have a period in the same range as the delay through the inverter M 5 , M 6 , the signal cannot be transmitted from the input of the controlled inverter to its output.
- the controlled inverter M 5 , M 6 at the input limits the maximum frequency, which may be divided.
- the present invention is based on the inventive recognition that inverting the phase of the feedback signal from the second flip-flop allows for an elimination of the inverter M 5 , M 6 and contributes to an increase of the maximum frequency of input signals, which are divided with this frequency divider.
- a controllable switch is coupled to the first data input and to the third output.
- the controllable switch is controlled by a clock signal driving the first flip-flop.
- controllable switch is coupled to the third output via resistive means.
- the resistive means reduces the current supplied to the input of the first flip-flop and the loading due to the input impedance of the first flip-flop. As a direct consequence, the consummated power is reduced.
- FIG. 1 depicts a prior-art R-S flip-flop
- FIG. 2 depicts a frequency divider using a prior-art flip-flop
- FIG. 3 depicts a frequency divider according to an embodiment of the invention.
- FIG. 4 depicts a frequency divider according to another embodiment of the invention.
- FIG. 3 depicts a frequency divider according to an embodiment of the invention.
- the frequency divider comprises a first flip-flop M 1 , M 2 , M 3 , M 4 having a first clock input Cl for receiving a clock signal.
- the flip-flop further comprises a first set input Q 4 and a first non-inverted output Q 1 .
- the frequency divider further comprises a second flip-flop M 1 ′, M 2 ′, M 3 ′, M 4 ′ having a second clock input Cl for receiving a second clock signal that is substantially in anti-phase with the clock signal inputted into the first clock input Cl , a second set input coupled to the first non-inverted output Q 1 , a second non-inverted output Q 2 and a second inverted output Q 2 , the second inverted output Q 2 being coupled to the first set input Q 4 .
- a period of the clock signal is of the same order of magnitude as a delay through an inverter stage of the divider.
- CML Current Mode Logic
- SCL Source Coupled Logic
- the input of the first flip-flop is coupled to the inverted output Q 2 of the second flip-flop, which provides a signal substantially in anti-phase i.e. phase shifted over 180 degrees with respect to the signal provided by the second output Q 2 .
- a controllable switch M 7 is coupled to the first data input Q 4 and to the third output Qa 2 .
- the switch is controlled by a clock signal driving the first flip-flop M 1 , M 2 , M 3 , M 4 .
- the maximum frequency of operation is increased when compared with the state of the art divider because the delay through the switch is smaller than the delay through two transistors implementing the controlled inverter.
- the controllable switch M 7 may be coupled to the third output Qa 2 via resistor R.
- the resistor R reduces the current supplied to the input of the first flip-flop and the loading due to the input impedance of the first flip-flop. As a direct consequence, the consummated power is reduced.
- pairs of transistors M 1 , M 4 ; and M 2 , M 3 in FIGS. 1-4 are in fact controlled inverters.
Landscapes
- Manipulation Of Pulses (AREA)
- Soil Working Implements (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03103937.3 | 2003-10-23 | ||
EP03103937 | 2003-10-23 | ||
PCT/IB2004/052080 WO2005041413A1 (en) | 2003-10-23 | 2004-10-13 | Frequency divider |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070146021A1 true US20070146021A1 (en) | 2007-06-28 |
Family
ID=34486350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/576,554 Abandoned US20070146021A1 (en) | 2003-10-23 | 2004-10-13 | Frequency divider |
Country Status (8)
Country | Link |
---|---|
US (1) | US20070146021A1 (de) |
EP (1) | EP1678829B1 (de) |
JP (1) | JP4719843B2 (de) |
CN (1) | CN1871772B (de) |
AT (1) | ATE465550T1 (de) |
DE (1) | DE602004026760D1 (de) |
TW (1) | TWI381641B (de) |
WO (1) | WO2005041413A1 (de) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9647669B1 (en) | 2016-07-18 | 2017-05-09 | Texas Instruments Incorporated | High speed frequency divider |
US9705507B1 (en) | 2016-05-19 | 2017-07-11 | Texas Instruments Incorporated | Fixed frequency divider circuit |
US10855294B2 (en) | 2016-11-08 | 2020-12-01 | Texas Instruments Incorporated | High linearity phase interpolator |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101630957B (zh) * | 2008-07-16 | 2011-07-06 | 中国科学院微电子研究所 | 具有自适应休眠的双模预分频器 |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4356411A (en) * | 1978-12-12 | 1982-10-26 | Tokyo Shibaura Denki Kabushiki Kaisha | Flip-flop circuit |
US4568843A (en) * | 1982-06-29 | 1986-02-04 | Thomson Csf | Bistable logic device, operating from DC to 10 GHz, and frequency divider including this bistable device |
US4791315A (en) * | 1987-06-04 | 1988-12-13 | Cherry Semiconductor Corporation | Cross-coupled latch |
US4806786A (en) * | 1987-11-02 | 1989-02-21 | Motorola, Inc. | Edge set/reset latch circuit having low device count |
US5541544A (en) * | 1993-09-24 | 1996-07-30 | Mitsubishi Denki Kabushiki Kaisha | Bipolar flip-flop circuit with improved noise immunity |
US5907589A (en) * | 1997-04-10 | 1999-05-25 | Motorola, Inc. | GHZ range frequency divider in CMOS |
US6140845A (en) * | 1998-12-04 | 2000-10-31 | The Texas A&M University System | Pseudo-dynamic differential flip-flop |
US6166571A (en) * | 1999-08-03 | 2000-12-26 | Lucent Technologies Inc. | High speed frequency divider circuit |
US6268752B1 (en) * | 1999-07-15 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Master-slave flip-flop circuit |
US6424194B1 (en) * | 1999-06-28 | 2002-07-23 | Broadcom Corporation | Current-controlled CMOS logic family |
US6657472B1 (en) * | 2002-04-25 | 2003-12-02 | Cypress Semiconductor Corp. | Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch |
US20050156643A1 (en) * | 2000-02-22 | 2005-07-21 | Karl Edwards | High-speed, current-driven latch |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA929609A (en) * | 1971-11-19 | 1973-07-03 | K. Au Kenneth | Single-channel mis flip-flop circuit |
JPS55145439A (en) * | 1979-04-27 | 1980-11-13 | Toshiba Corp | Input control type binary counter circuit |
JPS57180224A (en) * | 1981-04-28 | 1982-11-06 | Toshiba Corp | Flip-flop circuit |
DE3546132A1 (de) * | 1985-12-24 | 1987-07-02 | Ant Nachrichtentech | Schaltungsanordnung zur erzeugung zweier takte |
JPS63114409A (ja) * | 1986-10-31 | 1988-05-19 | Hitachi Ltd | フリツプフロツプ回路 |
JPS6352512A (ja) * | 1986-08-22 | 1988-03-05 | Hitachi Ltd | フリツプフロツプ回路 |
GB2198603A (en) * | 1986-12-05 | 1988-06-15 | Philips Electronic Associated | Divider circuit |
GB2354383A (en) * | 1999-09-17 | 2001-03-21 | Sony Uk Ltd | Dual loop phase-locked loop |
-
2004
- 2004-10-13 JP JP2006536233A patent/JP4719843B2/ja not_active Expired - Fee Related
- 2004-10-13 CN CN2004800309908A patent/CN1871772B/zh not_active Expired - Fee Related
- 2004-10-13 US US10/576,554 patent/US20070146021A1/en not_active Abandoned
- 2004-10-13 WO PCT/IB2004/052080 patent/WO2005041413A1/en active Application Filing
- 2004-10-13 AT AT04770247T patent/ATE465550T1/de not_active IP Right Cessation
- 2004-10-13 EP EP04770247A patent/EP1678829B1/de not_active Ceased
- 2004-10-13 DE DE602004026760T patent/DE602004026760D1/de active Active
- 2004-10-20 TW TW093131889A patent/TWI381641B/zh not_active IP Right Cessation
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4356411A (en) * | 1978-12-12 | 1982-10-26 | Tokyo Shibaura Denki Kabushiki Kaisha | Flip-flop circuit |
US4568843A (en) * | 1982-06-29 | 1986-02-04 | Thomson Csf | Bistable logic device, operating from DC to 10 GHz, and frequency divider including this bistable device |
US4791315A (en) * | 1987-06-04 | 1988-12-13 | Cherry Semiconductor Corporation | Cross-coupled latch |
US4806786A (en) * | 1987-11-02 | 1989-02-21 | Motorola, Inc. | Edge set/reset latch circuit having low device count |
US5541544A (en) * | 1993-09-24 | 1996-07-30 | Mitsubishi Denki Kabushiki Kaisha | Bipolar flip-flop circuit with improved noise immunity |
US5907589A (en) * | 1997-04-10 | 1999-05-25 | Motorola, Inc. | GHZ range frequency divider in CMOS |
US6140845A (en) * | 1998-12-04 | 2000-10-31 | The Texas A&M University System | Pseudo-dynamic differential flip-flop |
US6424194B1 (en) * | 1999-06-28 | 2002-07-23 | Broadcom Corporation | Current-controlled CMOS logic family |
US6268752B1 (en) * | 1999-07-15 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Master-slave flip-flop circuit |
US6166571A (en) * | 1999-08-03 | 2000-12-26 | Lucent Technologies Inc. | High speed frequency divider circuit |
US20050156643A1 (en) * | 2000-02-22 | 2005-07-21 | Karl Edwards | High-speed, current-driven latch |
US6657472B1 (en) * | 2002-04-25 | 2003-12-02 | Cypress Semiconductor Corp. | Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9705507B1 (en) | 2016-05-19 | 2017-07-11 | Texas Instruments Incorporated | Fixed frequency divider circuit |
US9647669B1 (en) | 2016-07-18 | 2017-05-09 | Texas Instruments Incorporated | High speed frequency divider |
US10855294B2 (en) | 2016-11-08 | 2020-12-01 | Texas Instruments Incorporated | High linearity phase interpolator |
Also Published As
Publication number | Publication date |
---|---|
EP1678829B1 (de) | 2010-04-21 |
TW200525889A (en) | 2005-08-01 |
JP4719843B2 (ja) | 2011-07-06 |
DE602004026760D1 (de) | 2010-06-02 |
EP1678829A1 (de) | 2006-07-12 |
CN1871772A (zh) | 2006-11-29 |
CN1871772B (zh) | 2011-07-13 |
TWI381641B (zh) | 2013-01-01 |
JP2007509561A (ja) | 2007-04-12 |
WO2005041413A1 (en) | 2005-05-06 |
ATE465550T1 (de) | 2010-05-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS, N.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STIKVOORT, EDUARD F.;SANDLEANU, MIHAI A., T.;REEL/FRAME:017817/0775 Effective date: 20050523 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KONINKLIJKE PHILIPS ELECTRONICS N.V.;REEL/FRAME:019719/0843 Effective date: 20070704 Owner name: NXP B.V.,NETHERLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KONINKLIJKE PHILIPS ELECTRONICS N.V.;REEL/FRAME:019719/0843 Effective date: 20070704 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |