DE602004026760D1 - Frequenzteiler - Google Patents

Frequenzteiler

Info

Publication number
DE602004026760D1
DE602004026760D1 DE602004026760T DE602004026760T DE602004026760D1 DE 602004026760 D1 DE602004026760 D1 DE 602004026760D1 DE 602004026760 T DE602004026760 T DE 602004026760T DE 602004026760 T DE602004026760 T DE 602004026760T DE 602004026760 D1 DE602004026760 D1 DE 602004026760D1
Authority
DE
Germany
Prior art keywords
frequency divider
inverted output
input
flip
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004026760T
Other languages
English (en)
Inventor
Eduard F Stikvoort
Mihai A Sanduleanu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ST Ericsson SA
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602004026760D1 publication Critical patent/DE602004026760D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
    • H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters
    • H03K23/542—Ring counters, i.e. feedback shift register counters with crossed-couplings, i.e. Johnson counters

Landscapes

  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Soil Working Implements (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Logic Circuits (AREA)
DE602004026760T 2003-10-23 2004-10-13 Frequenzteiler Active DE602004026760D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03103937 2003-10-23
PCT/IB2004/052080 WO2005041413A1 (en) 2003-10-23 2004-10-13 Frequency divider

Publications (1)

Publication Number Publication Date
DE602004026760D1 true DE602004026760D1 (de) 2010-06-02

Family

ID=34486350

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004026760T Active DE602004026760D1 (de) 2003-10-23 2004-10-13 Frequenzteiler

Country Status (8)

Country Link
US (1) US20070146021A1 (de)
EP (1) EP1678829B1 (de)
JP (1) JP4719843B2 (de)
CN (1) CN1871772B (de)
AT (1) ATE465550T1 (de)
DE (1) DE602004026760D1 (de)
TW (1) TWI381641B (de)
WO (1) WO2005041413A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101630957B (zh) * 2008-07-16 2011-07-06 中国科学院微电子研究所 具有自适应休眠的双模预分频器
US9705507B1 (en) 2016-05-19 2017-07-11 Texas Instruments Incorporated Fixed frequency divider circuit
US9647669B1 (en) 2016-07-18 2017-05-09 Texas Instruments Incorporated High speed frequency divider
US10855294B2 (en) 2016-11-08 2020-12-01 Texas Instruments Incorporated High linearity phase interpolator

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA929609A (en) * 1971-11-19 1973-07-03 K. Au Kenneth Single-channel mis flip-flop circuit
US4356411A (en) * 1978-12-12 1982-10-26 Tokyo Shibaura Denki Kabushiki Kaisha Flip-flop circuit
JPS55145439A (en) * 1979-04-27 1980-11-13 Toshiba Corp Input control type binary counter circuit
JPS57180224A (en) * 1981-04-28 1982-11-06 Toshiba Corp Flip-flop circuit
FR2529413A1 (fr) * 1982-06-29 1983-12-30 Thomson Csf Bascule logique, fonctionnant du continu a 10 ghz, et diviseur de frequence comportant cette bascule
DE3546132A1 (de) * 1985-12-24 1987-07-02 Ant Nachrichtentech Schaltungsanordnung zur erzeugung zweier takte
JPS63114409A (ja) * 1986-10-31 1988-05-19 Hitachi Ltd フリツプフロツプ回路
JPS6352512A (ja) * 1986-08-22 1988-03-05 Hitachi Ltd フリツプフロツプ回路
GB2198603A (en) * 1986-12-05 1988-06-15 Philips Electronic Associated Divider circuit
US4791315A (en) * 1987-06-04 1988-12-13 Cherry Semiconductor Corporation Cross-coupled latch
US4806786A (en) * 1987-11-02 1989-02-21 Motorola, Inc. Edge set/reset latch circuit having low device count
JPH0795015A (ja) * 1993-09-24 1995-04-07 Mitsubishi Electric Corp 半導体集積回路
US5907589A (en) * 1997-04-10 1999-05-25 Motorola, Inc. GHZ range frequency divider in CMOS
US6140845A (en) * 1998-12-04 2000-10-31 The Texas A&M University System Pseudo-dynamic differential flip-flop
US6424194B1 (en) * 1999-06-28 2002-07-23 Broadcom Corporation Current-controlled CMOS logic family
JP2001036389A (ja) * 1999-07-15 2001-02-09 Mitsubishi Electric Corp マスタ・スレーブ型フリップフロップ回路
US6166571A (en) * 1999-08-03 2000-12-26 Lucent Technologies Inc. High speed frequency divider circuit
GB2354383A (en) * 1999-09-17 2001-03-21 Sony Uk Ltd Dual loop phase-locked loop
US6535042B1 (en) * 2000-02-22 2003-03-18 Linear Technology Corporation High-speed, current-driven latch
US6657472B1 (en) * 2002-04-25 2003-12-02 Cypress Semiconductor Corp. Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch

Also Published As

Publication number Publication date
TW200525889A (en) 2005-08-01
US20070146021A1 (en) 2007-06-28
EP1678829B1 (de) 2010-04-21
EP1678829A1 (de) 2006-07-12
WO2005041413A1 (en) 2005-05-06
CN1871772A (zh) 2006-11-29
JP4719843B2 (ja) 2011-07-06
TWI381641B (zh) 2013-01-01
CN1871772B (zh) 2011-07-13
ATE465550T1 (de) 2010-05-15
JP2007509561A (ja) 2007-04-12

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: ST-ERICSSON SA, PLAN-LES-OUATES, CH

8364 No opposition during term of opposition