WO2005041412A1

WO2005041412A1 - Prescaler

Info

Publication number: WO2005041412A1
Application number: PCT/IB2004/052079
Authority: WO
Inventors: Mihai A. T. Sanduleanu; Eduard F. Stikvoort
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-10-23
Filing date: 2004-10-13
Publication date: 2005-05-06
Also published as: TW200522518A

Abstract

A prescaler, comprising a first flip-flop (F1) coupled to a second flip-flip (F2). Each flip-flop comprises a latch (M1, M2, M3, M4) having a first input (R) and a second input (S) coupled to respective first NOR circuit (M8, M9, M10) and second NOR circuit (M5, M6, M7).

Description

Prescaler

The invention relates to a prescaler. Prescalers, which are frequency dividers, are well known and widely used devices in applications as Phase Locked Loops (PLLs), prescalers, and digital receivers. Normally a frequency divider requires flip-flops coupled in a convenient manner for obtaining a desired frequency division. Actual trends in semiconductor technology are shrinking transistors size for improving the speed of the circuits and downsize the supply voltages for the integrated circuits for reducing a dissipation power of the chips.

US-A 6,424,194 describes ultra high-speed circuits using current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverters/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieved by combining C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high-speed transceivers used in fiber optic communication systems. It is observed that the circuits presented in the above-mentioned patent still use at least two stacked transistors, which make the less suitable for relative low- voltage (1.2, .9 or .7 V) supply applications. By stacking transistors, the threshold voltages of the upper transistors increase due to the back-bias effect. As a consequence, the upper transistors do not have maximum gain and maximum speed of operation. Modern trend in digital circuits design is lowering power consumption of the CMOS logic families operating at lower and lower supply voltages. A further trend is downscaling the oxide thickness used to build MOS transistors for reliability reasons. Even if they work at a relatively low supply voltage the logic families has to work also at relatively high frequencies. A relatively fast logic family in MOS technology is the Source Coupled Logic (SCL) family. At lower supply voltages SCL does not work properly due to the stacking of transistors. In this category are included AND, OR, XOR gates and the D-latch. The D-latch is the most difficult function to implement since the requirements for relatively short set-up and hold times implies high power consumption. The transconductance of the modern MOS transistors is low compared to its bipolar counterpart and therefore wider devices and higher currents are necessary to achieve gain requirements for such a device. In CMOS technology, it is possible to implement relatively easy a NOR function using a pair of transistors having their drains coupled together and further coupled to a supply voltage via resistors means. The MOS transistors work with zero back-gate voltage and they have the largest possible transconductance. Hence, based on this logic function a low-voltage, high-speed latch may be obtained coupling the NOR circuit to a Reset-Set (RS) flip-flop for obtaining a high-speed latch.

It is therefore an object of the invention to provide a frequency divider suitable for low- voltage supply voltages and high speed of operation. The invention is defined in independent claim. Dependent claims describe advantageous embodiments. The high-speed prescaler comprises a first flip-flop coupled to a second flip- flip each flip-flop comprising. Each flip-flop comprises a latch having a first input and a second input coupled to respective first NOR circuit and second NOR circuit. In an embodiment, the prescaler is implemented for differential signals as most of modern receivers and transceivers use nowadays.

The above and other features and advantages of the invention will be apparent from the following description of the exemplary embodiments of the invention with reference to the accompanying drawings, in which: Fig. 1 depicts a D latch implemented with R-S flip-flops and AND gates, Fig. 2, depicts a D latch according to the invention, Fig. 3 depicts a differential D latch according to an embodiment of the invention, and Fig. 4 depicts a prescaler according to the invention. Fig. 1 depicts a D latch implemented with R-S flip-flops and AND gates. A single ended binary signal D is inputted via an inverter into a pair of AND circuits, the AND circuits being further coupled to an R-S flip-flop. The circuit comprising the flip-flop and the AND gates forms what is known as J-K latch in prior-art. It is observed that a binary clock signal is applied to the AND gates having an enabling function i.e. when the clock signal is HIGH the input data D propagates to the R and S inputs of the R-S flip-flop, otherwise both signals at the inputs R and S are LOW. The S and R functions may be written as in equation 1. S = D*Q*Ck R = D*Q*Ck

Basically, R and S functions are AND functions and they are not suitable to be used in relatively high frequency applications with a relatively low supply voltage. On the other hand, as it was previously shown, NOR circuits are suitable for these applications. Hence, it is necessary to find a way to use NOR functions. Let us observe that equations (1) may be transformed as shown in equations (2). S=Q*D*Ck R = D*Q*Ck

Equations (2) describe NOR functions and therefore are suitable to be implemented using NOR circuits. The resulting block diagram of the flip-flop is shown in Fig. 2. Fig. 3 shows a transistor level implementation of the flip-flop shown in Fig. 2. In Fig. 3 transistors Ml, M2, M3 and M4 coupled to the supply voltage V_DD via resistors R2 implement an R-S flip-flop. NOR functions are implemented using transistors M8, M9, M10 and M5, M6 and M7, respectively. The transistors in each NOR have their drains coupled together either in the R input or in the S input of the R-S flip-flop. The drains are further connected to the supply voltage via resistors Rl. Signals D+ and D- are mutually in anti- phase i.e. mutually shifted with 180 degrees. Ck- denotes Ck and Q+ and Q- are the outputs of the R-S flip-flop. The signals Q+ and Q- are mutually in anti-phase. Hence, the circuit in Fig. 3 describes a differential flip-flop implementing equations (2). A main advantage of the flip-flop is that the minimum supply voltage is given by relation (3). V_DDmi_n = V_GS + ΔV_R1 (3) In relation (3) V_GS is the Gate to Source voltage of the NOR transistors and ΔV_RI is a voltage drop on resistors Rl. The current in the latch depends on temperature and voltage supply variations. That is why for maximum performance a voltage regulator is normally added to the supply voltage VDD- Using the latch described in Fig. 3 we may implement a high speed prescaler using differential signals as it is shown in Fig. 4. It has differential D inputs Dl, Dl and D2, D2 and differential outputs Ql, QΪ and Q2, Q2 respectively. Although the D-latch has a single ended clock input, in the prescaler configuration we need a differential input clock and therefore a mutually anti-phase clock signals Ck and Ck are inputted to respective clock inputs of the flip-flop Ckl and Ck2 . Practical implementation in CMOS 18 process shows operation up to 15GHz with a differential output amplitude of 1.6V peak to peak. It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word 'comprising' does not exclude other parts than those mentioned in the claims. The word 'a(n)' preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed purpose processor. The invention resides in each new feature or combination of features.

Claims

CLAIMS:

1. A prescaler, comprising: a first flip-flop (F 1) coupled to a second flip-flip (F2), each flip-flop comprising: a latch (Ml, M2, M3, M4) having a first input (R) and a second input (S) coupled to respective first NOR circuit (M8, M9, M10) and second NOR circuit (M5, M6, M7).

2. A high speed prescaler as claimed in Claim 4, wherein each NOR circuit comprises a triade (M8, M9, Ml 9; M5, M6, M7) of transistors each having a control terminal, a source and a drain, the respective drains being coupled to a supply voltage via resistor means (Rl).

3. A high speed prescaler as claimed in Claim 5, wherein an input signal is differential and each flip-flop (Fl, F2) has a respective clock input, which are driven by mutually in anti-phase signals.