CN112953525B - High-speed 8/9 prescaler circuit, control method thereof and phase-locked loop comprising same - Google Patents
High-speed 8/9 prescaler circuit, control method thereof and phase-locked loop comprising same Download PDFInfo
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention discloses a high-speed 8/9 dual-mode prescaler, which comprises 10 TSPC latches L1-L10, 1 NAND gate (G2), 1 NOR gate (G3), a first NOT gate (G1) and a second NOT gate (G4); the method is characterized in that: TSPC latches L1, L3, L5, L7, and L9 are latches of a first type, and TSPC latches L2, L4, L6, L8, and L10 are latches of a second type. The high-speed 8/9 dual-mode prescaler provided by the invention has high working frequency and wide coverage frequency band.
Description
Technical Field
The invention relates to the field of high-speed analog circuits and radio frequency integrated circuits, in particular to a dual-mode prescaler circuit, and more particularly to a high-speed 8/9 prescaler circuit, a control method thereof and a phase-locked loop comprising the prescaler.
Background
The prescaler is usually used as a component of a frequency divider in the phase-locked loop, taking a conventional pulse swallowing type programmable frequency divider in fig. 1 as an example, the dual-mode 8/9 prescaler is used to divide a high-frequency signal output by an oscillator in the phase-locked loop to a lower frequency, and then input the lower frequency signal into other programmable frequency division functional modules, and the frequency divider can realize a frequency division ratio of: 8 multiplied by M + A, wherein M is the module value of the M counter, A is the module value of the A counter, and M and A are integers.
Commonly used dual-Mode prescaler structures generally include an injection locked frequency divider, a frequency divider based on cml (current Mode logic), and a frequency divider based on true Single Phase clock tspc (true Single Phase lock) logic. The injection locking prescaler is an analog frequency divider, can work at higher frequency, but has a small working frequency range; the pre-divider based on the CML logic needs to make a compromise among the size of an MOS tube, the power consumption of the frequency divider, the voltage swing and the working frequency, and has high working frequency but high power consumption. Compared with the prescaler of the CML logic, the prescaler based on the TSPC logic has a slightly lower working frequency, but the power consumption and the area are smaller than those of the CML logic frequency divider. In the broadband radio frequency phase-locked loop, the frequency divisible frequency of the prescaler is required to be high, and the frequency divisible frequency range of the prescaler is required to be large.
In the frequency divider based on the TSPC logic, the available TSPC type circuit structure is as follows: the TSPC dual-mode prescaler is mainly composed of a TSPC trigger and a TSPC latch, reference 1 discloses an 2/3 dual-mode prescaler, reference 2 discloses a 2/3, 4/5 prescaler, and the prescalers disclosed by the references 1 and 2 adopt a TSPC trigger mode. Further, it is specifically noted that, in order to omit the trouble of repeated description, the entire contents of reference 1 and reference 2 are actually incorporated in their entirety into the present application based on the disclosure thereof. See references 1 and 2 below for details.
Reference 1: schroeber, a dual mode prescaler, CN111786668A, 2020-10-16.
Reference 2: xiaoran Li, Jian Gao, Zhiming Chen, Xinghua Wang.high-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Module Prescaler [ J ]. Electronics,2020,9 (5).
Disclosure of Invention
The dual-mode prescaler based on the CML logic and the dual-mode prescaler based on the TSPC logic both have digital frequency dividers, the operable frequency range is wide, and the dual-mode prescaler based on the TSPC logic is generally selected in advance from the aspects of power consumption and area. The dual-mode 8/9 prescaler based on the TSPC latch has high working frequency and wide coverage frequency band.
The invention provides a high-speed 8/9 dual-mode prescaler, which comprises 10 TSPC latches L1-L10, 1 NAND gate (G2), 1 NOR gate (G3), a first NOT gate (G1) and a second NOT gate (G4); the method is characterized in that: TSPC latches L1, L3, L5, L7, and L9 are latches of a first type, and TSPC latches L2, L4, L6, L8, and L10 are latches of a second type;
the TSPC latches L1-L8 are connected in series, and the output end Q of the TSPC latch L8 is connected with a second NOT gate (G4) and then serves as the output end of the dual-mode prescaler; an output end Q of the TSPC latch L9 is connected with one input end of a NAND gate (G2), the other input end of the NAND gate (G2) is a mode control input signal MC, an output end of the NAND gate is connected with an input end D of the TSPC latch L10 through a first NOT gate (G1), an output end of a NOR gate (G3) is connected with an input end D of the TSPC latch L1, and two input ends of the NOR gate are respectively connected with the output end Q of the TSPC latch L10 and the input end D of the TSPC latch L9;
where all of TSPC latches L1-10 have the same control clock signal.
The first type latch is composed of 6 MOS tubes and comprises 2 PMOS tubes and 4 NMOS tubes, the sources of the PMOS tubes MP1 and MP2 are connected to a power supply, the sources of the NMOS tubes MN2 and MN4 are grounded, the first type latch inputs a clock CK to control the grids of the PMOS tubes MP1, the NMOS tubes MN2 and MN3, an input signal D of the first type latch is connected with the grid of the NMOS tube MN1, the drain of the PMOS tube MP1 is connected with the drain of the NMOS tube MN1 and serves as grid control signals of the PMOS tubes MP2 and MN4, the source of the NMOS tube MN1 is connected with the drain of the NMOS tube MN2, the drain of the NMOS tube MN3 is connected with the drain of the PMOS tube MP2 and serves as an output signal Q, and the source of the NMOS tube MN3 is connected with the drain of the NMOS tube MN 4.
The second type latch is composed of 6 MOS transistors and comprises 2 NMOS transistors and 4 PMOS transistors, the sources of the PMOS transistors MP3 and MP6 are connected to a power supply, the sources of the NMOS transistors MN5 and MN6 are grounded, an input clock CK of the second type latch controls the gates of the PMOS transistors MP3, the NMOS transistors MN5 and the PMOS transistor MP5, an input signal D of the second type latch is connected with the gate of the PMOS transistor MP4, the drain of the PMOS transistor MP4 is connected with the drain of the NMOS transistor MN5 and serves as gate control signals of the PMOS transistors MP6 and MN6, the source of the PMOS transistor MP4 is connected with the drain of the PMOS transistor MP3, the drain of the NMOS transistor MN6 is connected with the drain of the PMOS transistor MP5 and serves as an output signal Q, and the source of the PMOS transistor MP6 is connected with the drain of the PMOS transistor MP 5.
In addition, the invention also provides a control method of the high-speed 8/9 dual-mode prescaler, which comprises the following specific steps: when the mode control input signal MC of the high-speed 8/9 dual-mode prescaler is low, the output of a NAND gate (G2) is at a high level, the output of an inverter (G1) is at a low level, the output of a second type latch L10 is also kept at a low level, the frequency dividing ratio of the high-speed 8/9 dual-mode prescaler is 8, and when the mode control input signal MC is high, a first type latch L9 and a second type latch L10 participate in frequency dividing action, so that the frequency dividing ratio of the prescaler is 9. The invention provides a high-speed 8/9 dual-mode prescaler, the power supply voltage of which is 1.2V, when the input clock is 600mV sine waves, the working range of which is 0.5GHz-14.5GHz, and the average current of which is lower than 1 mA. Furthermore, the invention also discloses a pulse swallowing type programmable frequency divider in the phase-locked loop, which comprises the high-speed 8/9 dual-mode prescaler provided by the invention.
Furthermore, the invention also provides a phase-locked loop which comprises the high-speed 8/9 dual-mode prescaler.
Drawings
FIG. 1 is a pulse-gating programmable frequency divider for a phase locked loop;
FIG. 2 is a high speed 8/9 dual modulus prescaler in accordance with the present invention;
FIG. 3(a) is a structure of a first type of latch proposed by the present invention;
FIG. 3(b) is a structure of a second type of latch proposed by the present invention;
FIG. 4 is a timing diagram illustrating the operation of a dual-mode 8/9 frequency divider;
FIG. 5 is a schematic diagram of the functional verification of a high speed 8/9 frequency divider;
fig. 6 is a modified 8/9 prescaler.
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings.
The dual-mode prescaler based on the CML logic and the dual-mode prescaler based on the TSPC logic both have digital frequency dividers, the operable frequency range is wide, and the dual-mode prescaler based on the TSPC logic is generally selected in advance from the aspects of power consumption and area. The dual-mode 8/9 prescaler based on the TSPC latch has high working frequency and wide coverage frequency band.
The whole circuit of the invention is shown in fig. 2 and comprises TSPC first type latches L1, L3, L5, L7, L9, TSPC second type latches L2, L4, L6, L8, L10, a nand gate G2, a nor gate G3 and not gates G1 and G4.
TSPC first type latch L1, L3, L5, L7, L9 are at high level, the output of the first type latch is equal to the input of the first type latch, at low level, the output of the first type latch is kept unchanged; TSPC the output of the second type latch L2, L4, L6, L8, L10 is equal to the input of the second type latch when it is low and remains unchanged when it is high. The output A of the second type latch L8 and the output B of the second type latch L10 are the input of a two-input NOR gate G3, the output of the NOR gate G3 is input to the first type latch L1, the output of the first type latch L9 and the mode control input signal MC are the input of a two-input NAND gate G2, the output of the NAND gate G2 passes through an inverter G1 and is input to the second type latch L10, and all the first type latches and the second type latches are clocked.
As shown in fig. 3(a), the structure of the first type latch used in the present invention is fully on when a high level is inputted and latched when a low level is inputted. The first type latch is composed of 6 MOS tubes and comprises 2 PMOS tubes and 4 NMOS tubes, the sources of MP1 and MP2 are connected with a power supply, the sources of MN2 and MN4 are grounded, an input clock CK of the first type latch controls the gates of MP1, MN2 and MN3, an input signal D of the first type latch is connected with the gate of MN1, the drain of MP1 is connected with the drain of MN1 and used as gate control signals of MP2 and MN4, the source of MN1 is connected with the drain of MN2, the drain of MN3 is connected with the drain of MP2 and used as an output signal Q, and the source of MN3 is connected with the drain of MN 4.
As shown in fig. 3(b), the structure of the second type latch used in the present invention latches when a high level is input and is all on when a low level is input. The second type latch is composed of 6 MOS tubes and comprises 2 NMOS tubes and 4 PMOS tubes, the sources of MP3 and MP6 are connected with a power supply, the sources of MN5 and MN6 are grounded, an input clock CK of the second type latch controls the gates of MP3, MN5 and MP5, an input signal D of the second type latch is connected with the gate of MP4, the drain of MP4 is connected with the drain of MN5 and used as gate control signals of MP6 and MN6, the source of MP4 is connected with the drain of MP3, the drain of MN6 is connected with the drain of MP5 and used as an output signal Q, and the source of MP6 is connected with the drain of MP 5.
L1, L3, L5, L7, L9 are latches of the first type, and as shown in fig. 3(a), when the clock signal CK is low, a is pulled up to high level, MN3 is turned off, a is high level to turn off MP2, so the output X remains unchanged; when the clock signal CK is at high level, MN3 is conducted, branch 2 is equivalent to an inverter, in branch 1, MN2 is conducted, if D is at high level, MN1 is conducted, a path exists between A and ground, A is changed into low level, namely logic of A is opposite to logic of B, and after A is inverted by branch 2, the output X is identical to logic of B; if B is low and MN1 is off, A keeps the original high level and the output X is low level, which is the same logic as B. Therefore, when CK is low, X remains unchanged, and when CK is high, X is logically the same as input B.
L2, L4, L6, L8, L10 are latches of the second type, whose function is, as shown in fig. 3(B), that X remains unchanged when CK is high and is logically identical to input B when CK is low.
Further, referring to FIG. 2 in conjunction with FIGS. 3(a) and 3(B), port D of TSPC latch L1-10 in FIG. 2 corresponds to input B in FIGS. 3(a) and 3(B), and port Q of TSPC latch L1-10 in FIG. 2 corresponds to output X in FIGS. 3(a) and 3 (B).
Referring to fig. 4, the timing of the operation of a dual-mode 8/9 frequency divider is shown. When the mode control input MC is low, the output of the nand gate G2 is high, the output of the inverter G1 is low, and the output of the second-type latch L10 is also kept low, i.e., in the whole frequency division loop, the first-type latch L9 and the second-type latch L10 do not function, the frequency division ratio of the prescaler is 8, and when MC is high, the first-type latch L9 and the second-type latch L10 participate in the frequency division function, so that the frequency division ratio of the prescaler is 9.
In an application example, the high-speed dual-mode 8/9 prescaler provided by the invention adopts a TSMC65nm process. By adopting the TSPC-based latch provided by the invention, under the typical working condition of the high-speed 8/9 prescaler, when the power supply voltage is 1.2V and the input clock is 600mV sine waves, the post-simulation shows that the working range is 0.5GHz-14.5GHz and the average current is lower than 1 mA. It can be seen that the 8/9 prescaler based on the TSPC latch proposed by the present invention can be used in a wideband phase locked loop.
Referring to fig. 5, a functional verification schematic of the dual mode 8/9 divider of the present invention in TSMC65nm technology is shown.
In order to further verify that the operating frequency of the 8/9 prescaler based on the TSPC latch is higher than that of the 8/9 prescaler based on the TSPC flip-flop, the structure of the 8/9 prescaler formed based on the TSPC flip-flop is shown in fig. 6, the TSMC65nm process is also adopted, and under the same input conditions, the prescaler with the structure shown in fig. 6 is adopted, and the operating frequency can only reach 10GHz at maximum. It can be seen that compared with the 8/9 prescaler formed by using the TSPC-based latch, the operating frequency of the invention can reach 14.5GHz to the maximum, and it can be seen that by using the high-speed 8/9 prescaler provided by the invention, because the prescaler is constructed by using the TSPC-based latch, compared with a scheme based on a trigger, the maximum operating frequency is higher than 4.5GHz, that is, the maximum operating frequency is improved by almost 5.
While the foregoing is directed to the embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (5)
1. A high-speed 8/9 dual-mode prescaler includes 10 TSPC latches L1-L10, 1 NAND gate (G2), 1 NOR gate (G3), a first NOT gate (G1) and a second NOT gate (G4); the method is characterized in that: TSPC latches L1, L3, L5, L7, and L9 are latches of a first type, and TSPC latches L2, L4, L6, L8, and L10 are latches of a second type;
the TSPC latches L1-L8 are connected in series, and the output end Q of the TSPC latch L8 is connected with a second NOT gate (G4) and then serves as the output end of the dual-mode prescaler; an output end Q of the TSPC latch L9 is connected with one input end of a NAND gate (G2), the other input end of the NAND gate (G2) is a mode control input signal MC, an output end of the NAND gate is connected with an input end D of the TSPC latch L10 through a first NOT gate (G1), an output end of a NOR gate (G3) is connected with an input end D of the TSPC latch L1, and two input ends of the NOR gate are respectively connected with the output end Q of the TSPC latch L10 and the input end D of the TSPC latch L9;
wherein all of the TSPC latches L1-10 have the same control clock signal;
the first type latch is composed of 6 MOS tubes and comprises 2 PMOS tubes and 4 NMOS tubes, the sources of the PMOS tube MP1 and the PMOS tube MP2 are connected to a power supply, the sources of the NMOS tube MN2 and the NMOS tube MN4 are grounded, a first type latch input clock CK controls the grids of the PMOS tube MP1, the NMOS tube MN2 and the NMOS tube MN3, a first type latch input signal D is connected with the grid of the NMOS tube MN1, the drain of the PMOS tube MP1 is connected with the drain of the NMOS tube MN1 and serves as grid control signals of the PMOS tube MP2 and the NMOS tube MN4, the source of the NMOS tube MN1 is connected with the drain of the NMOS tube MN2, the drain of the NMOS tube MN3 is connected with the drain of the PMOS tube MP2 and serves as an output signal Q, and the source of the NMOS tube MN3 is connected with the drain of the NMOS tube MN 4;
the second type latch is composed of 6 MOS tubes and comprises 2 NMOS tubes and 4 PMOS tubes, the sources of the PMOS tubes MP3 and MP6 are connected to a power supply, the sources of the NMOS tubes MN5 and MN6 are grounded, an input clock CK of the second type latch controls the gates of the PMOS tubes MP3, the NMOS tubes MN5 and the PMOS tube MP5, an input signal D of the second type latch is connected with the gate of the PMOS tube MP4, the drain of the PMOS tube MP4 is connected with the drain of the NMOS tube MN5 and is used as gate control signals of the PMOS tube MP6 and the NMOS tube MN6, the source of the PMOS tube MP4 is connected with the drain of the PMOS tube MP3, the drain of the NMOS tube MN6 is connected with the drain of the PMOS tube MP5 and is used as an output signal Q, and the source of the PMOS tube MP6 is connected with the drain of the PMOS tube MP 5.
2. A pulse swallowed programmable frequency divider in a phase locked loop, comprising: the dual-mode high speed 8/9 prescaler of claim 1, comprising an M counter, an A counter, wherein M is a modulus value of the M counter, A is a modulus value of the A counter, and both M and A are integers.
3. A method for controlling the high speed 8/9 dual-modulus prescaler of claim 1, wherein: when the mode control input signal MC of the high-speed 8/9 dual-mode prescaler is low, the output of a NAND gate (G2) is at a high level, the output of an inverter (G1) is at a low level, the output of a second type latch L10 is also kept at a low level, the frequency dividing ratio of the high-speed 8/9 dual-mode prescaler is 8, and when the mode control input signal MC is high, a first type latch L9 and a second type latch L10 participate in frequency dividing action, so that the frequency dividing ratio of the prescaler is 9.
4. A control method according to claim 3, characterized in that: when the power supply voltage is 1.2V and the input clock is 600mV sine wave, the working range of the high-speed 8/9 dual-mode pre-divider is 0.5GHz-14.5GHz, and the average current is lower than 1 mA.
5. A phase locked loop comprising the high speed 8/9 dual modulus prescaler of claim 1.
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| JP3275222B2 (en) * | 1994-03-04 | 2002-04-15 | 富士通株式会社 | Phase locked oscillator |
| KR20000000262A (en) * | 1999-10-07 | 2000-01-15 | 손상희 | A novel architecture of Programmable frequency divider |
| KR100329590B1 (en) * | 2000-05-25 | 2002-03-21 | 대표이사 서승모 | Dual-Modulus Prescaler For RF Frequency Synthesizer |
| US6822491B1 (en) * | 2003-06-27 | 2004-11-23 | Intel Corporation | Frequency prescaler apparatus, method, and system |
| CN102710259B (en) * | 2012-06-15 | 2014-08-13 | 江苏物联网研究发展中心 | True single-phase clock dual-mode prescaler with high speed and low power consumption |
| CN107565965A (en) * | 2017-09-13 | 2018-01-09 | 东南大学 | A kind of 8 frequency dividings at a high speed and the 9 frequency dividing pre- frequency dividing circuits of bimodulus |
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