200522518 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種預定標器。 【先前技術】 作為分頻器的預定標器係眾所週知且廣泛使用之裝置， 並且係例如鎖相回路（PLL)、預定標器及數位接收器之應用 中的廣泛使用裝置。通常而言，分頻器需要以方便方式加 以耦合的正反器，以獲得所需分頻。 半導體技術中的實際趨勢係縮減電晶體尺寸以改進電路 之速度，並罅小用於積體電路的供電電壓以減小晶片之消 耗功率。 美國專利第A 6,424,194號揭示超高速電路，其採用以傳 統CMOS處理技術所製造的電流控制cm〇S(C3MOS)邏輯。 可採用C3MOS技術來實施整個邏輯元件系族，包括反相器/ 緩衝器、位準偏移器、NAND閘極、NOR閘極、x〇r閘極、 鎖存器、正反器等等。藉由將c3M〇s邏輯與低功率傳統 CMOS邏輯組合，可以達到用於各電路應用的功率消耗與速 度之間的最佳平衡。所組合的C3M0S/CM0S邏輯允許電路 之更大整合’例如用於光纖通訊系統之高速收發器。應觀 察到上述專利所揭示&電路仍採用至彡二個堆疊的電晶 體，其不那麼適合於相對較低（12、0 9或〇.7v)電壓供應之 應用藉由堆⑥電晶體，較高電晶體之臨界電壓因向後偏 壓效應而增加。因而較高電晶體沒有最大增益及最大操作 速度。 96770.doc 200522518 將以越來越低之供電電壓下操作的CMOS邏輯系族之功 率消耗降低係數位電路中的現代趨勢。另一趨勢係為了可 靠性原因而縮減用以建立M0S電晶體的氧化物厚度。 即使邏輯系族以相對較低供電電壓進行作業，該等邏輯 系族仍必須還以相對較高頻率進行作業。M〇s技術中相對 較快的邏輯系族係源極麵合邏輯（SCL)系列。 在較低供電電壓的情況下，SCL因電晶體之堆疊而無法 正常工作。此類別包括AND閘極、N〇R閘極、x〇R閘極及D 鎖存器。D鎖存器係最難實施的功能，因為需要相對較短的 設定時間及保持時間意味著高功率消耗。與雙極電晶體相 比，現代MOS電晶體之跨導較低，因此有必要採用較寬的 I置及較咼的電流來達到此一裝置之增益要求。 在CMOS技術中，可以採用汲極耦合在一起並進一步經由 電阻益構件而與供電電壓耦合的一對電晶體來實施相對較 容易的NOR功能。MOS電晶體採用零向後閘極電壓而進行 作業，並且其具有最大可能之跨導。因此，根據此邏輯功 能，藉由將NOR電路與用以獲得高速鎖存器的重設設定 (R-S)正反器耦合，可獲得低電壓、高速鎖存器。 【發明内容】 ，此本發明之-目的係提供—種適合於低電壓供電電壓 及高速操作的分頻器。 本發明係定義在中請專利範圍之獨立項中1請專利範 圍之附屬項說明較佳具體實施例。 ’其與每個正反器所包 南速預定標器包含一第一正反器 96770.doc 200522518 含之一第二正反器搞合。各正反器包括一鎖存器，其具有 與個別第一NOR電路及第二NOR電路耦合的第一輸入及第 二輸入。 在一具體實施例中，如現今大多數現代接收器及收發器 所使用，針對差動信號實施預定標器。 【實施方式】 圖1描述採用R-S正反器及AND閘極所實施的D鎖存器。 經由反相器將單端二進制信號D輸入至一對AND電路中，而 將AND電路進一步與R-S正反器耦合。包括正反器及AND 閘極的電路形成先前技術中所瞭解的J-K鎖存器。應觀察到 將二進制時脈信號應用於具有致動功能的AND閘極，即當 時脈信號為HIGH時，輸入資料D會傳播至R-S正反器之R及 S輸入，否則輸入R及S中的兩個信號均為LOW。 可如等式1所示將S及R功能寫入。 S=D*0*Ck R= Z)*Q*Ck (1) 基本上，R及S功能為AND功能，並且其不適用於具有相對 較低供電電壓的相對較高頻率之應用。另一方面，如先前 所示，NOR電路適合於該等應用。因此有必要找出使用NOR 功能的方法。應觀察到可將等式（1)轉化為如等式（2)所示。 R=D*Q*Ck (2) 等式（2)說明NOR功能，因此適合於採用NOR電路而加以實 施。圖2顯示所獲得的正反器之方塊圖。 96770.doc 200522518 圖3顯示圖2所示的正反器之電晶體位準實施方案。在圖3 中，經由電阻器R2與供電電壓Vdd麵合的電晶體MU、 M3及Μ4實施R-S正反器。分別採用電晶體M8、M9、_ 與M5、M6及M7而實施N0R功能。各n〇r電路中的電晶體 之汲極於R-S正反器之R輸入或S輸入中耦合在一起。經由電 阻器R1將沒極另外連接至供電電壓。信號D+及&為相互反 相位，即相互偏移180度。200522518 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a prescaler. [Previous Technology] The prescaler as a frequency divider is a well-known and widely used device, and is a widely used device in applications such as a phase locked loop (PLL), a prescaler, and a digital receiver. In general, a frequency divider requires a coupled flip-flop in a convenient way to obtain the desired frequency divider. The practical trend in semiconductor technology is to reduce the size of the transistor to improve the speed of the circuit, and to reduce the supply voltage for integrated circuits to reduce the power consumption of the chip. U.S. Patent No. A 6,424,194 discloses an ultra-high-speed circuit that uses current-controlled cmOS (C3MOS) logic manufactured using conventional CMOS processing technology. C3MOS technology can be used to implement the entire family of logic elements, including inverters / buffers, level shifters, NAND gates, NOR gates, x0r gates, latches, flip-flops, and more. By combining c3M0s logic with low-power traditional CMOS logic, the best balance between power consumption and speed for each circuit application can be achieved. The combined C3M0S / CM0S logic allows greater integration of circuits', such as high-speed transceivers for fiber optic communication systems. It should be observed that the circuit disclosed in the above patent still uses up to two stacked transistors, which are not so suitable for applications with relatively low (12, 09, or 0.7v) voltage supply. By stacking transistors, The threshold voltage of higher transistors increases due to the effect of backward bias. Therefore, higher transistors do not have maximum gain and maximum operating speed. 96770.doc 200522518 A modern trend in CMOS logic families that will operate at increasingly lower supply voltages to reduce power consumption in coefficient-bit circuits. Another trend is to reduce the thickness of oxides used to build MOS transistors for reliability reasons. Even if the logic families operate at a relatively low supply voltage, the logic families must still operate at a relatively high frequency. The relatively fast logic family source area logic (SCL) series in Mos technology. At lower supply voltages, the SCL cannot work properly due to the stacking of transistors. This category includes AND gates, NO gates, x gate gates, and D latches. The D latch is the most difficult function to implement because the relatively short set-up and hold times mean high power consumption. Compared with bipolar transistors, the transconductance of modern MOS transistors is lower, so it is necessary to use a wider I set and higher current to achieve the gain requirements of this device. In CMOS technology, a relatively easy NOR function can be implemented using a pair of transistors with their drains coupled together and further coupled to the supply voltage via a resistive device. MOS transistors operate with zero back-gate voltage and have the greatest possible transconductance. Therefore, according to this logic function, a low-voltage, high-speed latch can be obtained by coupling a NOR circuit with a reset setting (R-S) flip-flop for obtaining a high-speed latch. [Summary of the Invention] The object of the present invention is to provide a frequency divider suitable for low-voltage power supply voltage and high-speed operation. The present invention is defined in the independent item of the patent scope, and the appended item of the patent scope describes preferred embodiments. ’It is combined with the south speed pre-scaler included in each flip-flop including a first flip-flop 96770.doc 200522518 and a second flip-flop. Each flip-flop includes a latch having a first input and a second input coupled to a respective first NOR circuit and a second NOR circuit. In a specific embodiment, as used by most modern receivers and transceivers today, a prescaler is implemented for differential signals. [Embodiment] FIG. 1 illustrates a D latch implemented by using an R-S flip-flop and an AND gate. The single-ended binary signal D is input to a pair of AND circuits via an inverter, and the AND circuit is further coupled to the R-S flip-flop. The circuit including the flip-flop and the AND gate forms a J-K latch as known in the prior art. It should be observed that the binary clock signal is applied to the AND gate with actuation function, that is, when the clock signal is HIGH, the input data D will propagate to the R and S inputs of the RS flip-flop, otherwise the input in R and S Both signals are LOW. The S and R functions can be written as shown in Equation 1. S = D * 0 * Ck R = Z) * Q * Ck (1) Basically, the R and S functions are AND functions, and they are not suitable for applications with relatively high frequency with relatively low supply voltage. On the other hand, as shown previously, NOR circuits are suitable for these applications. It is necessary to find out how to use the NOR function. It should be observed that equation (1) can be transformed as shown in equation (2). R = D * Q * Ck (2) Equation (2) describes the NOR function and is therefore suitable for implementation with a NOR circuit. FIG. 2 shows a block diagram of the obtained flip-flop. 96770.doc 200522518 Figure 3 shows the transistor level implementation of the flip-flop shown in Figure 2. In FIG. 3, R-S flip-flops are implemented via transistors MU, M3, and M4 in which the resistor R2 and the supply voltage Vdd are in plane. The transistors M8, M9, _ and M5, M6, and M7 are used to implement the NOR function. The drain of the transistor in each nor circuit is coupled to the R or S input of the R-S flip-flop. The pole is additionally connected to the supply voltage via resistor R1. The signals D + and & are out of phase with each other, that is, offset by 180 degrees from each other.
Ck-表示5 ’而Q+及Q_為R_s正反器之輸出。信號及 Q-為相互反相位◊因此圖3所示的電路說明實施等式（2)之 差動正反器。.正反器的主要優點在於由關係式⑺給定最小 供電電壓。 VDDmin = VGS + AVR1 (” 在關係式（3)中’ Vgs_OR電晶體之閘極至源極電壓，而 △ VR1為電阻器R1上的電壓降。 鎖存器中的電流取決於溫度及電壓供應之變化。此係通 常因最大性能而將電壓調整器加入供電電壓之原因。 採用圖3所說明的鎖存器，可使用如圖4所示的差動信號 而貫施咼速預疋標器。其分別具有差動D輸入D1、一與、 仍，及差動輸出Q1、0與Q2、以。雖然〇鎖存器具有單端 時脈輸入，但是在預定標器組態中需要差動輸入時脈，因 而將相互反相位之時脈信號Ck及α：輸入至正反器之個別時 脈輸入茂1及中。 CMOS 18程序中的實際實施方案顯示採用16 V峰值對峰 值之差動輸出振幅的最高至15 GHZ之操作。 96770.doc 200522518 應注意本發明之範疇不限於本文所說明的具體實施例。 本發明之保護的範鳴也不受中請專利範圍中的參考數字之 限制。詞|「包含」不排斥除中請專利範圍所提到的部件 以外之部件。元件前面的詞彙「一(一個)」不排斥複數個該 等元件。可以專用硬體的形式或以程式化目的處理器的形 式而實施形成本發明之部分的構件。本發明存在於各新賴 特徵或特徵之組合中。 【圖式簡單說明】 參考附圖，從本發明之示範性具體實施例的以上說明， 將明白本發明之以上及其他特徵及優點，其中： 圖1描述採用R-S正反器及AND閘極所實施的D鎖存器， 圖2描述依據本發明之d鎖存器， 圖3描述依據本發明之一具體實施例的差動D鎖#器’以及 圖4描述依據本發明之預定標器。 【主要元件符號說明】 F1 第一正反器 F2 第二正反器 Ml 鎖存器 M2 鎖存器 M3 鎖存器 M4 鎖存器 M5 第二NOR電路 M6 第二NOR電路 M7 第二NOR電路 96770.doc 200522518 M8 第一 NOR電路 M9 第一 NOR電路 M10 第一 NOR電路 R 第一輸入 R1 電阻器 R2 電阻器 S 第二輸入 96770.doc -1〇 -Ck- represents 5 'and Q + and Q_ are the outputs of the R_s flip-flop. The signal and Q- are opposite to each other, so the circuit shown in FIG. 3 illustrates the implementation of the differential flip-flop of equation (2). The main advantage of the flip-flop is that the minimum supply voltage is given by the relationship ⑺. VDDmin = VGS + AVR1 ("In relation (3), the gate-to-source voltage of the Vgs_OR transistor, and △ VR1 is the voltage drop across resistor R1. The current in the latch depends on the temperature and voltage supply This is the reason that the voltage regulator is usually added to the supply voltage due to the maximum performance. Using the latch illustrated in Figure 3, the speed pre-marker can be applied continuously using the differential signal shown in Figure 4. It has differential D inputs D1, one and, still, and differential outputs Q1, 0, and Q2, respectively. Although the 0 latch has a single-ended clock input, differential is required in the prescaler configuration The clock is input, so the clock signals Ck and α, which are in opposite phases to each other, are input to the individual clock inputs of the flip-flops 1 and 1. The actual implementation in the CMOS 18 program shows the difference between the 16 V peak to the peak value. The operation of the dynamic output amplitude is up to 15 GHZ. 96770.doc 200522518 It should be noted that the scope of the present invention is not limited to the specific embodiments described herein. The protection of the present invention is not covered by the reference numbers in the scope of patents. Restrictions. The word "include" does not exclude Please use parts other than those mentioned in the patent scope. The word "one (one)" in front of the elements does not exclude a plurality of such elements. The present invention can be implemented in the form of dedicated hardware or in the form of a programmatic processor. The components of the present invention. The present invention exists in each new feature or combination of features. [Brief description of the drawings] With reference to the drawings, the above and other aspects of the present invention will be understood from the above description of exemplary embodiments of the present invention. Features and advantages, of which: FIG. 1 depicts a D latch implemented using an RS flip-flop and an AND gate, FIG. 2 depicts a d latch according to the present invention, and FIG. 3 depicts a D latch according to a specific embodiment of the present invention. The differential D lock # device 'and FIG. 4 describe the prescaler according to the present invention. [Description of the main component symbols] F1 First flip-flop F2 Second flip-flop M1 Latch M2 Latch M3 Latch M4 Latch M5 second NOR circuit M6 second NOR circuit M7 second NOR circuit 96770.doc 200522518 M8 first NOR circuit M9 first NOR circuit M10 first NOR circuit R first input R1 resistor R2 resistor S Two-input 96770.doc -1〇 -