US20070138462A1 - Electronic device with unique encoding - Google Patents

Electronic device with unique encoding Download PDF

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US20070138462A1
US20070138462A1 US11/313,498 US31349805A US2007138462A1 US 20070138462 A1 US20070138462 A1 US 20070138462A1 US 31349805 A US31349805 A US 31349805A US 2007138462 A1 US2007138462 A1 US 2007138462A1
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Prior art keywords
transistors
gate
device defined
jet
printed
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US11/313,498
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English (en)
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Robert Street
Ana Arias
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Palo Alto Research Center Inc
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Palo Alto Research Center Inc
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Priority to US11/313,498 priority Critical patent/US20070138462A1/en
Assigned to PALO ALTO RESEARCH CENTER INCORPORATED reassignment PALO ALTO RESEARCH CENTER INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARIAS, ANA CLAUDIA, STREET, ROBERT A.
Priority to JP2006340138A priority patent/JP5192686B2/ja
Priority to EP06126615A priority patent/EP1801879A3/en
Publication of US20070138462A1 publication Critical patent/US20070138462A1/en
Priority to US12/645,987 priority patent/US7897439B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors

Definitions

  • the exemplary embodiment relates to a semiconductor apparatus and a method for producing it and, more particularly, to a semiconductor apparatus having a thin film transistor (TFT) matrix panel with electronic encryption and a method for producing it.
  • TFT thin film transistor
  • TFT thin film transistor
  • FET field effect transistor
  • the large-area X-ray imager has been successfully fabricated by integrating amorphous silicon (a-Si:H) TFTs with p-i-n photodiodes over a glass substrate coated with an X-ray converter material.
  • a-Si:H amorphous silicon
  • p-channel TFTs have been used to replace high-resistance loads in static random access memory (SRAM) devices.
  • SRAM static random access memory
  • high-density and high-response-speed printer and fax machines fabricated with TFTs have also been demonstrated.
  • the TFT can be used as a chemical sensor, e.g., to detect changes in gas-phase hydrogen concentration or liquid-phase potassium concentration.
  • a TFT array may be used as an electronic device that can be built directly on a silicon IC or a printed circuit board and fabricated in such a way that each device has a unique encoding built into its physical structure.
  • an electronic device comprising a semiconductor device such as a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments.
  • TFT thin film transistor
  • a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected.
  • An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones.
  • TFT array with n elements there are 2 n alternative configurations; therefore, a relatively small number of TFTs can uniquely identify a huge number of devices.
  • Such uniquely encoded devices have applications for encryption, identification and personalization of electronic systems.
  • TFT array One step in the construction of the TFT array is to print a material selectively onto specific TFTs. Normal semiconductor processing using photolithography would require a different mask for each device, and changing the mask for each device is not practical. Jet-printing offers a drop-on-demand printing system that can print a different pattern for each device, since the printer does not require a physical mask. The choice of the printed pattem is created in software.
  • an electronic device comprises a plurality of partially formed thin film transistors, each of the transistors including some of a gate contact, a source contact, a drain contact and a semiconductor, jet-printed material deposited on selected partially formed transistors to form completed transistors, and readout electronics to detect signals from the transistors and create an encoded bit stream, wherein the completed transistors and the partially formed transistors define the encoded bit stream.
  • an electronic device comprises a printed circuit board having a plurality of external leads, a jet-printed metal layer to connect selected leads to a voltage source, and an electronic circuit to measure the voltage on the external leads to identify the printed circuit board.
  • FIG. 1 is a schematic diagram of a two-dimensional matrix address array of thin film transistors wherein a subset of thin film transistors are selectively provided with a polymer semiconducting layer by ink-jet printing.
  • FIG. 2 is a schematic cross-section of the thin film transistor structure used to make printed polymer thin film transistor arrays.
  • FIG. 3 shows the pulse signal provided to the gates of the TFT array and the corresponding response for a printed thin film transistor and a non-printed thin film transistor.
  • FIG. 4 is a schematic diagram of an alternative two-dimensional matrix address array of thin film transistors using printed etch masks.
  • FIG. 5 is a schematic diagram of an alternative two-dimensional matrix address array of thin film transistors wherein a jet-printed connection is used to determine whether the thin film transistor is connected to the addressing circuit.
  • FIG. 6 is a diagram of a unique ID for a printed circuit board.
  • FIG. 1 is a schematic equivalent circuit diagram of a TFT array panel 10 according to an exemplary embodiment
  • FIG. 2 is a cross-sectional view of a thin film transistor 12 from the TFT array panel 10 .
  • the TFT array 10 comprises an n ⁇ m array of thin film field effect transistors 12 a - 12 i, in which a subset of TFTs (e.g., 12 b, 12 d, 12 e, and 12 i ) are selectively provided with a polymer semiconducting layer by ink-jet printing. Only the printed TFTs (e.g., 12 b, 12 d, 12 e, and 12 i ) will turn on when a gate voltage is applied and the non-printed devices (i.e., 12 a, 12 c, 12 f, 12 g, and 12 h ) are permanently turned off.
  • the printed pattern provides the encoding. and the pattern is electronically read out to validate the device by activating the matrix addressing. Every device that is to be secured can be made with a different printed pattern.
  • TFTs can be used for the encoding, depending on the requirement of the application, and a typical number is in the range 10 to 1000. It is convenient to organize the TFTs into a matrix because the number of contacts is reduced. An n ⁇ m array requires only about n+m contacts.
  • Each of the gate lines 14 , 16 , and 18 for transmitting gate signals extends substantially in a transverse direction.
  • the gate lines are preferably made of Al containing metal such as Al and Al alloy, Cu containing metal such as Cu and Cu alloy, Cr, Mo, Mo alloy, Ta, or Ti. They may have a multi-layered structure including two films having different physical characteristics. One of the two films is preferably made of low resistivity metal including Al containing metal for reducing signal delay or voltage drop in the gate lines.
  • the other film is preferably made of material such as Cr, Mo and Mo alloy, Ta or Ti, which has good physical, chemical, and electrical contact characteristics. Good examples of the combination of the two films are a lower Cr film and an upper Al—Nd alloy film and a lower Al film and an upper Mo film.
  • the gate lines may have a triple-layered structure including a lower Mo film, an intermediate Al film, and an upper Mo film.
  • a plurality of data lines 20 , 22 , and 24 are formed on the gate insulating layer and connect to one of the TFT contacts 26 or 28 .
  • the data lines 20 , 22 , and 24 for transmitting data voltages extend substantially in the longitudinal direction and intersect the gate lines.
  • the data lines 20 , 22 , and 24 are preferably made of a low resistivity metal.
  • the TFT contacts 26 and 28 must be a metal that forms a suitable ohmic contact to the TFT.
  • good contact materials include Au, Ag, ITO and organic conductors.
  • the TFT contacts 26 and 28 and the data lines 20 , 22 , and 24 can be comprised of the same metal or could comprise different metals in contact
  • bias lines 30 , 32 , and 34 there are three bias lines 30 , 32 , and 34 and a common bias 36 .
  • a common bias connection is made to the other TFT contact, and the metal requirements are the same as for the data lines 20 , 22 , and 24 .
  • One specific organization of the gate, data and bias lines is shown in FIG. 1 , but alternative arrangements are possible.
  • the bias lines 30 , 32 , and 34 could be parallel to the data lines 20 , 22 , and 24 rather than to the gate lines 14 , 16 , and 18 .
  • some of the TFTs 12 include a jet-printed semiconductor layer 38 .
  • polymers or soluble organic small molecules offer the best choice for a solution-based semiconductor layer, and they can be jet-printed effectively. Jet-printing of polymer TFTs in the structure shown in FIG. 1 is described in, for example, A. Arias, S. E. Ready, R. Lujari, W. S. Wong, K. E. Paul, A. Salleo, R. Apte, Y. Wu, P. Liu, B. Ong and R. A. Street, “ Jet - printed polymer thin film transistor display backplanes ”, Applied Physics Letters, 85, 3304 (2004). Encapsulation of the polymer may be employed to extend the life of the TFT.
  • Multi-ejector print-heads are available that will print the required pattern quickly and reliably. Only the final deposition of the polymer must be performed by jet-printing so that each device can be made with a unique encoded pattern.
  • the other layers of the FET gate metal, dielectric and source-drain metal
  • these layers may be patterned by printing, this is not required and other methods, such as conventional photolithography, could be used instead.
  • the TFT shown in FIG. 2 is a bottom gate device typical of the structure that is commonly used for TFT. However a top gate device could also be used.
  • the TFT comprises an insulating substrate 40 , a metal gate contact 42 , an insulating gate dielectric 44 , the semiconductor layer 38 , and the metal source and drain contacts 26 and 28 (referred to as the TFT contacts).
  • any number of gate lines may be formed on the insulating substrate 40 .
  • a gate insulating layer preferably made of silicon nitride (SiN x ) or silicon oxide may be formed on the gate lines.
  • the metal source and drain contacts 26 and 28 are applied before the semiconductor 38 , in what is known as a coplanar configuration.
  • An alternative configuration known as the staggered configuration has the source and drain deposited after the semiconductor. Any of these TFT configurations will perform adequately, but the bottom gate coplanar configuration is preferred for jet printing the polymer semiconductor 38 .
  • the electronic device with unique encoding operates like a conventional active matrix addressed array. That is, a gate pulse of appropriate voltage, which for the polymer TFT would be a negative voltage typically in the range ⁇ 10 to ⁇ 30 V, is applied to address each row of TFTs in turn, while the other rows are held in the off-state at typically +5 to +20V.
  • TFTs 12 b, 12 d, 12 e, and 12 i will respond by forming a conducting link between the data line ( 20 , 22 or 24 ) and the common bias line 36 , while the non-printed TFTs (i.e., 12 a, 12 c, 12 f, 12 g, and 12 h ) remain in a high resistance state.
  • the gate voltage is turned off and the subsequent gate lines are turned on in sequence.
  • the result is a unique output bit stream of the encoded device, which matches the specific pattern of printed TFTS.
  • a “1” in the bit stream corresponds to a printed TFT, while a “0” in the bit stream corresponds to a non-printed TFT.
  • the encoded output bit stream is 010110001.
  • the signals from the TFTs are detected by readout electronics 46 , 48 and 50 , which comprise circuitry outside of the TFT array 10 , either integrated next to the TFT array or external to the TFT array 10 (e.g., in a silicon IC).
  • the purpose of the readout electronics 46 , 48 and 50 is to provide the encoded output of the TFT array 10 to the electronic system, which will use the information. Hence, the details of the readout electronics 46 , 48 and 50 will depend on the specific needs of the electronic system.
  • the readout electronics 46 , 48 and 50 will typically contain a sense amplifier, which amplifies the output of the TFT array 10 and creates the encoded bit stream that is used by the electronic system.
  • the signal is binary so that the readout electronics 46 , 48 and 50 minimally require a discriminator to identify the state of the corresponding bit.
  • the sense amplifier could be by voltage sensing, charge sensing or current sensing, as is conventionally used to amplify small signals.
  • the readout electronics 46 , 48 and 50 also provide the signals to apply gate voltage pulses in sequence.
  • FIG. 3 An illustration of how the signal develops and is sensed after the gate pulse is applied is shown in FIG. 3 , which compares the results from TFTs with and without the printed semiconductor 38 .
  • the first curve 51 shows the gate voltage (V G ) versus time, while the second curve 52 below it shows the corresponding charge or voltage portion 54 and 56 for a printed TFT and a not-printed TFT, respectively.
  • V G gate voltage
  • the second curve 52 shows the corresponding charge or voltage portion 54 and 56 for a printed TFT and a not-printed TFT, respectively.
  • a gate pulse is applied to the first row of TFTs (e.g., 12 a, 12 b and 12 c, ) any printed TFTs in that row (e.g., 12 b ) become conducting.
  • a current flows from the bias line 30 to the data line 24 until the two are at the same voltage.
  • the gate When the gate is turned off, there will be a high voltage on the data lines corresponding to the printed TFTs and the voltage will be sensed ( 58 ). Following a reset ( 60 ), there will be a low voltage on the data lines corresponding to the non-printed TFTs. The low voltage will not be exactly zero because of leakage currents and capacitance transients ( 62 ) in the circuit, nor will the high voltage exactly equal the bias line voltage, for the same reasons. However, so long as there is a sufficient difference between the high and low voltage, the readout electronics, including a voltage sensing amplifier, can discriminate between the “1” and the “0” encoding.
  • the readout electronics 46 , 48 , and 50 can be configured with a charge sensing readout amplifier, which will detect the high or low amount of charge as the “1” and “0” encoding.
  • the fundamental speed of the TFT is given by L 2 / ⁇ V G, where L is the TFT length, ⁇ is the mobility and V G is the gate voltage.
  • L is the TFT length
  • ⁇ is the mobility
  • V G is the gate voltage.
  • Present jet-printing spatial resolution allows a channel length of about 20 ⁇ m and, therefore, a minimum gate pulse of 10-20 ⁇ s.
  • a 1000-bit encoded array can be read out in less that 1 ms. If the TFT array is made by conventional photolithography, except for the final step of jet-printing the polymer, then smaller feature sizes are possible as well as faster operation.
  • TAB Tape Automated Bonding
  • wirebond refers to the process where tiny wires are connected from chip bond pads to the leadframe.
  • a shift register a high-speed circuit that holds some number of bits for the purpose of shifting them left or right
  • output multiplexer could be made from the polymer materials.
  • the multiplexer reduces the number of interconnects by selecting gate or data lines in the TFT array with additional TFTs When a multiplexer is used, the read time would be longer but the interconnections would be considerably simpler. Even limited multiplexing provides an attractive simplification of the electronics.
  • Jet-printing is the preferred technique to form the unique encoding device, because the desired pattern is formed without the use of a physical mask and can be defined by software instructions to the printer. Jet-printing refers to any technique to deposit a printed pattern with single or multiple nozzles and includes the piezo-electric or thermal ejection techniques that are well known in printing technology.
  • An alternative embodiment of the electronic device with unique encoding uses amorphous silicon or poly-silicon for the TFT semiconductor, as in a conventional TFT array, and uses the jet-printer to print an etch mask to pattern the a-Si or p-Si layer. In locations where the mask is not printed, the etching process will remove the semiconductor layer and therefore only the printed subset of TFTs will turn on.
  • Amorphous silicon is the non-crystalline allotropic form of silicon.
  • amorphous silicon is used as the active layer in thin-film transistors (TFTs) which are most widely used in large-area electronics applications, mainly for liquid-crystal displays (LCDs).
  • TFTs thin-film transistors
  • Polycrystalline silicon or polysilicon or poly-Si is a material consisting of multiple small silicon crystals, and has long been used as the conducting gate material in MOSFET and CMOS processing technologies. For these technologies it is deposited using LPCVD reactors at high temperatures and is usually heavily n or p-doped.
  • Intrinsic and doped polysilicon has been used in large-area electronics as the active and/or doped layers in thin-film transistors. Although it can be deposited by low-pressure chemical-vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or solid-phase crystallization (SPC) of amorphous silicon in certain processing regimes, these processes still require relatively high temperatures of at least 300° C. These temperatures make deposition of polysilicon possible for glass substrates, but not for plastic substrates. Instead, a relatively new technique called laser crystallization can be used to crystallize a precursor amorphous silicon (a-Si) material on a plastic substrate without melting or damaging the plastic.
  • LPCVD low-pressure chemical-vapor deposition
  • PECVD plasma-enhanced chemical vapor deposition
  • SPC solid-phase crystallization
  • Short, high-intensity ultraviolet laser pulses are used to heat the deposited a-Si material to above the melting point of silicon, without melting the entire substrate.
  • the molten silicon will then crystallize as it cools.
  • researchers have been able to grow very large grains, of up to hundreds of micrometers in size in the extreme case, although grain sizes of 10 nanometers to 1 micrometer are also common.
  • a crystal grain size smaller than the device feature size is needed for homogeneity of the devices.
  • polysilicon over a-Si is that the mobility can be orders of magnitude larger and the material also shows greater stability under electric field and light-induced stress. This allows more complex, high-speed circuitry to be created on the glass substrate along with the a-Si devices, which are still needed for their low-leakage characteristics.
  • hybrid processing When polysilicon and a-Si devices are used in the same process this is called hybrid processing.
  • a complete polysilicon active layer process is also used in some cases where a small pixel size is required, such as in projection displays.
  • FIG. 4 shows an alternative TFT array 66 wherein elements shared with the first embodiment are denoted by like reference numerals.
  • the TFTs that will remain connected can be selected by printing an etch mask (e.g., 68 b, 68 d, 68 e, and 68 i ) in selected locations.
  • the location selected is one of the source-drain contacts ( 26 or 28 ) to the TFT rather than the gate contact, but the gate contact could be patterned in the same way.
  • One way to pattern the device is to use conventional photolithography to define the etch mask for the entire source-drain metal layer, except for a chosen area of the contact region that has a customized pattern. This region is then jet-printed with an etch mask to select the TFTs that will operate, as shown in FIG. 4 .
  • the metal layer is then etched, and the resist is stripped in the usual manner.
  • the encoded output bit stream (e.g., 010110001) may be determined by the readout electronics 46 , 48 , and 50 as described above.
  • FIG. 5 another alternative TFT array 70 incorporates printed metal bridges.
  • a metal connection e.g., 72 b, 72 d, 72 e, and 72 i
  • TFTs e.g., 12 b, 12 d, 12 e, and 12 i
  • the metal connection determines whether or not the TFT is connected to the gate pulses that come from the readout electronic circuitry.
  • FIG. 5 illustrates this approach for the case where the printed bridge is the connection to the TFT gate electrode. It is also possible to print the bridge at the source or drain contact ( 26 or 28 ).
  • the gate metal could be patterned by conventional lithography, leaving a gap between the address line and the gate electrode. The gap is selectively bridged by jet-printing. Alternatively, the complete gate metal layer could be jet-printed in the desired pattern. Again, a gate pulse is applied and the output bit stream (e.g., 010110001) may be determined by the readout electronics 46 , 48 , and 50 as described above.
  • PEDOT conducting polymers
  • metals e.g. nanoparticle gold or other metal particles in suspension
  • carbon nanotubes e.g. carbon nanotubes
  • the TFT array could include a compensation line, which is an additional row of TFTs without the semiconductor. This compensation line would provide a signal to the sense amplifiers corresponding to response of the parasitic capacitance, which can then be directly corrected for improving the sensitivity.
  • the format of the TFT array can be chosen to optimize some aspect of the performance. For example, an array with an equal number of gate and sense lines minimizes the number of electrical contacts. Alternatively, the readout speed can be enhanced by providing fewer gate line and more sense lines, which would provide a faster response.
  • the electronic encryption devices described above can be built directly on a silicon integrated circuit and fabricated in such a way that each device has a unique encoding built into its physical structure.
  • PCB printed circuit board
  • a PCB 80 having multiple external terminals or leads 82 a - 82 g.
  • a mask or a metal layer may be jet-printed to connect the leads to a voltage source 86 and make a unique identifying electrical circuit in the PCB.
  • Some of the metal traces can be connected and some left unconnected using the known printing techniques.
  • the voltage on the external leads can be measured by an electronic circuit (either on or external to the PCB) to identify the board.
  • PCBs usually contain many patterned layers, and only one of them needs to be printed in this way. Therefore, most of the PCB layers can be made by conventional means.
  • the unique printed identifier circuit on an electronic device in addition to the applications in security described above. These applications include, for example, identifying a specific device or device type and personalizing devices.
  • the custom circuit could inform a PC about the type of display or other peripheral device that has been installed. It could be used to keep track of which version of firmware was in used on a specific PBC.
  • a unique printed TFT array could be part of a liquid crystal display (for example the circuit could be placed around the periphery of the main part of the display). This could be patterned to give unique appearance for decoration (e.g. color, pattern), or for information (e.g. status of a cell phone, name of the owner).

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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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JP2006340138A JP5192686B2 (ja) 2005-12-21 2006-12-18 固有の符号化機能を備える電子デバイス
EP06126615A EP1801879A3 (en) 2005-12-21 2006-12-20 Electronic Device with Unique Encoding
US12/645,987 US7897439B2 (en) 2005-12-21 2009-12-23 Electronic device with unique encoding

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CN109087925A (zh) * 2018-08-09 2018-12-25 京东方科技集团股份有限公司 阵列基板、x射线平板探测器及x射线探测方法
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JP2017510017A (ja) * 2014-02-11 2017-04-06 アイメック・ヴェーゼットウェーＩｍｅｃ Ｖｚｗ 薄膜電子回路をカスタマイズするための方法
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CN109087925A (zh) * 2018-08-09 2018-12-25 京东方科技集团股份有限公司 阵列基板、x射线平板探测器及x射线探测方法
WO2020199155A1 (zh) * 2019-04-03 2020-10-08 深圳市汇顶科技股份有限公司 薄膜半导体结构以及相关操作方法及具指纹感测功能的手持装置

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JP2007180543A (ja) 2007-07-12
US7897439B2 (en) 2011-03-01

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