US20070132868A1 - Signal generator and method for generating signals for reducing noise in signals - Google Patents

Signal generator and method for generating signals for reducing noise in signals Download PDF

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Publication number
US20070132868A1
US20070132868A1 US11/524,436 US52443606A US2007132868A1 US 20070132868 A1 US20070132868 A1 US 20070132868A1 US 52443606 A US52443606 A US 52443606A US 2007132868 A1 US2007132868 A1 US 2007132868A1
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array
noise
reference signal
signal
pixel
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Myoung-su Lee
June-Soo Han
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HAN, JUNE-SOO, LEE, MYOUNG-SU
Publication of US20070132868A1 publication Critical patent/US20070132868A1/en
Priority to US12/230,882 priority Critical patent/US7864229B2/en
Priority to US12/801,942 priority patent/US8072512B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
    • H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree
    • H03M1/765—Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals

Definitions

  • the invention relates to signal generators and methods for generating signals, which may be employed by image sensors. More particularly, one or more aspects of the invention relate to complimentary metal oxide semiconductor (CMOS) image sensors and methods of operating CMOS image sensors having improved noise reduction and/or elimination properties and improved image quality.
  • CMOS complimentary metal oxide semiconductor
  • Image sensors may be employed in various fields, e.g., robotics, transportation, automobiles, satellite-based instrumentation, navigation, etc.
  • Image sensors may include a two-dimensional array of pixels formed on a semiconductor substrate, and such a pixel array may correspond to an image field of an image frame.
  • Image sensors may include a photoelectric conversion element that is capable of accumulating a quantity of electrical charge corresponding to an amount of detected energy, e.g., visible light, etc.
  • each pixel of a pixel array may include such a photoelectric conversion element and when photons impact a surface of the photoelectric conversion element, free charge carriers may be produced. These free charge carriers may then be collected by the respective photoelectric conversion element. The collected charge carriers may then be converted to an output signal, e.g., a voltage or a current, corresponding to the respective quantity of collected free charge carriers.
  • Each of the pixels of the pixel array may output a respective output signal and each of the output signals may be supplied to an output circuit and employed to generate an image corresponding to the amount of detected energy.
  • CMOS image sensors may be advantageous because, e.g., CMOS image sensors may be fabricated using, e.g., standard CMOS processes, may be integrated with other CMOS devices and circuitry on a single chip enabling miniaturization of devices, may employ relatively low operating voltages, and may consume relatively less power.
  • CMOS image sensors generally need to employ a high resolution analog-to-digital converter (ADC) for converting an analog signal received from an active pixel sensor (APS) to a digital signal.
  • ADC analog-to-digital converter
  • the quality of image(s) produced by an image sensor may be directly related to a signal to noise (S/N) ratio of the image sensor, e.g., the higher the S/N ratio of an image sensor, the higher the quality, e.g., resolution, of images produced by that image sensor.
  • S/N signal to noise
  • CMOS image sensors may employ, e.g., ADCs that perform correlated double sampling (CDS).
  • CDS correlated double sampling
  • Such an ADC that also performs CDS may reduce noise characteristics corresponding to aspects of the ADC itself.
  • ADCs that perform CDS may not reduce and/or eliminate other types of noise, e.g., power supply noise generated by a portion(s) of the respective pixel other than the respective ADC.
  • One or more aspects of the invention is therefore directed to signal generators and methods for generating signals, which may be employable by image sensors and which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
  • At least one of the above and other features and advantages of the present invention may be realized by providing a method for operating a CMOS image sensor including an active pixel sensor array and a noise canceller array corresponding to the active pixel sensor array, the method involving generating a varying reference signal that mirrors noise external to the active pixel sensor array, outputting the varying reference signal to the noise canceller array, and using the varying reference signal in the noise canceller array to cancel noise both internal to and external to the active pixel sensor array.
  • Generating the varying reference signal may involve mirroring noise in a power supply supplying power to the active pixel sensor array.
  • Mirroring noise in the power supply may involve creating a replicated signal in accordance with pixel functioning of a pixel in the active pixel sensor array and power from the power supply.
  • Generating the varying reference signal may involve adding the replicated signal to a constant reference signal. Creating the replicated signal may involve providing an optical black pixel having a pixel structure equivalent to that of the pixel in the active pixel sensor array and supplying power from the power supply to the optical black pixel.
  • Creating the replicated signal may involve providing an equivalent circuit having a response to input power equal to that of the pixel in the active pixel sensor array and supplying power from the power supply to the equivalent circuit.
  • Generating the varying reference signal may involve mirroring switching offset noise within the noise canceller array.
  • Generating the varying reference signal may involve supplying the replicated signal to a dummy noise canceller having an equivalent structure to that of a noise canceller of the noise canceller array.
  • Generating the varying reference signal may involve mirroring switching offset noise within the noise canceller array.
  • Generating the varying reference signal may involve supplying a constant reference signal to a dummy noise canceller having an equivalent structure to that of a noise canceller of the noise canceller array.
  • At least one of the above and other features and advantages of the present invention may be separately realized by providing an apparatus for use with a CMOS image sensor including an active pixel sensor array and a noise canceller array corresponding to the active pixel sensor array, the apparatus including a varying reference signal generator to generate a varying reference signal that mirrors noise external to the active pixel sensor array and to output the varying reference signal to the noise canceller array.
  • the varying reference signal may mirror noise in a power supply supplying power to the active pixel sensor array.
  • the apparatus may include a replication unit for creating a replicated signal in accordance with pixel function of a pixel in the active pixel sensor array and power from the power supply.
  • the varying reference signal generator may include a comparator for adding the replicated signal and a constant reference signal.
  • the replication unit may include an optical black pixel having a pixel structure equivalent to that of the pixel in the active pixel sensor array, the optical black pixel receiving power from the power supply.
  • the replication unit may include an equivalent circuit having a response to input power equal to that of the pixel in the active pixel sensor array, the equivalent circuit receiving power from the power supply.
  • the varying reference signal may mirror switching offset noise within the noise canceller array.
  • the varying reference signal generator may include a dummy noise canceller having an equivalent structure to that of a noise canceller of the noise canceller array, the dummy noise canceller may receive the replicated signal.
  • the varying reference signal may mirror switching offset noise within the noise canceller array.
  • the varying reference signal generator may include a dummy noise canceller having an equivalent structure to that of a noise canceller of the noise canceller array.
  • the varying reference signal generator may include a plurality of dummy noise cancellers.
  • FIG. 1 illustrates a general block diagram of an exemplary CMOS image sensor employable with one or more aspects of the invention
  • FIG. 2 illustrates a schematic diagram of an exemplary pixel of a CMOS image sensor employable with one or more aspects of the invention
  • FIG. 3 illustrates a schematic diagram of an exemplary CDS array employable with one or more aspects of the invention
  • FIG. 4 illustrates a timing diagram of a conventional CMOS image sensor
  • FIG. 5 illustrates a block diagram of a first exemplary embodiment of a CMOS image sensor employing one or more aspects of the invention
  • FIG. 6 illustrates a schematic diagram of the exemplary CDS array shown in FIG. 3 being employed according to one or more aspects of the invention with an exemplary reference voltage generator;
  • FIG. 7 illustrates an exemplary timing diagram of an exemplary CMOS image employing one or more aspects of the invention
  • FIG. 8 illustrates another exemplary embodiment of a reference voltage generator, according to one or more aspects of the invention.
  • FIG. 9 illustrates a block diagram of a second exemplary embodiment of a CMOS image sensor employing one or more aspects of the invention.
  • FIG. 10 illustrates a schematic diagram of an exemplary embodiment of a pixel noise replica unit according to one or more aspects of the invention.
  • FIG. 1 illustrates a general block diagram of an exemplary CMOS image sensor employable with one or more aspects of the invention
  • FIG. 2 illustrates a schematic diagram of an exemplary pixel 22 of a CMOS image sensor employable with one or more aspects of the invention.
  • a CMOS image sensor 5 may include a row driver 10 , an APS (active pixel sensor) array 20 , a CDS (correlated double sampling) array 30 , a digital code output unit 40 and a reference voltage generator 50 .
  • the row driver 10 may receive a timing signal and/or one more control signals from a controller (not shown), and may supply a plurality of driving signals to the APS array 20 .
  • the driving signals may control a read-out operation, i.e., reading of the charge absorbed, of pixels of the APS array 20 .
  • the driving signals may include, e.g., a reset signal RX, a transfer signal TX and/or a pixel selection signal SEL.
  • the driving signals may be supplied to the APS array 20 in a row-wise manner, such that, e.g., driving signals corresponding to respective rows of the APS array 20 may be sequentially supplied.
  • the APS array 20 may include a plurality of pixels 22 , each of which may have the exemplary structure illustrated in FIG. 2 .
  • the pixels 22 may be arranged in a row-by-column matrix and may include, e.g., n rows and m columns such that the APS array may include n ⁇ m pixels 22 , where n and m are both integers.
  • Each of the pixels 22 may absorb light reflected from an object in an image frame and may convert the absorbed light energy into an electrical signal.
  • the APS array 20 may receive a plurality of driving signals from the row driver 10 . Electrical signals produced by each of the pixels 22 of the APS array 20 may be supplied to the CDS array 30 .
  • each of the pixels 22 may include a photoelectric conversion element PD, reset element T RX , a transfer element T TX , a charge detection element N, an amplifying unit T AMP , and a selection element T SEL .
  • the photoelectric conversion element PD may be, e.g., a photodiode, a phototransistor, a photogate, a Pinned Photo Diode (PPD), etc.
  • the photoelectric conversion element PD may collect charge generated by absorbing light reflected from an object.
  • the transfer element T TX may be, e.g., a switch or a transistor for transferring charge collected by the photoelectric conversion element PD to the charge detection element N.
  • the transfer element T TX may include, e.g., one or more transistors. In the illustrated example, the transfer element T TX may be controlled by the transfer signal TX.
  • the reset element T RX may be, e.g., a switch or a transistor for transferring the reset signal RX. In the illustrated example, the reset element T RX may be controlled by the reset signal RX. The reset element T RX may periodically reset the charge detection element N. As shown in the illustrated example, the reset element T RX may have a drain connected to an external power source VDD_P.
  • the charge detection element N may be, e.g., a floating diffusion (FD) region.
  • the charge detection element N may correspond to an electrical node between the transfer element T TX and the amplifying unit T AMP , and may respectively receive the charge collected by the photoelectric conversion element PD via the transfer element T TX .
  • the charge detection element N may be connected to a source of the reset element T RX , a gate of the amplifying unit T AMP , and/or the transfer element T TX .
  • the charge detection element may have a parasitic capacitance, whereby charges may be cumulatively collected.
  • a capacitor Cp is shown, which may correspond to a parasitic capacitance and not a discrete additional component.
  • the amplifier T AMP may be, e.g., a source follower amplifier in combination with a constant current generator (not shown), which may be external to the pixel 22 .
  • the amplifier T AMP may output an output signal OUT, which may be, e.g., a variable voltage corresponding to the voltage received by the charge detection element N.
  • a source of the amplifier T AMP may be connected to a drain of the selection element T SEL and a drain of the selection element T SEL may be connected to the external power source VDD_P.
  • the selection element T SEL may enable selection of the respective pixel 22 to be read in a row-wise manner.
  • the respective pixel 22 may output a pixel output signal APS_O.
  • a gate of the selection element T SEL may receive the respective pixel selection signal SEL, and a source of the selection element T SEL may be connected to a bias current source I BIAS , which may be connected to a ground voltage source VSS_P.
  • the reset signal RX may control a reset operation for the pixels 22 of the APS array 20 .
  • a reset signal RX k corresponding to the k-th row of the APS array 20 may be applied to reset one or more pixels 22 arranged in the k-th row of the APS array 20 .
  • the respective reset signals RX may be supplied via corresponding electrical paths (not shown) connecting the row driver 10 the APS 20 .
  • the transfer signal TX may control the transfer element T TX .
  • the pixel selection signal SEL may control the selection of pixels 22 in the APS array 20 .
  • a pixel selection signal SEL k corresponding to the k-th row of the APS array 20 may select one or more pixels arranged in the k-th row of the APS array 20 .
  • the respective pixel selection signals SEL may be supplied via a corresponding electrical path (not shown) connecting the row driver 10 to the corresponding row of the APS array 20 .
  • the n rows of the APS array 20 may be, e.g., sequentially selected based on, e.g., the pixel selection signal SEL, and each of the pixels 22 in, e.g., a selected row of, the APS array 20 may output a respective output signal APS_O to the CDS array 30 .
  • the exemplary APS array 20 with n rows and m columns as discussed above, during a time period corresponding to the selected one of the n rows of the APS array 20 , m respective APS output signals APS_O_ 1 to APS_O_m may be output to the CDS array 30 .
  • Characteristics e.g.
  • a voltage of an output signal supplied by one of the pixels 22 may change.
  • a voltage of the respective APS output signal may correspond to a reset voltage Vres associated with the respective reset signal RX supplied to that pixel 22 .
  • a voltage of the respective APS output signal being supplied to the CDS array 30 , by the same pixel 22 may correspond to an image signal voltage Vsig.
  • Each of the respective APS output signals APS_O_ 1 to APS_O_m may correspond to a respective output voltage Vout, which may include the reset voltage Vres and the image signal voltage Vsig.
  • Vout may include the reset voltage Vres and the image signal voltage Vsig.
  • the reset and image signal voltages Vres, Vsig may be sequentially supplied by the respective pixel 22 of the APS array 20 to the CDS array 30 .
  • the CDS array 30 may perform correlated double sampling based on the received voltages, e.g., the respective reset voltage Vres and the respective image signal voltage Vsig.
  • FIG. 3 illustrates a schematic diagram of an exemplary CDS array 30 employable with one or more aspects of the invention.
  • the CDS 30 may include a plurality of CDS circuits 32 , 34 , 36 . Although three CDS circuits 32 , 34 , 36 are shown, the CDS array 30 may include any number of CDS circuits 32 , 34 , 36 .
  • Each of the CDS circuits 32 , 34 , 36 may include one or more switches, one or more capacitors, and one or more comparators and/or amplifiers.
  • each of the CDS circuits 32 , 34 , 36 may include four switches, e.g., S 1 , S 2 , S 3 , S 4 , blocking capacitor C 1 , a signal storing capacitor C 2 , a signal transfer capacitor C 3 , a comparator A 1 , and an amplifier A 2 .
  • switches e.g., S 1 , S 2 , S 3 , S 4 , blocking capacitor C 1 , a signal storing capacitor C 2 , a signal transfer capacitor C 3 , a comparator A 1 , and an amplifier A 2 .
  • the CDS array 30 may include, e.g., m CDS circuits, i.e., one CDS circuit for each of the m columns of the exemplary APS array 20 , and each of the m CDS circuits may respectively receive the respective APS output signal APS_O_ 1 to APS_O_m, including the respective reset voltage Vres and the respective image signal voltage Vsig, and may respectively output a CDS output signal CDS_O_ 1 to CDS_O_m.
  • Each CDS circuit, e.g., 32 , 34 , 36 may also receive a reference signal REF and a ramp signal RAMP, e.g., a voltage ramping signal, as shown in FIG. 3 .
  • the reference signal REF may be generated and supplied to the CDS array 30 by the reference voltage generator 50 .
  • the ramp signal RAMP may be supplied to the CDS array 30 by, e.g., a ramp signal generator (not shown).
  • the respective APS output signal e.g., APS_O_ 1 including the respective reset voltage Vres and the respective image signal voltage Vsig
  • the respective CDS circuit 32 may be supplied to the respective CDS circuit 32 , via switch S 1 and the ramp signal RAMP may be supplied to the CDS circuit 32 via switch S 2 .
  • the blocking capacitor C 1 may be connected between the switch S 1 and the signal storing capacitor C 2 , and the switch S 2 .
  • the switch S 3 may be connected in parallel with an input terminal IN of the comparator A 1 and an output terminal of the comparator A 1 .
  • the reference signal REF may be supplied to another input terminal of the comparator A 1 .
  • the signal transfer capacitor C 3 may be connected between an output terminal DIFF of the comparator A 1 and an input terminal of the amplifier A 2 .
  • the switch S 4 may be connected in parallel with the input terminal of the amplifier A 2 and an output terminal of the amplifier A 2 , which may correspond to the respective one of CDS output signals CDS_O_ 1 to CDS_O_m.
  • FIG. 4 illustrates a timing diagram of a conventional CMOS image sensor.
  • the reset signal RX, the transfer signal TX and the pixel selection signal SEL are omitted from the timing diagram illustrated in FIG. 4 .
  • the respective output voltage Vout may be relatively high. More particularly, during the period when reset signal sampling is performed, a respective reset signal RX associated with the respective pixel 22 may be high, i.e., the reset voltage Vres output by the respective pixel 22 may high.
  • the switches S 1 , S 2 , S 3 , S 4 may be turned on. In the example illustrated in FIG. 4 , the switch S 3 is turned off at time ( 2 ), and the switches S 1 , S 2 , and S 4 are turned off at time ( 3 ).
  • the respective voltage Vout of the APS output signal APS_O_ 1 to APS_O_m is reduced from the reset voltage Vres by an image signal voltage Vsig output by the same respective pixel 22 of the APS array 20 .
  • a voltage at the input terminal of the comparator A 1 reflects the drop in voltage of the respective voltage Vout of the respective APS output signal APS_O_ 1 to APS_O_m.
  • noise resulting from the power supply e.g., power supply voltage VDD_P
  • VDD_P power supply voltage
  • the reference voltage Vref of the reference signal REF that may be supplied by the reference voltage generator 50 reflects no or a negligible amount of noise.
  • the impact of noise included in the respective output voltage Vout of the respective APS output signal APS_O_ 1 to APS_O_m on the resulting signal output by the CDS array 30 may be illustrated by the following relationships.
  • V IN — 1 V ref + ⁇ V S3 + ⁇ V POWER
  • the switch S 3 may turn off and may be a dominant cause of signal noise during the reset signal sampling period.
  • V IN — 2 V ref+ ⁇ V S3 + ⁇ V POWER ⁇ V sig
  • V ref ⁇ V S3 + ⁇ V POWER ⁇ V sig
  • Vref and Vdiff_res_sig may be as follows.
  • V IN_ ⁇ 2 ⁇ Vref + ⁇ ⁇ ⁇ V S ⁇ ⁇ 3 + ⁇ ⁇ ⁇ V POWER - Vsig
  • CMOS image sensors and methods of operating CMOS image sensors that can reduce and/or eliminate the noise resulting, e.g. from the power supply and/or sources outside of the APS array 20 are desired.
  • FIG. 5 illustrates a block diagram of a first exemplary embodiment of a CMOS image sensor 105 employing one or more aspects of the invention. For simplicity, only differences between the exemplary embodiment of the CMOS image sensor 105 shown in FIG. 5 and the CMOS image sensor 5 described above in relation to FIGS. 1-3 will be described below.
  • the CMOS image sensor 105 may include a row driver 110 , an APS array 120 , a CDS array 130 , a digital code output unit 140 . Aspects of the invention may employ a reference voltage generator 150 .
  • the CMOS image sensor 105 may also include an optical black (OB) pixel array 122 .
  • OB optical black
  • the OB pixel array 122 may generally be provided in an image sensor to carry out automatic level compensation (ADLC), i.e., compensate for a pixel's voltage level offset.
  • ADLC automatic level compensation
  • the reference voltage generator 150 may employ the OB pixel array 122 to copy the power supply noise and supply the reference voltage generator 150 with an output signal OB_O including noise resulting from, e.g., a power supply, etc., outside of the CDS array 130 of the CMOS image sensor 105 .
  • the OB pixel array 122 may include a plurality of OB pixels arranged in one or more columns and one or more rows.
  • the number of rows of the OB pixel array 122 may correspond to a number of rows of the APS array 120 , e.g., the OB pixel array 122 may have n rows.
  • the OB pixel array 122 may be utilized in a variety of ways. One, some or all of the columns of the OB pixel array 122 may correspond to one of the m columns of the APS array 120 in order to replicate the noise, e.g., the power supply noise.
  • the OB pixel array 122 includes a plurality of columns corresponding to columns of the APS array 120
  • some or all of the respective output signals OB_O may be connected together as a single signal to the reference voltage generator 150 .
  • each of the respective output signals OB_O of the plurality of columns of the OB pixel array 122 may be used separately.
  • output signals OB_O of the OB pixel array 122 may be separated into groups, and a corresponding number of respective output signals OB_O may be output to the reference voltage generator 150 .
  • each output signal OB_O of each column of the OB pixel array 120 may be based on one, some or all of the OB pixels of the respective column of the OB pixel array 120 .
  • the exemplary embodiment of the reference voltage generator 150 may receive the output signal OB_O from the OB pixel array 122 , a ramp signal RAMP_R, and a REF_OB signal, and may supply a REF_C signal to the CDS array 130 via amplifier A 3 (shown in FIG. 6 ).
  • the CDS array 130 , the APS array 120 , the digital code output unit 140 , and the row driver 110 may have, e.g., structures corresponding to the CDS array 30 , the APS array 20 , the digital code output unit 40 , and the row driver 10 of the CMOS image sensor shown in FIGS. 1-3 .
  • a ramp signal generator may generate a plurality of ramp signals, e.g. RAMP_R and RAMP_C.
  • the RAMP_R signal may be supplied to the reference voltage generator 150 and the RAMP_C signal may be supplied to the CDS array 130 .
  • the RAMP_R signal may be supplied to the reference voltage generator 150 and may not have any voltage variation.
  • the RAMP_R signal supplied to the reference voltage generator 150 may be a substantially constant or completely constant voltage signal, even before, at or after time ( 6 ) where the RAMP_C signal may begin increasing.
  • the REF_OB signal may correspond to a noise free reference signal generated by, e.g., a known, reference voltage generator, e.g., 50 in FIG. 1 .
  • the REF_C signal may include noise resulting from, e.g., factors outside of the CDS array 130 . Such noise factors may be, e.g., power supply noise, clock feed-through noise due to on/off switching operations.
  • the OB pixel array 122 may be employed by the reference voltage generator 150 to generate a signal having the same or substantially the same noise characteristics as signals of the CMOS image sensor 105 such that the output REF_C signal may cancel all or substantially all of the noise degrading the quality of signals within the CMOS image sensor 105 .
  • a reference voltage signal e.g., REF_C that includes all or substantially all of the noise degradation affecting the signals within the CMOS image sensor, the effect of noise on image quality may be reduced and/or eliminated.
  • the reference voltage generator 150 may include a CDS circuit structure that corresponds to CDS circuits in the CDS array 130 .
  • the reference voltage generator 150 may include the same CDS circuit structure as that of the corresponding CDS array 130 and thus, clock feed-through noise due to, e.g., on/off switching operations may be copied to the generated reference voltage signal REF_C.
  • FIG. 6 illustrates a schematic diagram of the exemplary CDS array 130 shown in FIG. 3 being employed according to one or more aspects of the invention with the exemplary reference voltage generator 150 . Only differences between the CDS array 130 illustrated in FIG. 6 and the CDS array 30 illustrated in FIG. 3 will be described below.
  • CDS array 130 illustrated in FIG. 6 corresponds to the CDS array 30 illustrated in FIG. 3
  • aspects of the invention may be employed with the CDS array 30 illustrated above in FIG. 3 .
  • embodiments of the invention may employ a noise canceling device, e.g., the voltage generator 150 , in lieu of, e.g., the voltage generator 50 , in addition to, e.g., the voltage generator 50 to cancel noise that may result from factors beyond the CDS array 130 .
  • a noise canceling device e.g., the voltage generator 150
  • the voltage generator 50 e.g., the voltage generator 50
  • the reference voltage generator 150 may employ the output signal OB_O from the OB pixel array 122 , the RAMP_R signal, the REF_OB signal, and a structure 152 corresponding to the structure of a CDS circuit 132 , 134 , 136 , of the corresponding CDS array 130 to generate a reference voltage signal REF_C including noise that substantially or completely corresponds to noise terms resulting from, e.g. power supply and/or clock feed-through, e.g., ⁇ V S3 , ⁇ V POWER and ⁇ V S1 , as discussed above.
  • FIG. 7 illustrates an exemplary timing diagram of an exemplary CMOS image employing one or more aspects of the invention.
  • Operation of the switches S 1 , S 2 , S 3 , S 4 may correspond to operation of the switches S 1 , S 2 , S 3 , S 4 in the timing diagram shown in FIG. 4 .
  • the RAMP_C signal may correspond to the RAMP signal shown in FIG. 4 .
  • the output voltage Vout signal may substantially or completely correspond to the Vout signal shown in FIG. 4 .
  • the RAMP_R signal supplied to the reference voltage generator 150 may be a substantially constant or completely constant voltage signal, even before, at or after time ( 6 ) where the RAMP_C signal may begin increasing.
  • the reference voltage signal REF_C supplied to the CDS array 130 may be generated based on the respective output signal OB_O from the OB pixel array 122 , which may copy, e.g, the power supply noise, to the noise free reference voltage REF_OB.
  • an output signal Vdiff of the comparator A 1 may not include, e.g., the power supply noise.
  • the voltage signal Vref_c of the REF_C signal may cancel noise existing in the Vout signal such that the resulting output Vdiff does not include any or substantially all of the noise, e.g., the power supply noise.
  • embodiments of the invention enable quality of image signals and thus, image quality, may be improved.
  • the switch S 3 turns off and is a dominant cause of signal noise during the reset signal sampling period.
  • V IN — 2 V ref+ ⁇ V S3 + ⁇ V POWER ⁇ V sig
  • Vdiff_res_sig signal multiple sources of noise, e.g., ⁇ V S3 , ⁇ V POWER and ⁇ V S1 may be canceled and components intended to be transferred, e.g., Vsig and V RAMP may be transferred with no noise or substantially no noise.
  • FIG. 8 illustrates another exemplary embodiment of a reference voltage generator, according to one or more aspects of the invention.
  • the second embodiment of the reference voltage generator 150 ′ shown in FIG. 8 corresponds to the exemplary embodiment of the reference voltage generator 150 shown in FIG. 1 , but includes more than one of the corresponding CDS circuit structures, e.g., 152 , 154 .
  • Embodiments of the invention may employ a plurality of such corresponding CDS circuit structures, e.g., 152 , 154 , in an attempt to reduce an effect of input capacitance on the amplifier A 3 because the amplifier A 3 may be connected to, e.g., many comparators A 1 .
  • corresponding CDS circuit structures e.g., 152 , 154
  • embodiments of the invention may employ more than two corresponding CDS circuit structures.
  • a number of corresponding CDS circuit structures employed may correspond to a number of devices, e.g., comparators A 1 , of the corresponding CDS array 130 being driven by the respective reference voltage generator 150 .
  • FIG. 9 illustrates a block diagram of a second exemplary embodiment of a CMOS image sensor employing one or more aspects of the invention
  • FIG. 10 illustrates a schematic diagram of an exemplary embodiment of a pixel noise replica unit according to one or more aspects of the invention. Only aspects of the exemplary embodiment that are different to the exemplary embodiments described above with relation to FIGS. 5-8 will be described below.
  • a pixel noise replication unit 160 is employed instead of the OB pixel array 122 of the CMOS image sensor 105 .
  • the pixel noise replication unit 160 may copy pixel noise, e.g., power supply noise, to an output signal PNR_O to be supplied to the reference voltage generator 150 .
  • the exemplary pixel noise replication unit 160 may include devices, e.g., resistors and switches, for scaling a voltage level of the pixel noise, e.g. power supply noise.
  • the power supply voltage VDD_P and the ground power supply voltage VSS_P are supplied by the same voltage sources that are supplying, e.g., the APS array 120 .

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KR20070060437A (ko) 2007-06-13
CN1980335B (zh) 2015-05-27
CN1980335A (zh) 2007-06-13
US8072512B2 (en) 2011-12-06
KR100746197B1 (ko) 2007-08-06
TWI333369B (en) 2010-11-11
TW200723856A (en) 2007-06-16
US20100271247A1 (en) 2010-10-28
JP5105832B2 (ja) 2012-12-26

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