US20060097371A1 - Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads - Google Patents

Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads Download PDF

Info

Publication number
US20060097371A1
US20060097371A1 US11/194,691 US19469105A US2006097371A1 US 20060097371 A1 US20060097371 A1 US 20060097371A1 US 19469105 A US19469105 A US 19469105A US 2006097371 A1 US2006097371 A1 US 2006097371A1
Authority
US
United States
Prior art keywords
heat sink
semiconductor element
die pads
resin
leadframe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/194,691
Other languages
English (en)
Inventor
Tomoki Kawasaki
Yuichiro Yamada
Toshiyuki Fukuda
Shuichi Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUKUDA, TOSHIYUKI, KAWASAKI, TOMOKI, OGATA, SHUICHI, YAMADA, YUICHIRO
Publication of US20060097371A1 publication Critical patent/US20060097371A1/en
Priority to US12/208,804 priority Critical patent/US7952177B2/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a leadframe for use in a semiconductor device with built-in heat sink, and to a resin-sealed semiconductor device that uses the leadframe.
  • the mounting temperature when mounting a resin-sealed semiconductor device with built-in heat sink to a printed circuit board using lead-free solder is higher than for normal lead solder. This increases the temperature within the semiconductor device, which in turn raises the vapor pressure of absorbed moisture and promotes exfoliation of the semiconductor element from the heat sink, giving rise to the danger of internal bulging and cracking.
  • the present invention aims to provide a resin-sealed semiconductor device in which internal bulging and cracking is prevented even when mounted on a printed circuit board using lead-free solder, and a leadframe for use in the semiconductor device.
  • the present invention is a resin-sealed semiconductor device having a semiconductor element mounted on a heat sink.
  • the semiconductor device includes: a plurality of outer leads for external electrical connection extending at right angles to sides of a rectangle; a plurality of inner leads in series at one end with the outer leads; the heat sink adhered to an underside of an opposite end of the inner leads; a plurality of substantially square openings provided in the heat sink so as to lie partially outside a mounting area for the semiconductor element and with sides thereof positioned at an angle to a direction in which the outer leads extend; the semiconductor element adhered by adhesive to an upper surface of the heat sink in an area sandwiched by the openings; a plurality of metallic wires electrically connecting the inner leads with corresponding electrode pads of the semiconductor element; and a sealing resin that seals the inner leads, the semiconductor element and the metallic wires, with the outer leads left exposed.
  • sealing resin runs into the gap via the openings. Exfoliation of the semiconductor element is thus prevented even in the case of lead-free solder being used to mount the semiconductor device to a printed circuit board, as is bulging or cracking of the sealing resin.
  • the sides of the openings may be positioned at an approximately 45° angle, and the semiconductor element may be adhered to the heat sink via a plurality of die pads.
  • the formation of a gap is prevented because of the semiconductor element being securely adhered via a plurality of die pads.
  • the resin-sealed semiconductor device may further include a loop-shaped body encircled by the ends of the inner leads and surrounding the mounting area, the loop-shaped body being adhered to the upper surface of the heat sink via an underside thereof and having an inward protrusion positioned centrally on each side thereof.
  • the present invention is also a leadframe for use in a resin-sealed semiconductor device having a semiconductor element mounted on a heat sink.
  • the leadframe includes: a plurality of outer leads for external electrical connection extending at right angles to sides of a rectangle; a plurality of inner leads in series at one end with the outer leads and electrically connected to electrode pads of the semiconductor element via connecting members; the heat sink adhered to an underside of an opposite end of the inner leads; a plurality of substantially square die pads adhered to the heat sink in a mounting area for the semiconductor element so that sides thereof are positioned at an angle to a direction in which the outer leads extend; and a plurality of openings provided in the heat sink so as to form a checkered pattern with the die pads.
  • the semiconductor element can be securely adhered to the die pads of the leadframe with a small amount of adhesive. Moreover, the formation of a gap between the semiconductor element and the heat sink when manufacturing a resin-sealed semiconductor device that uses the leadframe is prevented because of sufficient sealing resin running between the semiconductor element and the heat sink via the openings. Thus, even in the case of lead-free solder (i.e. requires higher temperature than for normal lead solder) being used to mount the resin-sealed semiconductor device, bulging and cracking of the sealing resin due to the semiconductor element exfoliating can be prevented.
  • lead-free solder i.e. requires higher temperature than for normal lead solder
  • the sides of the die pads may be positioned at an approximately 45° angle
  • the openings may have rounded vertices
  • each opening positioned circumferentially may lie partially outside the mounting area.
  • sealing resin runs between the semiconductor element and the heat sink via openings positioned partially on the outside of the mounting area for the semiconductor element, enabling the formation of a gap to be securely prevented. Moreover, rounding the vertices of the openings allows the concentration of local stress to be alleviated.
  • the present invention is also a method of manufacturing a leadframe for use in a resin-sealed semiconductor device having a semiconductor element mounted on a heat sink.
  • the method includes the steps of: etching or stamping a piece of sheet metal to manufacture a metallic member that includes outer leads for external electrical connection extending at right angles to sides of a rectangle, inner leads in series at one end with the outer leads, substantially square die pads positioned with sides thereof at an angle to a direction in which the outer leads extend, a coupling ring coupling together the die pads, a dambar coupling the inner leads to the outer leads in side directions of the rectangle, and hanging leads holding the die pads from vertices of the dambar; adhering an upper surface of the heat sink to an underside of an opposite end of the inner leads and an underside of the die pads; and providing a plurality of openings in the heat sink to form a checkered pattern with the die pads and at the same time sectioning the coupling ring and the hanging leads.
  • the die pads can be separated at the same time as the openings are formed, which avoids complicating the processes and allows for an improved leadframe.
  • FIG. 1 is a plan view of an embodiment 1 of a leadframe pertaining to the present invention
  • FIG. 2 is a bottom view of FIG. 1 ;
  • FIG. 3 is a cross-sectional view cutting FIG. 1 at S-S′ of a resin-sealed semiconductor device that uses the leadframe of embodiment 1;
  • FIGS. 4A-4F are cross-sectional views of processes for manufacturing the resin-sealed semiconductor device of embodiment 1;
  • FIG. 5 is a plan view of an embodiment 2 of a leadframe with die pads pertaining to the present invention.
  • FIG. 6 is a bottom view of FIG. 5 ;
  • FIG. 7 is a plan view of the leadframe shown in FIG. 5 prior to openings being formed
  • FIG. 8 is a bottom view of FIG. 7 ;
  • FIG. 9 is a cross-sectional view cutting FIG. 5 at S-S′ of a resin-sealed semiconductor device that uses the leadframe with die pads of embodiment 2;
  • FIGS. 10A-10F are cross-sectional views of processes for manufacturing the resin-sealed semiconductor device of embodiment 2;
  • FIG. 11 is a plan view of an embodiment 3 of a leadframe with loop-shaped body pertaining to the present invention.
  • FIG. 12 is a bottom view of FIG. 11 ;
  • FIG. 13 is a cross-sectional view cutting FIG. 11 at S-S′ of a resin-sealed semiconductor device that uses the leadframe with loop-shaped body of embodiment 3;
  • FIGS. 14A-14F are cross-sectional views of processes for manufacturing the resin-sealed semiconductor device of embodiment 3;
  • FIG. 15 is a cross-sectional view schematically showing the flow of sealing resin in embodiment 2;
  • FIG. 16 is a cross-sectional view schematically showing the flow of sealing resin in embodiment 1;
  • FIG. 17 is a plan view of a conventional leadframe used in a comparative example for verifying the occurrence of cracking etc. in the resin-sealed semiconductor device of embodiment 2;
  • FIG. 18 is a bottom view of FIG. 17 ;
  • FIG. 19 is a cross-sectional view of a resin-sealed semiconductor device that uses the leadframe shown in FIG. 17 .
  • FIG. 1 is a plan view of an embodiment 1 of a leadframe pertaining to the present invention, while FIG. 2 shows a bottom view of the same.
  • a leadframe 101 includes a rectangular frame 102 , a plurality of outer leads 103 extending at right angles to the four sides of frame 102 , a plurality of inner leads 104 that are in series at one end with the outer leads and extend toward the inside of frame 102 , and a heat sink 105 adhered to the underside of the opposite ends of inner leads 104 .
  • a plurality of substantially square openings 106 with rounded vertices are formed at an approximately 45° angle to the direction in which the outer leads extend. The openings are positioned partially outside a mounting area 107 for the semiconductor element marked by the chain line.
  • the border area between outer leads 103 and inner leads 104 is coupled in the four side directions of frame 102 by a dambar 108 .
  • An area 109 marked by the chain line on the inside of dambar 108 indicates the area to be covered by sealing resin in a resin-sealed semiconductor device that uses leadframe 101 .
  • the components of leadframe 101 apart from heat sink 105 are obtained by processing sheet metal made from copper alloy having a thickness of 0.15 mm and a hardness of 150 to 185 Hv, for example, using an etching or stamping technique.
  • Heat sink 105 is a copper alloy sheet having a thickness of 0.13 mm, for example. Heat sink 105 is thermally adhered to the underside of the ends of inner leads 104 with adhesive.
  • FIG. 3 is a cross-sectional view cutting FIG. 1 at S-S′ of a resin-sealed semiconductor device that uses leadframe 101 .
  • a semiconductor element 301 is adhered to heat sink 105 in mounting area 107 thereof using a die bond 302 such as silver paste, for example. Electrode pads of semiconductor element 301 are connected to corresponding inner leads 104 by wires (e.g. metallic wires).
  • the semiconductor device is resin sealed using a sealing resin 304 made from an epoxy resin, for example, with outer leads 103 left exposed.
  • FIGS. 4A to 4 F are cross-sectional views cutting FIG. 1 at S-S′.
  • FIGS. 4A and 4B show the manufacturing processes for leadframe 101 .
  • FIG. 4A shows a process of using adhesive to adhere a metallic member (i.e. processed copper alloy sheet metal) that includes outer leads 103 and inner leads 104 etc. coupled together by frame 102 to the upper surface of heat sink 105 via the underside of the ends of inner leads 104 .
  • a metallic member i.e. processed copper alloy sheet metal
  • outer leads 103 and inner leads 104 etc. coupled together by frame 102 to the upper surface of heat sink 105 via the underside of the ends of inner leads 104 .
  • FIG. 4B shows a process of forming openings 106 by punch processing heat sink 105 adhered to the metallic member. This completes the manufacture of leadframe 101 .
  • FIG. 4C shows a process of adhering semiconductor element 301 to leadframe 101 .
  • Die bond 302 is applied at points 110 on heat sink 105 marked by the dotted lines in FIG. 1 , and semiconductor element 301 is placed over these points and adhered thereto.
  • FIG. 4D shows a wire bonding process.
  • the electrode pads of semiconductor element 301 are connected to the tip of corresponding inners lead 104 by wires 303 .
  • FIG. 4E shows a resin sealing process.
  • a mold is disposed so as to cover leadframe 101 and wires 303 while leaving outer leads 103 exposed, and a sealing resin made from epoxy resin is injected at a mold temperature of 180° C.
  • the injection time is set to 8 seconds, for example.
  • the mold is removed after cooling.
  • FIG. 4F shows a process of bending outer leads 103 .
  • Frame 102 of leadframe 101 is separated using a tie bar cut and outer leads 103 are bent to complete the manufacture of the resin-sealed semiconductor device.
  • sealing resin injected via openings 106 which extend beyond mounting area 107 runs into the space between semiconductor element 301 and heat sink 105 , enhancing the adhesion of semiconductor element 301 with heat sink 105 .
  • the formation of a gap between semiconductor element 301 and heat sink 105 can thus be prevented.
  • FIG. 5 is a plan view of a leadframe with die pads
  • FIG. 6 is a bottom view of the same.
  • a plurality of die pads 502 is provided in mounting area 107 of a leadframe 501 so as to form an oblique checkered-pattern with openings 106 .
  • Die pads 502 are substantially square in shape, and as with openings 106 the sides of the die pads are angled at approximately 45 degrees to the direction in which outer leads 103 extend. Those openings 106 positioned circumferentially lie partially outside mounting area 107 .
  • openings 106 and die pads 502 surrounded by openings 106 form a checkered pattern and are angled at approximately 45 degrees to the direction in which outer leads 103 extend, the area of die pads 502 occupying mounting area 107 is ideal for applying the adhesive to adhere semiconductor element 301 .
  • Hanging leads 503 protrude toward a central point from the vertices of dambar 108 of leadframe 501 .
  • Heat sink 105 is adhered to the underside of both die pads 502 and the ends of inner leads 104 using adhesive.
  • FIG. 7 is a plan view of the leadframe with die pads shown in FIGS. 5 and 6 prior to openings 106 being formed, while FIG. 8 is a bottom view of the same.
  • Die pads 502 are coupled together by a coupling ring 701 , which is connected to dambar 108 via hanging leads 503 .
  • the underside of die pads 502 , coupling ring 701 and hanging leads 503 are adhered to the upper surface of heat sink 105 using adhesive.
  • leadframe 501 excluding heat sink 105 is manufactured, similar to embodiment 1, by one-piece molding copper alloy sheet metal using a stamping technique, for example.
  • FIG. 9 is a cross-sectional view cutting FIG. 5 at S-S′ of a resin-sealed semiconductor device that uses the leadframe with die pads.
  • die pads 502 are interposed between and adhered with adhesive to both semiconductor element 301 and the upper surface of heat sink 105 .
  • the formation of a gap between semiconductor element 301 and heat sink 105 can thus be minimized since this expands the space between semiconductor element 301 and heat sink 105 and facilitates the flow of sealing resin 304 via openings 106 .
  • FIGS. 10A to 10 F are cross-sectional views cutting FIG. 5 at S-S′, and that extraneous items have been omitted to simplify the diagrams. Note also that description of the processes shown in FIGS. 10D and 10F have been omitted given the substantial similarities with processes shown in FIG. 4 of embodiment 1.
  • FIG. 10A shows a process of using adhesive to adhere a metallic member (i.e. processed copper alloy sheet metal) consisting of outer leads 103 , inner leads 104 and die pads 502 etc. coupled together by frame 102 to the upper surface of heat sink 105 via the underside of both die pads 502 and the ends of inner leads 104 .
  • a metallic member i.e. processed copper alloy sheet metal
  • FIG. 10B shows a process of forming openings 106 by punch processing heat sink 105 adhered to the metallic member and at the same time removing coupling ring 701 and part of hanging leads 503 to separate die pads 502 .
  • Openings 106 disposed so as to form a checkered pattern with die pads 502 , are substantially square in shape and positioned at an approximately 45° angle to the sides of the rectangular form of leadframe 501 . Also, those openings 106 positioned circumferentially lie partially outside mounting area 107 .
  • FIG. 10C shows a process of adhering semiconductor element 301 to leadframe 501 .
  • Die bond 302 is applied to the upper surface of die pads 502 , and semiconductor element 301 is placed over the die pads and adhered thereto.
  • FIG. 10D to 10 F are similar to embodiment 1.
  • sealing resin shown in FIG. 10E is made easier than in embodiment 1 as a result of the space between semiconductor element 301 and heat sink 105 .
  • FIG. 11 is a plan view of a leadframe with loop-shaped body
  • FIG. 12 is a bottom view of the same.
  • Leadframe 1100 consists of the addition of a loop-shaped body 1101 that surrounds mounting area 107 for semiconductor element 301 to leadframe 101 of embodiment 1.
  • Cap-shaped protrusions 1103 that protrude toward semiconductor element 301 are formed centrally on sides of loop-shaped body 1101 .
  • Hanging leads 1102 that connect loop-shaped body 1101 to dambar 108 are formed at the corners of loop-shaped body 1101 .
  • leadframe 1100 is integrally formed from sheet metal.
  • FIG. 13 is a cross-sectional view of a resin-sealed semiconductor device that uses leadframe 1100 . This cross sectional view cuts FIG. 11 at S-S′.
  • Loop-shaped body 1101 is disposed on the inside of inner leads 104 so as to surround semiconductor element 301 .
  • a cross-section of protrusions 1103 is shown in FIG. 13 .
  • FIGS. 14A to 14 F are cross-sectional views illustrating processes for manufacturing leadframe 1100 and a resin-sealed semiconductor device that uses leadframe 1100 . Note that these cross-sectional views cut FIG. 11 at S-S′ with extraneous items having been omitted.
  • FIG. 14A shows a process of adhering heat sink 105 to the metallic member.
  • Adhesive is applied to the underside of both loop-shaped body 1101 and the ends of inner leads 104 , and the upper surface of heat sink 105 is adhered thereto by the adhesive.
  • loop-shaped body 1101 connected to hanging leads 1102 on the inside of inner leads 104 in this process prevents the adhesion of heat sink 105 in a warped state, with any heat-related deformation being absorbed by protrusions 1103 provided centrally on the sides of loop-shaped body 1101 .
  • loop-shaped body 1101 in the resin sealing process in FIG. 14E prevents sealing resin 304 from impacting on semiconductor element 301 when injected.
  • FIG. 14F The bending process in FIG. 14F is substantially similar to embodiment 1.
  • An exemplary leadframe incorporates the die pads described in embodiment 2 with the loop-shaped body described in embodiment 3.
  • FIGS. 15 and 16 The flow of the sealing resin in the resin sealing process of embodiments 1 and 2 is described next using FIGS. 15 and 16 .
  • FIG. 15 shows semiconductor element 301 adhered to heat sink 105 via die pads 502
  • FIG. 16 shows semiconductor element 301 adhered directly to heat sink 105
  • Semiconductor element 301 is adhered using die bond 302 in both cases, although when adhered to heat sink 105 via die pads 502 as in embodiment 2, a space equivalent to the thickness of die pads 502 is opened up between semiconductor element 301 and heat sink 105 .
  • arrow A 501 this enables the sealing resin to flow sufficiently into the space between semiconductor element 301 and heat sink 105 via openings 106 .
  • the flow of sealing resin between semiconductor element 301 and heat sink 105 via openings 106 is as shown by arrow 1601 , preventing the formation of a gap.
  • FIG. 17 A plan view of a conventional leadframe is shown in FIG. 17 , while a bottom view of the same is shown in FIG. 18 .
  • a single opening 1701 is provided in heat sink 105 below mounting area 107 .
  • FIG. 19 is a cross-sectional view cutting FIG. 17 at S-S′ of a conventional resin-sealed semiconductor device that uses this leadframe.
  • the present and conventional devices were firstly baked for 12 hours at 125° C. and dried, before being placed in an atmosphere having a temperature of 30° C. and a relative humidity of 70% for 72 hours to absorb moisture. Then, after having been subjected to a temperature of 265° C. for five minutes, the devices were again placed in an atmosphere having a temperature of 30° C. and a relative humidity of 70% for 96 hours. After again being subjected to a temperature of 265° C. for five minutes, the devices were cooled to room temperature and then supersonic waves were used to investigate for exfoliation and cracking.
  • Resin-sealed semiconductor devices using leadframes pertaining to the present invention are for use as environmentally friendly semiconductor devices in the field of semiconductor manufacturing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
US11/194,691 2004-11-10 2005-08-02 Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads Abandoned US20060097371A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/208,804 US7952177B2 (en) 2004-11-10 2008-09-11 Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004326513A JP4307362B2 (ja) 2004-11-10 2004-11-10 半導体装置、リードフレーム及びリードフレームの製造方法
JPJP2004-326513 2004-11-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/208,804 Division US7952177B2 (en) 2004-11-10 2008-09-11 Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads

Publications (1)

Publication Number Publication Date
US20060097371A1 true US20060097371A1 (en) 2006-05-11

Family

ID=36315488

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/194,691 Abandoned US20060097371A1 (en) 2004-11-10 2005-08-02 Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads
US12/208,804 Active US7952177B2 (en) 2004-11-10 2008-09-11 Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/208,804 Active US7952177B2 (en) 2004-11-10 2008-09-11 Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads

Country Status (4)

Country Link
US (2) US20060097371A1 (ja)
JP (1) JP4307362B2 (ja)
CN (2) CN1790687A (ja)
TW (1) TW200618232A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070111395A1 (en) * 2005-09-29 2007-05-17 Siliconware Precision Industries Co., Ltd. Lead frame structure and semiconductor package integrated with the lead frame structure
US20180182644A1 (en) * 2016-12-27 2018-06-28 Renesas Electronics Corporation Method for manufacturing a semiconductor device
US10888496B2 (en) 2015-09-17 2021-01-12 Corvida Medical, Inc. Medicament vial assembly
US10894317B2 (en) 2015-10-13 2021-01-19 Corvida Medical, Inc. Automated compounding equipment for closed fluid transfer system
US10966905B2 (en) 2008-05-14 2021-04-06 Corvida Medical, Inc. Systems and methods for safe medicament transport
US11171077B2 (en) * 2019-07-10 2021-11-09 Nxp Usa, Inc. Semiconductor device with lead frame that accommodates various die sizes

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5096812B2 (ja) * 2007-06-28 2012-12-12 株式会社三井ハイテック 複合リードフレームを用いた半導体装置
JP5149854B2 (ja) 2009-03-31 2013-02-20 ルネサスエレクトロニクス株式会社 半導体装置
US9054077B2 (en) * 2010-03-10 2015-06-09 Altera Corporation Package having spaced apart heat sink
US9029991B2 (en) * 2010-11-16 2015-05-12 Conexant Systems, Inc. Semiconductor packages with reduced solder voiding
US9754861B2 (en) * 2014-10-10 2017-09-05 Stmicroelectronics Pte Ltd Patterned lead frame
CN108493169A (zh) * 2018-05-31 2018-09-04 江苏长电科技股份有限公司 一种无基岛框架封装结构及其工艺方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378656A (en) * 1992-03-27 1995-01-03 Hitachi, Ltd. Leadframe, semiconductor integrated circuit device using the same, and method of and process for fabricating the same
US5635756A (en) * 1990-04-06 1997-06-03 Hitachi, Ltd. Semiconductor device, lead frame therefor and memory card to provide a thin structure
US6396142B1 (en) * 1998-08-07 2002-05-28 Hitachi, Ltd. Semiconductor device
US20020074627A1 (en) * 1993-09-03 2002-06-20 Combs Edward G. Molded plastic package with heat sink and enhanced electrical performance
US7211471B1 (en) * 2002-09-09 2007-05-01 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
JPH0878605A (ja) 1994-09-01 1996-03-22 Hitachi Ltd リードフレームおよびそれを用いた半導体集積回路装置
CN1080793C (zh) 1997-03-14 2002-03-13 何振才 外环状道路立体交通系统及其建造方法
JPH11354706A (ja) 1998-06-09 1999-12-24 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP2000174193A (ja) 1998-12-07 2000-06-23 Hitachi Cable Ltd 放熱板付きリードフレーム
US6258630B1 (en) * 1999-02-04 2001-07-10 Nec Corporation Resin-sealed semiconductor device having island for mounting semiconductor element coupled to heat spreader
JP3454192B2 (ja) 1999-07-02 2003-10-06 松下電器産業株式会社 リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5635756A (en) * 1990-04-06 1997-06-03 Hitachi, Ltd. Semiconductor device, lead frame therefor and memory card to provide a thin structure
US5378656A (en) * 1992-03-27 1995-01-03 Hitachi, Ltd. Leadframe, semiconductor integrated circuit device using the same, and method of and process for fabricating the same
US20020074627A1 (en) * 1993-09-03 2002-06-20 Combs Edward G. Molded plastic package with heat sink and enhanced electrical performance
US6552417B2 (en) * 1993-09-03 2003-04-22 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US6396142B1 (en) * 1998-08-07 2002-05-28 Hitachi, Ltd. Semiconductor device
US7211471B1 (en) * 2002-09-09 2007-05-01 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070111395A1 (en) * 2005-09-29 2007-05-17 Siliconware Precision Industries Co., Ltd. Lead frame structure and semiconductor package integrated with the lead frame structure
US7459770B2 (en) * 2005-09-29 2008-12-02 Siliconware Precision Industries Co., Ltd. Lead frame structure having blocking surfaces and semiconductor package integrated with the lead frame structure
US10966905B2 (en) 2008-05-14 2021-04-06 Corvida Medical, Inc. Systems and methods for safe medicament transport
US10888496B2 (en) 2015-09-17 2021-01-12 Corvida Medical, Inc. Medicament vial assembly
US10894317B2 (en) 2015-10-13 2021-01-19 Corvida Medical, Inc. Automated compounding equipment for closed fluid transfer system
US20180182644A1 (en) * 2016-12-27 2018-06-28 Renesas Electronics Corporation Method for manufacturing a semiconductor device
US10128130B2 (en) * 2016-12-27 2018-11-13 Renesas Electronics Corporation Method for manufacturing a semiconductor device
US11171077B2 (en) * 2019-07-10 2021-11-09 Nxp Usa, Inc. Semiconductor device with lead frame that accommodates various die sizes

Also Published As

Publication number Publication date
JP2006140208A (ja) 2006-06-01
US20090008754A1 (en) 2009-01-08
JP4307362B2 (ja) 2009-08-05
US7952177B2 (en) 2011-05-31
CN101383330A (zh) 2009-03-11
TW200618232A (en) 2006-06-01
CN101383330B (zh) 2010-06-16
CN1790687A (zh) 2006-06-21

Similar Documents

Publication Publication Date Title
US7952177B2 (en) Resin-sealed semiconductor device, leadframe with die pads, and manufacturing method for leadframe with die pads
US8389336B2 (en) Semiconductor device package and method of assembly thereof
US7582958B2 (en) Semiconductor package
US7489021B2 (en) Lead frame with included passive devices
US20160056097A1 (en) Semiconductor device with inspectable solder joints
US5053852A (en) Molded hybrid IC package and lead frame therefore
JP2009534812A (ja) 電源リング及びアース・リングを有するｑｆｎパッケージの製造方法
US9190352B2 (en) Multi-die sensor device
KR960012647B1 (ko) 반도체장치 및 그 제조방법
US10978378B2 (en) Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier
US20180122728A1 (en) Semiconductor packages and methods for forming same
JP6668393B2 (ja) ヒートスラグとリベットのないダイ取付領域とを有する半導体パッケージ
US11037866B2 (en) Semiconductor device and method of manufacturing the same
JP3734225B1 (ja) 面実装タイプ樹脂製中空パッケージ及びこれを用いた半導体装置
US9099363B1 (en) Substrate with corner cut-outs and semiconductor device assembled therewith
WO2008083146A1 (en) Stress-resistant leadframe and method
US6312976B1 (en) Method for manufacturing leadless semiconductor chip package
JP4695672B2 (ja) 半導体装置
JP2003007933A (ja) 樹脂封止型半導体装置
CN106158810B (zh) 用于ic封装的具有偏转的连接杆的引线框架
JP2004207415A (ja) 半導体モジュール、電子機器および半導体モジュールの製造方法
JPH0758273A (ja) リードフレーム及びそれを用いた半導体装置
KR100704311B1 (ko) 내부리드 노출형 반도체 칩 패키지와 그 제조 방법
KR100198312B1 (ko) 리드프레임의 구조 및 이를 이용한 반도체 패키지
JP2002252319A (ja) 半導体装置及びその製造方法、並びにリードフレーム

Legal Events

Date Code Title Description
AS Assignment

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWASAKI, TOMOKI;YAMADA, YUICHIRO;FUKUDA, TOSHIYUKI;AND OTHERS;REEL/FRAME:016836/0735

Effective date: 20050628

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: PANASONIC CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;REEL/FRAME:022434/0348

Effective date: 20081001