US20050252828A1 - Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape - Google Patents

Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape Download PDF

Info

Publication number
US20050252828A1
US20050252828A1 US11/073,766 US7376605A US2005252828A1 US 20050252828 A1 US20050252828 A1 US 20050252828A1 US 7376605 A US7376605 A US 7376605A US 2005252828 A1 US2005252828 A1 US 2005252828A1
Authority
US
United States
Prior art keywords
holes
carrier tape
line
region
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/073,766
Other languages
English (en)
Inventor
Yoshikazu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Assigned to OKI ELECTRIC INDUSTRY CO., LTD. reassignment OKI ELECTRIC INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAKAHASHI, YOSHIKAZU
Publication of US20050252828A1 publication Critical patent/US20050252828A1/en
Assigned to OKI SEMICONDUCTOR CO., LTD. reassignment OKI SEMICONDUCTOR CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI ELECTRIC INDUSTRY CO., LTD.
Assigned to Lapis Semiconductor Co., Ltd. reassignment Lapis Semiconductor Co., Ltd. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI SEMICONDUCTOR CO., LTD
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/0084—Containers and magazines for components, e.g. tube-like magazines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path

Definitions

  • the present invention relates to a carrier tape which is used when a plurality of relatively small electronic devices such as semiconductor devices are consecutively manufactured, to a method of manufacturing the electronic device with the carrier tape, and to an electronic device package with the carrier tape.
  • a carrier tape has a plurality of sprocket holes which are formed along both of long edges of the carrier tape.
  • the sprocket holes are arranged in a line at standardized pitches along each of the long edges.
  • the carrier tape is reeled by a sprocket.
  • Each of the standardized pitches of the sprocket holes is equal to the pitch between teeth of the sprocket.
  • device holes are formed between the sprocket holes arranged along both of the long edges in the carrier tape by using a mold tool.
  • a carrier tape configured for use in an electronic device assembly process.
  • the carrier tape includes a base film having a long edge and a plurality of first holes which extend through the base film.
  • the first holes are aligned in a line that is adjacent to and parallel to the long edge of the base film and are spaced at a regular pitch.
  • the carrier tape further includes a plurality of second holes which extend through the base film and which are aligned in the line. The second holes are spaced at the regular pitch and are respectively located between adjacent pairs of the first holes.
  • a method of manufacturing an electronic device in an assembly process includes processes described below.
  • the tape carrier is provided which has a base film having a long edge and a plurality of first holes which extend through the base film.
  • the first holes are aligned in a line that is adjacent to and parallel to the long edge of the base film and are spaced at a regular pitch.
  • the carrier tape further includes a plurality of second holes which extend through the base film and which are aligned in the line.
  • the second holes are spaced at the regular pitch and are respectively located between adjacent pairs of the first holes.
  • a first electronic component is aligned at a first region of the carrier tape by using at least one of the first holes and is mounted at the first region of the carrier tape.
  • the carrier tape is transferred by action of a sprocket having teeth extending into the first holes or the second holes of the carrier tape.
  • a second electronic component is aligned at a second region of the carrier tape by using at least one of the second holes and is mounted at the second region of the carrier tape.
  • a tape carrier package which includes a carrier tape having a base film having a long edge and a plurality of first holes which extend through the base film.
  • the first holes are aligned in a line that is adjacent to and parallel to the long edge of the base film and are spaced at a regular pitch.
  • the carrier tape further includes a plurality of second holes which extend through the base film and which are aligned in the line.
  • the second holes are spaced at the regular pitch and are respectively located between adjacent pairs of the first holes.
  • the tape carrier package further includes a first electronic component located in a first region of the carrier tape and aligned with with one of the first holes.
  • the first electronic component is covered with a first resin.
  • the tape carrier package still further includes a second electronic component located in a second region, which is different from the first region, of the carrier tape and aligned with one of the second holes.
  • the second electronic component is covered with a second resin.
  • FIG. 1 is a plain view for describing a tape carrier package which includes a semiconductor element according to a first preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view along a dashed line I-I′ of the tape carrier package of FIG. 1 .
  • FIG. 3 is a plain view for describing a tape carrier package which includes a semiconductor element according to a second preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional view along a dashed line II-II′ of the tape carrier package of FIG. 3 .
  • FIG. 5 is a plain view for describing a tape carrier package which includes a semiconductor element according to a thid preferred embodiment of the present invention.
  • FIG. 6 is a cross-sectional view along a dashed line III-III′ of the tape carrier package of FIG. 5 .
  • FIG. 7 and FIG. 8 are enlarged plain views for describing the long edge region of the carrier tape according to the first to third preferred embodiments of the present invention.
  • FIG. 1 is a plain view for describing a tape carrier package which includes a semiconductor element according to a first preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view along a dashed line I-I′ of the tape carrier package of FIG. 1 .
  • the carrier tape 1 is used in an assembly process of electronic devices.
  • a semiconductor device is referenced as a typical example of the electronic device and a semiconductor element is referenced as a typical example of the electronic component.
  • the tape carrier package is referred to as a “TCP”.
  • the carrier tape 1 includes a base film 2 with long edge regions 2 a.
  • the base film 2 is made of polyimide or polyester having a high heat-resisting property.
  • a plurality of first holes 3 extend through the base film 2 of the carrier tape 1 and aligned in a line that is adjacent to and parallel to the long edge region 2 a.
  • the first holes 3 are spaced at a regular pitch P.
  • the carrier tape 1 is reeled by a sprocket.
  • the sprocket has a plurality of teeth whose pitch is substantially equal to the regular pitch P of the first holes 3 .
  • the first holes 3 are used as sprocket holes in this embodiment.
  • the regular pitch P is standardized, for example, 4.75 mm in this embodiment.
  • a transferring movement of the carrier tape 1 is executed with the teeth of the sprocket extending into the first holes 3 and and with the sprocket rotating.
  • the direction of the transferring movement of the carrier tape 1 is hereinafter referred to as “a longitudinal direction”.
  • the sprocket is driven by an electrical drive unit in a semiconductor equipment not shown in the figures.
  • the electrical drive unit in this embodiment has a pulse motor which is capable of controlling a rotation angle of the sprocket depending on pulses applied to the pulse motor.
  • each of the first holes 3 is made substantially quadrangle and has a size B in the longitudinal direction as shown in FIG. 1 .
  • the configuration of the first hole 3 is not limited by the quadrangle. That is, the configuration of the first hole 3 may be circular, so some other shape so long as the first holes 3 are capable of executing the transferring movement of the carrier tape 1 when the teeth of the sprocket are placed into the first holes 3 .
  • a device hole 20 is formed in each of the semiconductor element locating regions 2 b.
  • a plurality of first outer leads 7 for input signals and a plurality of second outer leads 8 for output signals are formed on the carrier tape 1 around the device hole 20 .
  • a plurality of inner leads 11 are formed on the carrier tape 1 between the device hole 20 and the first and second outer leads 7 and 8 .
  • a portion of the inner leads 11 and the first and second outer leads 7 and 8 are fixed on the carrier tape 1 through an adhesive layer 14 and covered with a solder resist 12 .
  • a plurality of semiconductor elements 10 including first and second semiconductor elements 10 a and 10 b are respectively located in the device holes 20 of the carrier tape 1 .
  • the semiconductor element 10 has a plurality of electrodes 9 connected with the inner leads 11 .
  • Each of the semiconductor elements 10 is covered with a molding resin 13 .
  • a plurality of test pads 15 are connected with the second outer leads 8 and are used for an electrical test of the semiconductor unit 4 on the carrier tape 1 before the TCP is divided into each of the semiconductor units 4 .
  • Each of the semiconductor units 4 is separated from the carrier tape 1 by a plurality of cutting regions including first and second cutting regions 5 a and 5 b.
  • a plurality of second holes 17 extend through the base film 2 of the carrier tape 1 and aligned in the line where the first holes 3 are aligned. That is, the second holes 17 are adjacent to and parallel to the long edge region 2 a.
  • Each of the second holes 17 is located between adjacent pairs of the first holes 3 . That is, the first holes 3 and the second holes 17 are alternatively located.
  • each of the second holes 17 is located in the middle between the adjacent pairs of the first holes 3 . In this case, for example, a pitch between the first hole 3 and the second hole 17 which are adjacent is 2.375 mm.
  • the second holes 17 are spaced at the regular pitch P which is substantially equal to the pitch of the teeth of the sprocket as well as the first holes 3 .
  • each of the second holes 17 is made substantially quadrangle like the first holes 3 and has a size B in the longitudinal direction.
  • a detector has a light emission element 18 a disposed over the long edge region 2 a of the carrier tape 1 and a light-sensitive element 18 b disposed under the long edge region 2 a of the carrier tape 1 . That is, the detector such as an optical sensor is set so that the carrier tape 1 can be positioned between the light emission element 18 a and the light-sensitive element 18 b. The detector detects an anterior edge of the first hole 3 and the second hole 17 when the light-sensitive element 18 b receives light from the light emission element 18 a through the first hole 3 or the second hole 17 .
  • a ratchet type positioning plotter may be used instead of the detector. The first holes 3 and the second holes 17 can be detected by changing a ratchet angle in this plotter.
  • a center line of the size B of the first hole 3 or the second hole 17 which is perpendicular to the longitudinal direction is conformed to a center line of a size C of one of the cutting regions (hereinafter referred to as “a cutting region size C”) which is perpendicular to the longitudinal direction (which is like the dashed line I-I′).
  • the first hole 3 or the second hole 17 in the above-mentioned case may be called a criterial hole 19 .
  • the first cutting region 5 a in which the first semiconductor element 10 a is mounted is set to be positioned on the carrier tape 1 by taking one of the second holes 17 as a first criterial hole 19 a.
  • the second cutting region 5 b in which the second semiconductor unit 10 b is located is set to be positioned on the carrier tape 1 by taking one of the first holes 3 as a second criterial hole 19 b.
  • the criterial holes 19 which are used for setting the cutting regions 5 are located at predetermined pitches L (hereinafter referred to as “criterial hole pitches L”) so that adjacent semiconductor units 4 can be kept away from each other and so that each of intervals between the adjacent semiconductor units 4 can be shortened as much as possible.
  • the criterial hole pitch L is larger, for example, by 0.05 mm-0.2 mm than the total device size T.
  • a method of manufacturing a plurality of semiconductor devices including first and second semiconductor elements 10 a and 10 b by using the sprocket and the carrier tape 1 in the assembly process is described below.
  • the carrier tape 1 with the long edge regions 2 a is provided.
  • the carrier tape 1 has a plurality of the first holes 3 and a plurality of the second holes 17 which extend through the base film 2 and are aligned in the long edge regions 2 a of the base film 2 .
  • a plurality of the device holes 20 are positioned in the semiconductor element locating region 2 b, based on the criterial holes 19 which are selected among the first holes 3 and the second holes 17 at the criterial hole pitches L.
  • the inner leads 11 and the first and second outer leads 7 and 8 are located around the device holes 20 by etching a beaten-copper layer formed on the semiconductor element locating region in photo lithography and etching processes.
  • a plurality of the semiconductor elements 10 including the first and second semiconductor elements 10 a and 10 b are provided.
  • a positioning information about the first criterial hole 19 a (which is one of the second holes 17 ) is input into the semiconductor equipment.
  • the transferring movement of the carrier tape 1 is executed by the sprocket and the pulse motor while the detector 18 detects the anterior edges of the first hole 3 and the second hole 17 .
  • the electrical drive unit begin to reduce a speed of the rotation of the sprocket by a feedforward control of the friction brake.
  • the foregoing reduction in the rotational speed of the sprocket restrains the first hole 3 or the second hole 17 , into which the tooth of the sprocket is placed, from getting damaged by a quick stop.
  • the detector 18 detects the anterior edge of the first criterial hole 19 a
  • the transferring movement of the carrier tape 1 is interrupted by the friction brake.
  • the first semiconductor element 10 a is mounted in the first cutting region 5 a.
  • a center line of the first semiconductor element 10 a which is perpendicular to the longitudinal direction may be conformed to the center line of the first cutting region 5 a which is perpendicular to the longitudinal direction.
  • the electrodes 9 are connected with the inner leads 11 , for example, by an eutectic thermo compression method depending on temperature, pressure and time of loading of a bonding tool by which the inner leads 11 are connected with the electrodes 9 or by a welding method using ultrasonic waves.
  • the transferring movement of the carrier tape 1 is executed again.
  • the electrical drive unit begins to reduce the speed of the rotation of the sprocket by the feedforward control of the friction brake, in order to restrain the first hole 3 or the second hole 17 from getting damaged by the quick stop.
  • the second criterial hole 19 b is the one of the first holes 3 which is located away from the first criteria hole 19 a at the criteria hole pitch L.
  • the transferring movement of the carrier tape 1 is interrupted by the friction brake.
  • the second semiconductor element 10 b is located in the second cutting region 5 b.
  • a center line of the second semiconductor element 10 b which is perpendicular to the longitudinal direction may be conformed to a center line of the second cutting region 5 a which is perpendicular to the longitudinal direction.
  • the electrodes 9 are connected with the inner leads 11 , for example, by an eutectic thermo compression method depending on temperature, pressure and time of loading of a bonding tool by which the inner leads 11 are connected with the electrodes 9 or by a welding method using ultrasonic waves.
  • remaining semiconductor elements 10 are sequentially located in remaining cutting regions 5 of the semiconductor element locating region 2 b of the carrier tape 1 as well as the first and second semiconductor elements 10 a and 10 b are located.
  • all of the semiconductor elements 10 and all of the cutting regions 5 are located in the semiconductor element locating region 2 b at the criterial hole pitches L.
  • an alignment hole 6 is located in each of the cutting regions 5 .
  • the carrier tape 1 may be divided into a plurality of semiconductor unit groups which respectively include some of a plurality of the semiconductor units 4 by being cut in rectangles. Also, after the semiconductor unit groups which are cut in rectangles are shipped to electronic makers as intermediate products, each of the semiconductor units 4 in the cutting regions 5 may be separated apart from the carrier tape 1 into individual products in the electronic makers.
  • the sprocket described in this embodiment is set in a place different from the place for the locating operation of the semiconductor elements 10 . Therefore, the sprocket does not discourage the detector 18 from detecting the anterior edge of the first hole 3 or the second hole 17 .
  • the sprocket described in this embodiment has teeth at the standardized pitches of the first holes 3 and the second holes 17 . Therefore, when the teeth of the sprocket are put into the first holes 3 , the teeth are not put into the second holes 17 . On the other hand, when the teeth of the sprocket are put into the second holes 17 , the teeth are not put into the first holes 3 .
  • the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, the cutting regions 5 are located on the carrier tape 1 at pitches defined by five adjacent first holes 3 .
  • Each of these pitches corresponds to a pitch defined by nine of adjacent first holes 3 and second holes 17 in the present invention. That is, in this example, the value of the criterial hole pitch L is set to 19 mm.
  • the cutting regions 5 can be located on the carrier tape 1 at pitches defined by eight of the adjacent first holes 3 and second holes 17 in the present invention. That is, in this example, the value of the criterial hole pitch L can be set to 16.625 mm. Therefore, when the same number of pieces of the semiconductor devices is manufactured in the related art and the present invention, the entire length of the carrier tape 1 in the present invention can be shortened by 12.5% of the entire length of the carrier tape in the related art. As a result, it can be realized that the cost of the carrier tape is reduced.
  • the configurations of the first hole 3 and the second hole 17 are concurrently represented by the quadrangles in the drawings.
  • the configuration of the second hole 17 may be rectanglar or circular as long as the size B of the second hole 17 is equal to the size B of the first hole 3 in the longitudinal direction.
  • the carrier tape which has a plurality of the first holes arranged on a line at the standardized pitches, includes a plurality of the second holes arranged on the same line as the first holes are at the standardized pitches. Moreover, each of the second holes is located between adjacent first holes of a plurality of the first holes. Therefore, a plurality of the cutting regions, in which the semiconductor elements are respectively mounted, can be set on the carrier tape at shorter pitches. As a result, the entire length of the carrier tape can be shortened, and thus the cost of the carrier tape is reduced. Also, the exchange frequency of the carrier tape can be decreased, and thus the productive efficiency of the electronic devices is improved. Also, in the present invention, a plurality of the second holes can be formed in the carrier tape which previously has a purality of the first holes spaced at the regular pitch without sophisticated changes of design. Therefore, the carrier tape which produces the above mentioned effects can be easily realized.
  • the second holes are formed so that they have configurations into which the teeth of the sprocket are placed, the exchange of the carrier tapes can be easily executed without distinguishing between the first holes and the second holes in the assembly process. As a result, the efficiency in the exchange of the carrier tape can be improved. Also, in first preferred embodiment of the present invention, since the second holes are formed on the same line as the first holes are, increasing of the width of the carrier tape can be restrained. Therefore, the carrier tape of the present invention can be applied to existing manufacturing equipment.
  • the first and second holes are formed in both of the long edge regions of the carrier tape, they may be formed only in one of the long edge regions of the carrier tape.
  • the first and second holes can be detected by an imaging sensor such as a CCD camera instead of the detector which detects the anterior edge of the first hole or the second hole.
  • an imaging sensor such as a CCD camera
  • the imaging sensor is used, a center point of the first hole or the second hole is detected. Therefore, it is not necessary that the size B of the second hole is equal to the size B of the first hole in the longitudinal direction. That is, the second holes can be easily formed.
  • FIG. 3 is a plain view for describing a tape carrier package which includes a semiconductor element according to a second preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional view along a dashed line II-II′ of the tape carrier package of FIG. 3 .
  • a plurality of semiconductor elements 10 are respectively located on the cutting regions 5 without forming the device holes in the carrier tape 1 . Then, each of the cutting regions 5 is separated from the carrier tape 1 as in the first preferred embodiment.
  • Each of these types of the semiconductor devices is called a Chip On Film (hereinafter referred to as “COF”) type semiconductor device.
  • COF Chip On Film
  • the other configurations of the semiconductor devices 21 according to the second preferred embodiment are the same as those according to the first preferred embodiment.
  • the semiconductor element 10 has a chip surface where a plurality of the electrodes 9 are formed.
  • the semiconductor elements 10 are located on the carrier tape 1 while the chip surfaces face the carrier tape 1 . After locating the semiconductor elements 10 on the carrier tape 1 , the molding resin 13 is provided between each of the semiconductor elements 10 and the carrier tape 1 .
  • the semiconductor elements 10 are sequentially located on the cutting regions 5 of the carrier tape 1 in accordance with the criterial holes 19 formed on the long edge region 2 a as in the first preferred embodiment.
  • the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at half the standardized pitches of 4.75 mm.
  • a plurality of the COF type semiconductor devices 21 which has the total device size T of 14.6 mm are manufactured with the carrier tape 1 .
  • the value of the criterial hole pitch L can be set to 16.625 mm as described in the first preferred embodiment.
  • the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm, the value of the criterial hole pitch L is set to 19 mm. Therefore, when the same number of pieces of the COF type semiconductor devices 21 is manufactured in the related art and the present invention, the entire length of the carrier tape 1 in the present invention can be shortened by 12.5% of the entire length of the carrier tape in the related art. As a result, the cost of the carrier tape is reduced.
  • the carrier tape 1 which has an entire length of 40 m.
  • the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at a half of the standardized pitch of 4.75 mm and that an extraction rate of the carrier tape 1 is 95%.
  • 2285 pieces of the COF type semiconductor devices 21 are manufactured from one roll of the carrier tape 1 .
  • the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm
  • 2000 pieces of the COF type semiconductor devices 21 are manufactured from one roll of the carrier tape 1 . That is, the COF type semiconductor devices can be manufactured in the present invention about 1.14 times as many as in the related art. Therefore, the exchange frequency of the carrier tape can be decreased. As a result, the productive efficiency of the semiconductor devices is improved as in the first preferred embodiment.
  • the carrier tape which has a plurality of the first holes arranged on a line at the standardized pitches, includes a plurality of the second holes arranged on the same line as the first holes at the standardized pitches. Moreover, each of the second holes is located between adjacent first holes. Therefore, a plurality of the cutting regions, in which the COF type semiconductor elements are respectively located, can be set on the carrier tape at shorter pitches. As a result, the entire length of the carrier tape can be shortened, and thus the cost of the carrier tape is reduced. Also, the exchange frequency of the carrier tape can be decreased, and thus productive efficiency of the COF type semiconductor devices is improved. Also, in the present invention, a plurality of the second holes can be formed in the carrier tape which previously has a purality of the first holes arranged at the standardized pitches without sophisticated changes of design. Therefore, the carrier tape which produces the above mentioned effects can be easily realized.
  • FIG. 5 is a plain view for describing a tape carrier package which includes a semiconductor element according to a thid preferred embodiment of the present invention.
  • FIG. 6 is a cross-sectional view along a dashed line III-III′ of the tape carrier package of FIG. 5 .
  • a plurality of semiconductor elements 31 are respectively mounted on the cutting regions 5 without forming the device holes in the carrier tape 1 . Then, each of the cutting regions 5 is separated from the carrier tape 1 as in the first preferred embodiment.
  • each of these types of semiconductor devices 31 is called a Ball Grid Array (hereinafter referred to as “BGA”) type semiconductor device.
  • the configurations of the first holes 3 and the second holes 17 are the same as those according to the first and second preferred embodiment.
  • the semiconductor element 10 has a top surface where a plurality of electrode pads 32 are formed and a rear surface opposite to the top surface.
  • the carrier tape 1 has a plurality of wiring patterns 33 which are formed on the semiconductor element locating region 2 b through a first adhesive layer 38 .
  • the wiring patterns 33 are covered with a solder resist layer 36 .
  • the semiconductor elements 10 are located on the solder resist layer 36 through a second adhesive layer 39 .
  • the electrode pads 32 of the semiconductor element 10 are connected with the wiring patterns 33 by a plurality of bonding wires 34 .
  • On opposite sides of the wiring patterns 33 are a plurality of land patterns 35 .
  • the carrier tape 1 has a plurality of land openings 41 in each of the cutting regions 5 , and the land patterns 35 are exposed from the land openings 41 .
  • a plurality of external electrodes 40 are formed on the land patterns 35 through the opening 41 .
  • two of the semiconductor elements 10 are mounted on the carrier tape 1 in a direction perpendicular to the longitudinal direction in which the transferring movement of the carrier tape 1 is executed. That is, every two of the semiconductor elements 10 is located in the cutting regions 5 based on the criterial hole 19 .
  • the electrode pads 32 are connected with the wiring patterns 33 by the bonding wires 34 , and then, the semiconductor elements 10 are covered with molding resin 37 .
  • the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at a half of the standardized pitch of 4.75 mm as in the first and second preferred embodiments.
  • the cutting regions 5 can be located on the carrier tape 1 at pitches defined by five adjacent first holes 3 and second holes 17 in the present invention. That is, in this example, the value of the criterial hole pitch L can be set to 11.875 mm.
  • the cutting regions 5 are located on the carrier tape 1 at pitches defined by three adjacent first holes 3 .
  • Each of these pitches corresponds to a pitch defined by six adjacent first holes 3 and second holes 17 in the present invention. That is, the value of the criterial hole pitch L is set to 14.25 mm. Therefore, when the same number of pieces of the BGA type semiconductor devices 31 is manufactured in the related art and the present invention, the entire length of the carrier tape 1 in the present invention can be shortened by 16.7% of the entire length of the carrier tape in the related art. As a result, the cost of the carrier tape is reduced.
  • a plurality of the BGA type semiconductor devices 31 which has a total device size T of 11.189 mm are manufactured with the carrier tape 1 which has an entire length of 40 m.
  • the carrier tape 1 has the first holes 3 and the second holes 17 which are alternatively arranged at a half of the standardized pitch of 4.75 mm and that an extraction rate of the carrier tape 1 is 95%.
  • 6400 pieces of the BGA type semiconductor devices 31 are manufactured from one roll of the carrier tape 1 .
  • the carrier tape 1 has only the first holes 3 which are arranged at the standardized pitches of 4.75 mm
  • 5332 pieces of the BGA type semiconductor devices 31 are manufactured from one roll of the carrier tape 1 .
  • the number of the BGA type semiconductor devices that can be manufactured in the present invention is about 1.20 times the related art. Therefore, the exchange frequency of the carrier tape can be decreased. As a result, it can be realized that the productive efficiency of the semiconductor devices is improved as in the first and second preferred embodiments.
  • the carrier tape which has a plurality of the first holes arranged on a line at the standardized pitches, includes a plurality of the second holes arranged on the same line as the first holes are at the standardized pitches. Moreover, each of the second holes is located between adjacent first holes. Therefore, a plurality of the cutting regions, in which the BGA type semiconductor elements are respectively located, can be set on the carrier tape at shorter pitches. As a result, the entire length of the carrier tape can be shortened, and thus the cost of the carrier tape is reduced. Also, the exchange frequency of the carrier tape can be decreased, and thus the productive efficiency of the BGA type semiconductor devices is improved. Also, in the present invention, a plurality of the second holes can be formed in the carrier tape which previously has a purality of the first holes arranged at the standardized pitches without sophisticated changes of design. Therefore, the carrier tape which produces the above mentioned effects can be easily realized.
  • each of the second holes 17 may be arranged so as to be closer to either one of the adjacent first holes 3 as long as the second holes 17 are spaced at the regular pitch P as shown in FIG. 7 .
  • one second hole 17 and one third hole 22 may be arranged between the adjacent first holes 3 at regular intervals R as shown in FIG. 8 .
  • any pitch of adjacent second holes 17 or adjacent third holes 22 is substantially equal to the regular pitch P of the adjacent first holes 3 . Therefore, the criterial hole pitches can be more finely defined. As a result, the cost of the carrier tape can be further cut down and the productive efficiency of the semiconductor devices can be further improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
US11/073,766 2004-05-11 2005-03-08 Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape Abandoned US20050252828A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004141401A JP4070135B2 (ja) 2004-05-11 2004-05-11 テープキャリア、半導体装置の製造方法および半導体装置
JP141401/2004 2004-05-11

Publications (1)

Publication Number Publication Date
US20050252828A1 true US20050252828A1 (en) 2005-11-17

Family

ID=35308395

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/073,766 Abandoned US20050252828A1 (en) 2004-05-11 2005-03-08 Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape

Country Status (4)

Country Link
US (1) US20050252828A1 (zh)
JP (1) JP4070135B2 (zh)
KR (1) KR101162939B1 (zh)
CN (1) CN1697164B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102673839A (zh) * 2012-05-18 2012-09-19 昆山诚业德精密模具有限公司 屏蔽罩平面度自动检测和吸塑盘包装一体机
CN103187385A (zh) * 2011-12-30 2013-07-03 联咏科技股份有限公司 薄膜覆晶封装的衬底
US20140069697A1 (en) * 2010-12-03 2014-03-13 Nederlandse Organisatie Voor Toegepast-Natuurweten Method and apparatus for assembling electric components on a flexible substrate as well as assembly of an electric component with a flexible substrate

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4283292B2 (ja) * 2006-09-08 2009-06-24 シャープ株式会社 半導体装置用テープキャリア、および半導体装置の製造方法
CN102673822B (zh) * 2012-05-18 2013-11-06 昆山诚业德通讯科技有限公司 屏蔽罩平面度自动检测和载带包装一体机
KR101791356B1 (ko) * 2016-09-20 2017-10-30 김부욱 차단기용 접촉자 제조 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2536153A (en) * 1947-02-04 1951-01-02 Time Inc Electronic register control for web pasting
US6589817B1 (en) * 1996-12-03 2003-07-08 Oki Electric Industry Co., Ltd. Semiconductor device, method for manufacturing the same, and method for mounting the same
US6887330B2 (en) * 2002-07-09 2005-05-03 Hitachi High-Tech Electronics Engineering Co., Ltd. Machine for punching out electronic circuitry parts, method for replacing tape supply reels, and method for producing electronic circuitry parts from tape
US6911729B1 (en) * 1999-05-14 2005-06-28 Sharp Kabushiki Kaisha Tape carrier semiconductor device
US7171744B2 (en) * 2003-09-01 2007-02-06 Oki Electric Industry Co., Ltd. Substrate frame

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2836208B2 (ja) * 1990-07-10 1998-12-14 日本電気株式会社 フィルムキャリアテープ
JP3398106B2 (ja) 1999-12-24 2003-04-21 株式会社鈴木 電子部品用フイルムの孔明け加工方法
JP4080683B2 (ja) * 2000-10-12 2008-04-23 三井金属鉱業株式会社 フィルムキャリア形成用テープおよび電子部品実装用フィルムキャリアテープ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2536153A (en) * 1947-02-04 1951-01-02 Time Inc Electronic register control for web pasting
US6589817B1 (en) * 1996-12-03 2003-07-08 Oki Electric Industry Co., Ltd. Semiconductor device, method for manufacturing the same, and method for mounting the same
US6911729B1 (en) * 1999-05-14 2005-06-28 Sharp Kabushiki Kaisha Tape carrier semiconductor device
US6887330B2 (en) * 2002-07-09 2005-05-03 Hitachi High-Tech Electronics Engineering Co., Ltd. Machine for punching out electronic circuitry parts, method for replacing tape supply reels, and method for producing electronic circuitry parts from tape
US7171744B2 (en) * 2003-09-01 2007-02-06 Oki Electric Industry Co., Ltd. Substrate frame

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140069697A1 (en) * 2010-12-03 2014-03-13 Nederlandse Organisatie Voor Toegepast-Natuurweten Method and apparatus for assembling electric components on a flexible substrate as well as assembly of an electric component with a flexible substrate
US9338894B2 (en) * 2010-12-03 2016-05-10 Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno Method and apparatus for assembling electric components on a flexible substrate as well as assembly of an electric component with a flexible substrate
CN103187385A (zh) * 2011-12-30 2013-07-03 联咏科技股份有限公司 薄膜覆晶封装的衬底
CN102673839A (zh) * 2012-05-18 2012-09-19 昆山诚业德精密模具有限公司 屏蔽罩平面度自动检测和吸塑盘包装一体机

Also Published As

Publication number Publication date
CN1697164A (zh) 2005-11-16
KR101162939B1 (ko) 2012-07-05
JP4070135B2 (ja) 2008-04-02
JP2005322852A (ja) 2005-11-17
CN1697164B (zh) 2010-04-28
KR20060043637A (ko) 2006-05-15

Similar Documents

Publication Publication Date Title
US20050252828A1 (en) Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape
JP3649993B2 (ja) 半導体装置及び半導体装置の製造方法
US7208821B2 (en) Multichip leadframe package
US7615409B2 (en) Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US20070158799A1 (en) Interconnected IC packages with vertical SMT pads
US7049687B2 (en) Tape carrier package having stacked semiconductor elements, and short and long leads
US6574858B1 (en) Method of manufacturing a chip package
US20050116327A1 (en) Method of manufacturing a semiconductor device
US20010042924A1 (en) Semiconductor package
US4927491A (en) Method of bonding IC unit
US8101470B2 (en) Foil based semiconductor package
US6897092B2 (en) Method of supporting a substrate film
US20020104684A1 (en) Tape circuit board and semiconductor chip package including the same
JP4439598B2 (ja) フィルムキャリアテープの搬送装置
US4564582A (en) Method for making carrier tape
US20230062701A1 (en) Semiconductor assemblies with system and methods for aligning dies using registration marks
JP2006157049A (ja) フィルムキャリアテープ、フィルムキャリアテープの製造方法、ｉｃモジュールを搭載したフィルムキャリアテープ及びｉｃモジュールを搭載したフィルムキャリアテープの製造方法
JP2731292B2 (ja) 搬送テープ及びその製造方法
JP2836208B2 (ja) フィルムキャリアテープ
KR100351919B1 (ko) 반도체 패키지의 제조방법
JPH01256138A (ja) キャリアテープおよびその使用方法
JP2734761B2 (ja) Ｔａｂフィルムキャリヤ及びｔａｂ実装半導体装置のインナーリードボンディング方法
JPS60160625A (ja) 半導体装置の製造方法
JPH01155632A (ja) テープキャリア式半導体装置
JPH01170028A (ja) 電子装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKAHASHI, YOSHIKAZU;REEL/FRAME:016364/0600

Effective date: 20050214

AS Assignment

Owner name: OKI SEMICONDUCTOR CO., LTD., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022092/0903

Effective date: 20081001

Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022092/0903

Effective date: 20081001

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION

AS Assignment

Owner name: LAPIS SEMICONDUCTOR CO., LTD., JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:OKI SEMICONDUCTOR CO., LTD;REEL/FRAME:032495/0483

Effective date: 20111003