US20050224942A1 - Semiconductor device with a plurality of ground planes - Google Patents

Semiconductor device with a plurality of ground planes Download PDF

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Publication number
US20050224942A1
US20050224942A1 US10/810,510 US81051004A US2005224942A1 US 20050224942 A1 US20050224942 A1 US 20050224942A1 US 81051004 A US81051004 A US 81051004A US 2005224942 A1 US2005224942 A1 US 2005224942A1
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chip
mcm
chips
ground plane
substrate
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US10/810,510
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English (en)
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Fan Ho
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SCA IPLA Holdings Inc
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Individual
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Assigned to INAPAC TECHNOLOGY, INC. reassignment INAPAC TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HO, FAN
Priority to US10/810,510 priority Critical patent/US20050224942A1/en
Application filed by Individual filed Critical Individual
Priority to KR1020050027896A priority patent/KR101120211B1/ko
Priority to JP2005125649A priority patent/JP2005286345A/ja
Priority to TW094109618A priority patent/TWI367550B/zh
Priority to CNA2005100697435A priority patent/CN1702861A/zh
Priority to EP05006797A priority patent/EP1580810A2/en
Publication of US20050224942A1 publication Critical patent/US20050224942A1/en
Priority to US12/346,437 priority patent/US7808092B2/en
Assigned to RAMBUS INC. reassignment RAMBUS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INAPAC TECHNOLOGY, INC.
Priority to JP2012027997A priority patent/JP2012094919A/ja
Assigned to SCA IPLA HOLDINGS INC. reassignment SCA IPLA HOLDINGS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAMBUS INC.
Priority to JP2014161289A priority patent/JP2014207488A/ja
Abandoned legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • E—FIXED CONSTRUCTIONS
    • E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02F—DREDGING; SOIL-SHIFTING
    • E02F3/00—Dredgers; Soil-shifting machines
    • E02F3/04—Dredgers; Soil-shifting machines mechanically-driven
    • E02F3/96—Dredgers; Soil-shifting machines mechanically-driven with arrangements for alternate or simultaneous use of different digging elements
    • E02F3/963—Arrangements on backhoes for alternate use of different tools
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G01R31/3161—Marginal testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to integrated circuits, and more specifically to a semiconductor device with a plurality of ground planes.
  • a multi-chip module comprises a plurality of IC chips on a common or shared substrate, all contained within the same protective package.
  • the individual IC chips in an MCM are interconnected by metallic paths formed on the substrate.
  • the IC chips are coupled to terminals on the substrate, which may be coupled to a conventional lead frame with very thin wires.
  • the substrate and lead frame are encapsulated within the protective package.
  • each IC chip in the MCM may be coupled to its own power plane, which is separate from other power planes coupled to the other IC chips in the MCM. According to previously developed techniques, all of the IC chips share a single ground plane on the MCM substrate.
  • testing of an MCM may be performed at a chip level, a package level or a system level (board level).
  • Conventional testing of MCMs with IC chips, such as IC memory chips usually occurs at the chip level. That is, each IC chip is manufactured and tested separately prior its incorporation in an MCM.
  • Conventional testing methods may be time-consuming; restricted to simple, non-complex components; and/or require extra components for testing.
  • Package-level testing has not been performed. System-level testing of MCMs is prohibitively expensive.
  • an MCM comprises an IC memory chip and an ASIC.
  • the IC memory chip and ASIC chip may share a set of input/output (I/O) connectors (e.g., pins, pads, or balls) of the MCM.
  • I/O input/output
  • a method separately accesses and tests the IC memory chip and the ASIC chip.
  • the MCM comprises a first integrated circuit (IC) chip on a substrate, a first ground plane coupled to the first IC chip, a second IC chip on the substrate, and a second ground plane coupled to the second IC chip.
  • IC integrated circuit
  • Another aspect of the invention relates to a method of testing first and second integrated circuit (IC) chips on a substrate in a multi-chip module.
  • Each IC chip has its own ground plane.
  • the method comprises testing the first IC chip without affecting an operation of the second IC chip; and testing the second IC chip without affecting an operation of the first IC chip.
  • Another aspect of the invention relates to a method of testing first and second integrated circuit (IC) chips on a substrate in a multi-chip module.
  • Each IC chip has its own ground plane.
  • the method comprises testing the first IC chip without being affected by an operation of the second IC chip; and testing the second IC chip without being affected by an operation of the first IC chip.
  • Another aspect of the invention relates to a method of testing an interconnect between first and second integrated circuit (IC) chips on a substrate in a multi-chip module.
  • Each IC chip has its own ground plane.
  • the method comprises applying a signal to the first IC chip and determining whether current is passed from the first IC chip to the second chip via the interconnect in response to the signal applied to the first IC chip.
  • FIG. 1 illustrates one embodiment of a multi-chip module (MCM) with a plurality of integrated circuits (ICs), according to an embodiment of the invention.
  • MCM multi-chip module
  • ICs integrated circuits
  • FIG. 2 illustrates one embodiment of an IC chip structure that may be implemented in an MCM, according to an embodiment of the invention.
  • FIG. 3 illustrates one embodiment of a multiple IC chip structure that may be implemented in an MCM, according to an embodiment of the invention.
  • FIG. 4 is a cross-sectional side view of another embodiment of a multiple IC chip structure that may be implemented in an MCM, according to an embodiment of the invention.
  • FIGS. 1 through 4 of the drawings Like numerals are used for like and corresponding parts of the various drawings.
  • the present invention recognizes a need for cost-effective testing of integrated circuit (IC) chips (also referred to as “dies”) in an MCM package (also called a “packaged device,” a “packaged semiconductor device” or a “multi-chip semiconductor device”).
  • IC integrated circuit
  • MCM multi-chip semiconductor device
  • Other aspects of testing systems, methods, and MCM structures are described in U.S. patent application Ser. No. 09/666,208, filed on Sep. 21, 2000, entitled “Chip Testing Within a Multi-Chip Semiconductor Package,” U.S. patent application Ser. No. 09/967,389, filed on Sep. 28, 2001, entitled “Testing of Integrated Circuit Devices,” U.S. patent application Ser. No. 10/305,635, filed on Nov.
  • each IC chip within an MCM has its own ground plane/layer on the MCM substrate.
  • IC chips with their own ground planes advantageously facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips in the MCM.
  • IC chips with their own ground planes allow customers to test IC chips, such as memory chips, in an MCM to determine whether a customer's product with an MCM is functioning properly.
  • IC chips with their own ground planes also facilitate testing of interconnects or connections between two or more chips in the MCM.
  • IC chips with their own ground planes also allow many different types of application-specific integrated circuits (ASICs), even ASICs without high impedance inputs, to be implemented in an MCM.
  • ASICs application-specific integrated circuits
  • FIG. 1 illustrates one embodiment of a multi-chip module (MCM) 100 , in accordance with the present invention.
  • MCM 100 may also referred to as a “packaged device,” a “packaged semiconductor device,” a “multi-chip semiconductor device” or a “system in package” (SIP).
  • MCM 100 can be packaged as a standard ball grid array (BGA) or thin quad flatpack (TQFP) having 144 pins or more.
  • BGA ball grid array
  • TQFP thin quad flatpack
  • the packaging may have a ceramic base with wire bonding or employing thin film substrates, and mounting on a silicon substrate or a printed circuit board (PCB) substrate.
  • PCB printed circuit board
  • the packaging may further utilize various surface mount technologies such as a single in-line package (SIP), dual in-line package (DIP), zig-zag in-line package (ZIP), plastic leaded chip carrier (PLCC), small outline package (SOP), thin SOP (TSOP), flatpack, and quad flatpack (QFP), to name but a few, and utilizing various leads (e.g., J-lead, gull-wing lead) or BGA type connectors.
  • SIP single in-line package
  • DIP dual in-line package
  • ZIP zig-zag in-line package
  • PLCC plastic leaded chip carrier
  • SOP small outline package
  • TSOP thin SOP
  • QFP quad flatpack
  • the MCM 100 comprises input/output (I/O) connectors 102 A- 102 N, a substrate 104 , and integrated circuit (IC) chips (also referred to as “dies”) 108 A- 108 C.
  • I/O connector 102 A- 102 N can comprise an I/O pin, a ball (of a ball grid array (BGA)), or other suitable connector for the transfer of signals into and out of MCM 100 .
  • MCM 100 may comprise a plastic ball grid array (PBGA) or other suitable packaging.
  • PBGA plastic ball grid array
  • Substrate 104 can be a printed circuit board (PCB) substrate, onto which IC chips 108 A- 108 C can be mounted.
  • PCB printed circuit board
  • a plurality of bonding pads or terminals 101 A- 101 N and interconnectors/traces/leads 110 A- 110 C, 112 A- 112 C may be incorporated in or formed on substrate 104 .
  • Connectors/traces/leads 110 A- 110 C, 112 A- 112 C may function to connect, and support communication between, IC chips 108 A- 108 C.
  • a number of bonding pads or terminals 101 A- 101 N may be connected to one or more I/O connectors 102 A- 102 N via leads 103 A- 103 N, thus supporting communication between substrate 104 and circuitry external to MCM 100 .
  • At least one IC chip 108 in FIG. 1 is a memory chip, and at least one IC chip 108 is an application-specific integrated circuit (ASIC) chip.
  • ASIC application-specific integrated circuit
  • the IC chips 108 A, 108 C can be memory chips and the IC chip 108 B can be an ASIC chip.
  • the IC memory chip(s) 108 A, 108 C and the ASIC chip 108 B may share some of the same pins/balls/pads 102 A- 102 N of the MCM 100 .
  • the MCM 100 may comprise various combinations of different types of ASICs, even ASICs without high impedance inputs pads or input pins.
  • at least one IC chip 108 in FIG. 1 may comprise logic and embedded memory, such as an embedded dynamic random access memory (DRAM).
  • DRAM embedded dynamic random access memory
  • Each IC chip 108 A- 108 C may comprise, or have incorporated therein, one or more bonding pads/terminals 118 A- 118 C. Bonding wires 120 A- 120 C or other suitable connections connect bonding pads/terminals 118 of IC chips 108 to bonding pads/terminals 101 of substrate 104 .
  • the MCM 100 may comprise any number of I/O pins/pads/balls, bonding pads, wires, leads, terminals, traces, ground planes, IC chips, interconnects/connections and power planes.
  • the MCM 100 may comprise other components (not shown) in addition to or instead of the components shown in FIG. 1 .
  • the MCM 100 has multiple layers.
  • a number of conductive plans 106 A- 106 C, 114 A- 114 C are provided, or incorporated, on substrate 104 .
  • planes 106 A- 106 C are ground planes and planes 114 A- 114 E are power planes.
  • the structures 114 A- 114 C are ground planes, and the structures 106 A- 106 C are power planes.
  • each IC chip 108 may have its own power plane 114 and its own ground plane 106 on the MCM substrate 104 .
  • Each power plane 114 is separate from the corresponding ground plane 106 .
  • each power plane 114 may have a voltage of 1.8 volts, 3.3 volts or 5 volts.
  • one or more conductive plans can be implemented as layers formed on the substrate 104 , for example, by processes that are typically used to form traces on a printed circuit board (PCB). Also, in the same or other embodiments, one or more conductive plans can be implemented as a conductive mesh or strip which is attached to the substrate, for example, by any suitable bonding process.
  • Each IC chip 108 may be bonded or otherwise attached to one or more power planes 114 . Similarly, each IC chip 108 may be bonded or otherwise attached to one or more ground planes 106 .
  • each chip 108 may be attached to one or more power planes 114 and/or one or more ground planes 106 via a “flip chip” attachment technique, which is known to those of ordinary skill in the art.
  • Each chip 108 and its associated ground and power plans may form or be part of a “chip structure.”
  • a ground plane in accordance with embodiments of the invention, may be located anywhere in the MCM and does not need to be near a corresponding IC chip.
  • the ground plane 106 A may be located anywhere in the MCM 100 and does not have to be near the chip 108 A.
  • a ground plane 106 is implemented on the surface of the substrate.
  • a ground plane 106 is implemented in a portion within the substrate beneath its surface.
  • Each ground plane 106 can be coupled to an external connector of the MCM 100 , such as I/O connector 102 A.
  • a ground plane 106 may have any configuration and any shape, such as a strip or a layer.
  • the size of each ground plane 106 in an MCM may vary according to the power consumption of a chip associated with the ground plane. Thus, in one embodiment, a larger ground plane 106 will be provided for a chip which consumes more power, and a smaller ground plane 106 will be provided for a chip which consumes less power.
  • Each ground plane 106 may be made of a metal, such as copper, aluminum, gold or tungsten, or any other suitable conductive material.
  • a ground plane 106 may be substantially solid (e.g., a single “sheet”) or partially divided into a plurality of interconnected pieces (e.g., a grid, a mesh or a perforated design).
  • a ground plane 106 may be flexible or non-flexible (rigid).
  • FIG. 2 illustrates one embodiment of an IC chip structure 200 that may be implemented in the MCM 100 of FIG. 1 .
  • the structure 200 in FIG. 2 comprises a first conductive plane 202 , a second conductive plane 204 , a third conductive plane 206 and an IC chip 208 .
  • the conductive planes 202 , 204 , 206 may comprise a ground plane and two power planes with two voltage levels, such as 1.8, 3.3 or 5 volts.
  • Conductive plans 202 , 204 , and 206 may be separated (e.g., electrically isolated) with suitable insulative or non-conductive layers (not shown).
  • FIG. 2 illustrates an IC chip structure 200 having multiple power planes.
  • FIG. 3 illustrates one embodiment of a multiple IC chip structure 300 that may be implemented in the MCM 100 of FIG. 1 .
  • the structure 300 in FIG. 3 comprises a plurality of conductive planes 301 , 302 , 304 A, 304 B, 306 A, 306 B and a plurality of IC chips 308 A, 308 B.
  • Conductive plans 301 , 302 , 304 A, 304 B, 306 A, 306 B may be separated (e.g., electrically isolated) with suitable insulative or non-conductive layers (not shown).
  • Each IC chip 308 in FIG. 3 may be provided with its own ground plane and one or more power planes.
  • the chip 308 A may be coupled to a ground plane 306 A and three power planes 304 A, 302 , 301 .
  • the voltage levels of the power planes 304 A, 302 , 301 may be 1.8, 3.3 or 5 volts (in any desired order).
  • FIG. 3 demonstrates that a plurality of IC chips 308 A, 308 B may share at least one power plane, such as the plane 302 or the plane 301 .
  • the chip 308 A may be coupled to the chip 308 B via interconnects 310 .
  • FIG. 4 is a cross-sectional side view of another embodiment of a multiple IC chip structure 400 that may be implemented in the MCM 100 of FIG. 1 .
  • the structure 400 in FIG. 4 comprises a first IC chip 401 A, a second IC chip 401 B, a plurality of layers or planes 402 A, 402 B, 404 , 406 A, 406 B and a substrate 412 .
  • the chips 401 A, 401 B, planes 402 A, 402 B, 404 , 406 A, 406 B and substrate 412 may be vertically separated by dielectric layers or layers of one or more insulative or non-conductive materials.
  • one or more of the planes 402 A, 402 B, 404 , 406 A, 406 B may be embedded in a part of the substrate 412 .
  • the chips 401 A, 401 B in FIG. 4 may be coupled via one or more connectors or leads or traces 408 .
  • the chips 401 A, 401 B may be coupled to the planes 402 A, 402 B, 404 , 406 A, 406 B connectors (e.g., vias) 410 A, 410 B.
  • the planes 402 A, 402 B, 404 are power planes
  • the planes 406 A, 406 B are ground planes.
  • the plane 404 may be a power plane shared by the two IC chips 401 A, 401 B.
  • the MCM 100 and structures described herein may be tested at a chip level, a package level or a system level. In some situations, it is desirable to test at the chip level because normal test routines designed for each chip can be used for testing, thus, allowing faulty chips to be identified and isolated or repaired.
  • a testing device accesses and tests each IC chip, such as the chip 108 B in FIG. 1 , separately from other chips, such as the chips 108 A, 108 C.
  • ground plane 106 B allows corresponding chip 108 B to be tested without affecting the operation or voltage/current levels of other chips, such as chips 108 A, 108 C.
  • each chip 108 in the MCM 100 of FIG. 1 can be activated (i.e., powered-up) and tested without supplying power to other chips 108 in the MCM 100 .
  • the ground planes described herein with reference to FIGS. 1-4 facilitate separate testing of each chip, such as chip 108 B ( FIG. 1 ), without being affected by the operation or voltage/current levels of other chips, such as chips 108 A, 108 C.
  • the various and separate ground planes allow for complete isolation between and among chips 108 .
  • the structures described above may also facilitate testing of interconnects/connections/traces between two or more chips, such as, for example, the interconnects 110 A- 110 C, 112 A- 112 C between chips 108 A, 108 B, 108 C in FIG. 1 .
  • a testing device tests the interconnects 110 A- 110 C, 112 A- 112 C by examining a current change on each interconnect 110 or 112 in response to a signal sent to a chip 108 .
  • a device tests the interconnects 110 A- 110 C, 112 A- 112 C by determining whether each interconnect 110 or 112 passes current. If an interconnect 110 or 112 does not pass current, then the interconnect has a broken connection. An MCM with a defective interconnect may be discarded or repaired.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
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  • Structural Engineering (AREA)
  • Mining & Mineral Resources (AREA)
  • Mechanical Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
US10/810,510 2004-03-26 2004-03-26 Semiconductor device with a plurality of ground planes Abandoned US20050224942A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
US10/810,510 US20050224942A1 (en) 2004-03-26 2004-03-26 Semiconductor device with a plurality of ground planes
KR1020050027896A KR101120211B1 (ko) 2004-03-26 2005-03-26 다수의 접지면을 구비한 반도체 장치
JP2005125649A JP2005286345A (ja) 2004-03-26 2005-03-28 複数の接地面を備えた半導体素子
TW094109618A TWI367550B (en) 2004-03-26 2005-03-28 A semiconductor device with a plurality of ground planes
CNA2005100697435A CN1702861A (zh) 2004-03-26 2005-03-28 一种具有多个接地平面的半导体器件
EP05006797A EP1580810A2 (en) 2004-03-26 2005-03-29 A semiconductor device with a plurality of ground planes
US12/346,437 US7808092B2 (en) 2004-03-26 2008-12-30 Semiconductor device with a plurality of ground planes
JP2012027997A JP2012094919A (ja) 2004-03-26 2012-02-13 複数の接地面を備えた半導体素子
JP2014161289A JP2014207488A (ja) 2004-03-26 2014-08-07 マルチチップ・モジュール

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US7808092B2 (en) 2010-10-05
JP2005286345A (ja) 2005-10-13
TWI367550B (en) 2012-07-01
KR20060045459A (ko) 2006-05-17
JP2012094919A (ja) 2012-05-17
TW200605296A (en) 2006-02-01
US20090108393A1 (en) 2009-04-30
CN1702861A (zh) 2005-11-30
KR101120211B1 (ko) 2012-03-19
EP1580810A2 (en) 2005-09-28
JP2014207488A (ja) 2014-10-30

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